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/linux/include/dt-bindings/pinctrl/
H A Dk210-fpioa.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 * kendryte-standalone-sdk/lib/drivers/include/fpioa.h
32 #define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */
33 #define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */
38 #define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */
39 #define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */
40 #define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */
41 #define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */
42 #define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */
43 #define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */
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/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Intel(R) Speed Select Technology User Guide
7 The Intel(R) Speed Select Technology (Intel(R) SST) provides a powerful new
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
21 and configure these features is by using the Intel Speed Select utility.
23 This document explains how to use the Intel Speed Select tool to enumerate and
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
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/linux/Documentation/hwmon/
H A Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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H A Daquacomputer_d5next.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver aquacomputer-d5next
14 * Aquacomputer High Flow Next sensor
19 * Aquacomputer High Flow USB flow meter
25 -----------
32 speed (in RPM), power, voltage and current. Temperature offsets and fan speeds
35 For the D5 Next pump, available sensors are pump and fan speed, power, voltage
37 available through debugfs are the serial number, firmware version and power-on
39 temperature curves directly from the pump. If it's not connected, the fan-related
49 as well as eight PWM controllable fans, along with their speed (in RPM), power, voltage
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H A Dw83792d.rst10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
35 -----------
42 parameter; this will put it into a more well-behaved state first.
44 The driver implements three temperature sensors, seven fan rotation speed
48 The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7
53 Automatic fan control mode is possible only for fan1-fan3.
55 For all pwmX outputs, a value of 0 means minimum fan speed and a value of
56 255 means maximum fan speed.
64 triggered if the rotation speed has dropped below a programmable limit. Fan
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-pci-drivers-ehci_hcd7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
15 Sometimes you want to force a high-speed device to connect
16 at full speed, which can be accomplished by forcing the
23 For example: To force the high-speed device attached to
24 port 4 on bus 2 to run at full speed::
28 To return the port to high-speed operation::
30 echo -4 >/sys/bus/usb/devices/usb2/../companion
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/linux/Documentation/usb/
H A Dehci.rst5 27-Dec-2002
7 The EHCI driver is used to talk to high speed USB 2.0 devices using
8 USB 2.0-capable host controller hardware. The USB 2.0 standard is
11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
15 USB 1.1 only addressed full speed and low speed. High speed devices
23 (TT) in the hub, which turns low or full speed transactions into
24 high speed "split transactions" that don't waste transfer bandwidth.
31 While usb-storage devices have been available since mid-2001 (working
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/linux/drivers/usb/gadget/udc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
24 # - discrete ones (including all PCI-only controllers)
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/linux/drivers/usb/gadget/function/
H A Du_uvc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
36 * Control descriptors array pointers for full-/high-speed and
37 * super-speed. They point by default to the uvc_fs_control_cls and
45 * Streaming descriptors array pointers for full-speed, high-speed and
46 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
47 * for configfs-based gadgets. Legacy gadgets must initialize them in
54 /* Default control descriptors for configfs-based gadgets. */
60 * Control descriptors pointers arrays for full-/high-speed and
61 * super-speed. The first element is a configurable control header
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/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed eUSB2 repeater on Qualcomm
174 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
177 Support for the USB high-speed ULPI compliant phy on Qualcomm
185 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
198 tristate "Qualcomm 28nm High-Speed PHY"
200 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
204 High-Speed PHY driver. This driver supports the Hi-Speed PHY which
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/linux/drivers/hid/intel-thc-hid/intel-quicki2c/
H A Dquicki2c-dev.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/hid-over-i2c.h>
68 * struct quicki2c_subip_acpi_parameter - QuickI2C ACPI DSD parameters
70 * @connection_speed: I2C device expected connection speed
83 * struct quicki2c_subip_acpi_config - QuickI2C ACPI DSD parameters
84 * @SMHX: Standard Mode (100 kbit/s) Serial Clock Line HIGH Period
88 * @FMHX: Fast Mode (400 kbit/s) Serial Clock Line HIGH Period
94 * @FPHX: Fast Mode Plus (1Mbit/sec) Serial Clock Line HIGH Period
98 * @HMHX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line HIGH Period
99 * @HMLX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line LOW Period
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/linux/Documentation/devicetree/bindings/usb/
H A Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
38 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
40 serial is specified and High-Speed Inter-Chip feature if HSIC is
46 maximum-speed:
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/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dhsta.txt2 ppc476gtr High Speed Serial Assist (HSTA) node
5 The 476gtr SoC contains a high speed serial assist module attached
6 between the plb4 and plb6 system buses to provide high speed data
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-usi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The USI IP-core provides configurable support for serial protocols, enabling
18 simultaneously in select combinations - High-Speed I2C0, High-Speed
19 I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed
23 High-Speed I2C.
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_sw.c36 dce_i2c_sw->ctx = ctx; in dce_i2c_sw_construct()
46 dal_gpio_get_value(ddc->pin_data, &value); in read_bit_from_ddc()
48 dal_gpio_get_value(ddc->pin_clock, &value); in read_bit_from_ddc()
61 dal_gpio_set_value(ddc->pin_data, value); in write_bit_to_ddc()
63 dal_gpio_set_value(ddc->pin_clock, value); in write_bit_to_ddc()
70 dal_ddc_close(dce_i2c_sw->ddc); in release_engine_dce_sw()
71 dce_i2c_sw->ddc = NULL; in release_engine_dce_sw()
120 --shift; in write_byte_sw()
123 /* The display sends ACK by preventing the SDA from going high in write_byte_sw()
125 * If the SDA goes high after that bit, it's a NACK in write_byte_sw()
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/linux/drivers/infiniband/hw/hfi1/
H A Dmad.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright(c) 2015 - 2017 Intel Corporation.
41 #define OPA_NOTICE_TRAP_LSE_CHG 0x04 /* Link Speed Enable changed */
101 u8 sl; /* SL: high 5 bits */
105 __be32 qp1; /* high 8 bits reserved */
106 __be32 qp2; /* high 8 bits reserved */
114 u8 sl; /* SL: high 5 bits */
118 __be32 qp1; /* high 8 bits reserved */
119 __be32 qp2; /* high 8 bits reserved */
299 * struct cc_state combines the (active) per-port congestion control
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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_cyclone5_chameleon96.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
28 compatible = "regulator-fixed";
29 regulator-name = "3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
35 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
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/linux/drivers/usb/dwc2/
H A Dhcd.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hcd.h - DesignWare HS OTG Controller host-mode declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
24 * struct dwc2_host_chan - Software host channel descriptor
30 * @speed: Device speed. One of the following values:
31 * - USB_SPEED_LOW
32 * - USB_SPEED_FULL
33 * - USB_SPEED_HIGH
35 * - USB_ENDPOINT_XFER_CONTROL: 0
36 * - USB_ENDPOINT_XFER_ISOC: 1
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/linux/Documentation/devicetree/bindings/clock/
H A Dgoogle,gs101-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Griffin <peter.griffin@linaro.org>
16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 'dt-bindings/clock/gs101.h' header.
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,snps-eusb2-repeater.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
19 - items:
20 - enum:
21 - qcom,pm7550ba-eusb2-repeater
22 - const: qcom,pm8550b-eusb2-repeater
23 - enum:
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H A Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
57 description: Pull-down/up setting to apply to the pin.
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/linux/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - mobileye,eyeq-sd4hc
20 - socionext,uniphier-sd4hc
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-exynos5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung's High Speed I2C controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's High Speed I2C controller is used to interface with I2C devices
19 Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details.
24 - enum:
25 - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
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