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/linux/drivers/gpu/drm/sprd/
H A Dsprd_dpu.h23 /* DPU Layer registers offset */
33 * Sprd DPU context structure
35 * @base: DPU controller base address
38 * @vm: videomode structure to use for DPU and DPI initialization
39 * @stopped: indicates whether DPU are stopped
40 * @wait_queue: wait queue, used to wait for DPU shadow register update done and
41 * DPU stop register done interrupt signal.
42 * @evt_update: wait queue condition for DPU shadow register
43 * @evt_stop: wait queue condition for DPU stop register
57 * Sprd DPU device structure
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm8650-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
7 title: Qualcomm SM8650 Display DPU
12 $ref: /schemas/display/msm/dpu-common.yaml#
18 - qcom,eliza-dpu
19 - qcom,glymur-dpu
20 - qcom,kaanapali-dpu
21 - qcom,sa8775p-dpu
22 - qcom,sm8650-dpu
23 - qcom,sm8750-dpu
24 - qcom,x1e80100-dpu
[all …]
H A Dqcom,sc7180-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
7 title: Qualcomm Display DPU on SC7180
12 $ref: /schemas/display/msm/dpu-common.yaml#
17 - qcom,sc7180-dpu
18 - qcom,sm6125-dpu
19 - qcom,sm6350-dpu
20 - qcom,sm6375-dpu
68 - qcom,sm6375-dpu
69 - qcom,sm6125-dpu
86 compatible = "qcom,sc7180-dpu";
H A Dqcom,sdm845-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
7 title: Qualcomm Display DPU on SDM845
12 $ref: /schemas/display/msm/dpu-common.yaml#
17 - qcom,sdm670-dpu
18 - qcom,sdm845-dpu
62 compatible = "qcom,sdm845-dpu";
H A Ddpu-common.yaml3 $id: http://devicetree.org/schemas/display/msm/dpu-common.yaml#
6 title: Qualcomm Display DPU common properties
14 Common properties for QCom DPU display controller.
38 Contains the list of output ports from DPU device. These ports
39 connect to interfaces that are external to the DPU hardware,
H A Dqcom,sm6115-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
7 title: Qualcomm Display DPU on SM6115
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm6115-dpu
62 compatible = "qcom,sm6115-dpu";
H A Dqcom,qcm2290-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
7 title: Qualcomm Display DPU on QCM2290
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,qcm2290-dpu
60 compatible = "qcom,qcm2290-dpu";
H A Dqcom,msm8998-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
7 title: Qualcomm Display DPU on MSM8998
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,msm8998-dpu
63 compatible = "qcom,msm8998-dpu";
H A Dqcom,sm6150-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml#
7 title: Qualcomm SM6150 Display DPU
13 $ref: /schemas/display/msm/dpu-common.yaml#
17 const: qcom,sm6150-dpu
51 compatible = "qcom,sm6150-dpu";
H A Dqcom,sm7150-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-dpu.yaml#
7 title: Qualcomm SM7150 Display Processing Unit (DPU)
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm7150-dpu
61 compatible = "qcom,sm7150-dpu";
H A Dqcom,sm6125-mdss.yaml14 like DPU display controller, DSI and DP interfaces etc.
54 const: qcom,sm6125-dpu
109 compatible = "qcom,sm6125-dpu";
H A Dqcom,sm6115-mdss.yaml14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
49 const: qcom,sm6115-dpu
106 compatible = "qcom,sm6115-dpu";
H A Dqcom,sm6375-mdss.yaml14 like DPU display controller, DSI and DP interfaces etc.
54 const: qcom,sm6375-dpu
106 compatible = "qcom,sm6375-dpu";
H A Dqcom,qcm2290-mdss.yaml14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
55 const: qcom,qcm2290-dpu
114 compatible = "qcom,qcm2290-dpu";
H A Dqcom,sm6350-mdss.yaml14 like DPU display controller, DSI and DP interfaces etc.
54 const: qcom,sm6350-dpu
115 compatible = "qcom,sm6350-dpu";
H A Dqcom,sm6150-mdss.yaml15 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
52 const: qcom,sm6150-dpu
116 compatible = "qcom,sm6150-dpu";
H A Dqcom,glymur-mdss.yaml14 DPU display controller, DP interfaces, etc.
47 const: qcom,glymur-dpu
110 compatible = "qcom,glymur-dpu";
/linux/Documentation/devicetree/bindings/display/sprd/
H A Dsprd,sharkl3-dpu.yaml4 $id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml#
7 title: Unisoc Sharkl3 Display Processor Unit (DPU)
13 DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
19 const: sprd,sharkl3-dpu
63 dpu: dpu@63000000 {
64 compatible = "sprd,sharkl3-dpu";
H A Dsprd,display-subsystem.yaml14 DPU devices or other display interface nodes that comprise the
52 of DPU devices.
/linux/drivers/vdpa/solidrun/
H A Dsnet_ctrl.c3 * SolidRun DPU driver for control plane
34 /* Control register used to read data from the DPU */
112 /* Wait until the DPU finishes completely. in snet_wait_for_dpu_completion()
118 /* Reading ctrl from the DPU:
123 * (1) Verify that the DPU is not in the middle of another operation by
184 SNET_WARN(pdev, "Error while reading control data from DPU, err %d\n", ret); in snet_ctrl_read_from_dpu()
208 SNET_WARN(pdev, "Timeout waiting for the DPU to complete a control command\n"); in snet_ctrl_read_from_dpu()
215 /* Send a control message to the DPU using the old mechanism
227 * Make sure that the opcode register is empty, and that the DPU isn't in snet_send_ctrl_msg_old()
239 /* DPU ACKs the message by clearing the opcode register */ in snet_send_ctrl_msg_old()
[all …]
H A Dsnet_main.c3 * SolidRun DPU driver for control plane
14 /* SNET DPU device ID */
27 /* How long should we wait for the DPU to read our config */
29 /* Size of configs written to the DPU */
178 * Return 0 only if this is the initial state we use in the DPU. in snet_set_vq_state()
215 /* If DPU started, destroy it */ in snet_reset_dev()
341 * Magic number should be written last, this is the DPU indication that the data is ready in snet_write_conf()
386 /* The DPU will ACK the config by clearing the signature */ in snet_write_conf()
390 SNET_ERR(snet->pdev, "Timeout waiting for the DPU to read the config\n"); in snet_write_conf()
394 /* set DPU flag */ in snet_write_conf()
[all …]
H A Dsnet_vdpa.h3 * SolidRun DPU driver for control plane
46 /* IRQ index, DPU uses this to parse data from MSI-X table */
75 /* IRQ index, DPU uses this to parse data from MSI-X table */
194 /* The DPU expects a 64bit integer in 2 halves, the low part first */ in snet_write64()
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
H A Dpipeline.json10 …"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB…
15 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being proce…
20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p…
25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json9 …n issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and the…
12 …n issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and the…
15 …ion issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and the…
18 …ion issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and the…
21 …ed due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and the…
24 …ed due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and the…
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dpipeline.json21 …, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue …
24 …, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue …
27 …sued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue i…
30 …sued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue i…

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