xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8650 Display DPU
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12$ref: /schemas/display/msm/dpu-common.yaml#
13
14properties:
15  compatible:
16    enum:
17      - qcom,sm8650-dpu
18      - qcom,x1e80100-dpu
19
20  reg:
21    items:
22      - description: Address offset and size for mdp register set
23      - description: Address offset and size for vbif register set
24
25  reg-names:
26    items:
27      - const: mdp
28      - const: vbif
29
30  clocks:
31    items:
32      - description: Display hf axi
33      - description: Display MDSS ahb
34      - description: Display lut
35      - description: Display core
36      - description: Display vsync
37
38  clock-names:
39    items:
40      - const: nrt_bus
41      - const: iface
42      - const: lut
43      - const: core
44      - const: vsync
45
46required:
47  - compatible
48  - reg
49  - reg-names
50  - clocks
51  - clock-names
52
53unevaluatedProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/interrupt-controller/arm-gic.h>
58    #include <dt-bindings/power/qcom,rpmhpd.h>
59
60    display-controller@ae01000 {
61        compatible = "qcom,sm8650-dpu";
62        reg = <0x0ae01000 0x8f000>,
63              <0x0aeb0000 0x2008>;
64        reg-names = "mdp", "vbif";
65
66        clocks = <&gcc_axi_clk>,
67                 <&dispcc_ahb_clk>,
68                 <&dispcc_mdp_lut_clk>,
69                 <&dispcc_mdp_clk>,
70                 <&dispcc_vsync_clk>;
71        clock-names = "nrt_bus",
72                      "iface",
73                      "lut",
74                      "core",
75                      "vsync";
76
77        assigned-clocks = <&dispcc_vsync_clk>;
78        assigned-clock-rates = <19200000>;
79
80        operating-points-v2 = <&mdp_opp_table>;
81        power-domains = <&rpmhpd RPMHPD_MMCX>;
82
83        interrupt-parent = <&mdss>;
84        interrupts = <0>;
85
86        ports {
87            #address-cells = <1>;
88            #size-cells = <0>;
89
90            port@0 {
91                reg = <0>;
92                dpu_intf1_out: endpoint {
93                    remote-endpoint = <&dsi0_in>;
94                };
95            };
96
97            port@1 {
98                reg = <1>;
99                dpu_intf2_out: endpoint {
100                    remote-endpoint = <&dsi1_in>;
101                };
102            };
103        };
104
105        mdp_opp_table: opp-table {
106            compatible = "operating-points-v2";
107
108            opp-200000000 {
109                opp-hz = /bits/ 64 <200000000>;
110                required-opps = <&rpmhpd_opp_low_svs>;
111            };
112
113            opp-325000000 {
114                opp-hz = /bits/ 64 <325000000>;
115                required-opps = <&rpmhpd_opp_svs>;
116            };
117
118            opp-375000000 {
119                opp-hz = /bits/ 64 <375000000>;
120                required-opps = <&rpmhpd_opp_svs_l1>;
121            };
122
123            opp-514000000 {
124                opp-hz = /bits/ 64 <514000000>;
125                required-opps = <&rpmhpd_opp_nom>;
126            };
127        };
128    };
129...
130