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/linux/Documentation/scsi/
H A Dbfa.rst16 1657:0013:1657:0014 425 4Gbps dual port FC HBA
17 1657:0013:1657:0014 825 8Gbps PCIe dual port FC HBA
18 1657:0013:103c:1742 HP 82B 8Gbps PCIedual port FC HBA
19 1657:0013:103c:1744 HP 42B 4Gbps dual port FC HBA
20 1657:0017:1657:0014 415 4Gbps single port FC HBA
21 1657:0017:1657:0014 815 8Gbps single port FC HBA
22 1657:0017:103c:1741 HP 41B 4Gbps single port FC HBA
23 1657:0017:103c 1743 HP 81B 8Gbps single port FC HBA
24 1657:0021:103c:1779 804 8Gbps FC HBA for HP Bladesystem c-class
26 1657:0014:1657:0014 1010 10Gbps single port CNA - FCOE
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dapm,xgene-phy.yaml7 title: APM X-Gene 15Gbps Multi-purpose PHY
13 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
26 Possible values are 0 (SATA), 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
146 0 = 1-2Gbps
147 1 = 2-4Gbps (1st tuple default)
148 2 = 4-8Gbps
149 3 = 8-15Gbps (2nd tuple default)
150 4 = 2.5-4Gbps
151 5 = 4-5Gbps
152 6 = 5-6Gbps
[all …]
/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h112 VSR_PHY_STAT = 0x00 * 4, /* Phy Interrupt Status */
113 VSR_PHY_MODE1 = 0x01 * 4, /* phy Interrupt Enable */
114 VSR_PHY_MODE2 = 0x02 * 4, /* Phy Configuration */
115 VSR_PHY_MODE3 = 0x03 * 4, /* Phy Status */
116 VSR_PHY_MODE4 = 0x04 * 4, /* Phy Counter 0 */
117 VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */
118 VSR_PHY_MODE6 = 0x06 * 4, /* Event Counter Control */
119 VSR_PHY_MODE7 = 0x07 * 4, /* Event Counter Select */
120 VSR_PHY_MODE8 = 0x08 * 4, /* Event Counter 0 */
121 VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */
[all …]
/linux/tools/testing/selftests/drivers/net/hw/
H A Ddevlink_rate_tc_bw.py39 - Total bandwidth: 1Gbps
82 4: 80.0,
143 {"vlan_id": 102, "tc": 4, "ip": "198.51.100.10"},
215 {"index": 4, "bw": 80},
280 gbps = bits_per_second / 1e9
281 if gbps < min_expected_gbps:
283 f"iperf3 bandwidth too low: {gbps:.2f} Gbps "
284 f"(expected ≥ {min_expected_gbps} Gbps)"
287 return gbps
303 ("198.51.100.10", "198.51.100.9", 4),
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h32 #define PPTABLE_ARCTURUS_SMU_VERSION 4
39 #define NUM_UCLK_DPM_LEVELS 4
42 #define NUM_XGMI_PSTATE_LEVELS 4
60 #define FEATURE_DPM_FCLK_BIT 4
191 #define THROTTLER_TEMP_VR_GFX_BIT 4
216 #define WORKLOAD_PPLIB_CUSTOM_BIT 4
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h45 #define NUM_UCLK_DPM_LEVELS 4
50 #define NUM_XGMI_PSTATE_LEVELS 4
80 #define FEATURE_DPM_FCLK_BIT 4
199 #define THROTTLER_TEMP_VR_GFX_BIT 4
223 #define FW_DSTATE_SMN_DS_BIT 4
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
[all …]
H A Dsmu13_driver_if_aldebaran.h33 #define NUM_UCLK_DPM_LEVELS 4
35 #define NUM_XGMI_DPM_LEVELS 4
42 #define FEATURE_DPM_FCLK_BIT 4
115 #define THROTTLER_TDC_HBM_BIT 4
358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
427 uint8_t UclkSpreadPercent; // Q4.4
432 uint8_t FclkSpreadPercent; // Q4.4
494 uint16_t TemperatureAllHBM[4] ;
551 #define TABLE_SMU_METRICS 4
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
69 maxItems: 4
123 data-lanes = <1 2 3 4>;
149 data-lanes = <1 2 3 4>;
H A Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
72 maxItems: 4
132 data-lanes = <1 2 3 4>;
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c64 * Pixel data arrives in 4:4:4 format from the VENC
87 * - PHY, Clock and Mode setup for 2k && 4k modes
291 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
295 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
299 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
310 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
314 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
318 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
325 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
330 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
[all …]
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
69 #define CFG_0_TX_CRC_EN_SHIFT 4
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
/linux/drivers/net/phy/
H A Dphy-core.c31 return "1Gbps"; in phy_speed_to_str()
33 return "2.5Gbps"; in phy_speed_to_str()
35 return "5Gbps"; in phy_speed_to_str()
37 return "10Gbps"; in phy_speed_to_str()
39 return "14Gbps"; in phy_speed_to_str()
41 return "20Gbps"; in phy_speed_to_str()
43 return "25Gbps"; in phy_speed_to_str()
45 return "40Gbps"; in phy_speed_to_str()
47 return "50Gbps"; in phy_speed_to_str()
49 return "56Gbps"; in phy_speed_to_str()
[all …]
/linux/include/rdma/
H A Dopa_port_info.h12 #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
31 #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
89 #define OPA_LINKINIT_REASON_LINKUP (1 << 4)
90 #define OPA_LINKINIT_REASON_FLAPPING (2 << 4)
91 #define OPA_LINKINIT_REASON_CLEAR (8 << 4)
92 #define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4)
93 #define OPA_LINKINIT_QUARANTINED (9 << 4)
94 #define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4)
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h29 #define HCLGE_RD_OTHER_STATS_NUM 4
90 #define HCLGE_RSS_TC_SIZE_2 4
121 #define HCLGE_GET_DFX_REG_TYPE_CNT 4
169 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U
175 #define HCLGE_MEM_BAR 4
191 #define HCLGE_SUPPORT_100G_R4_BIT BIT(4)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-puzzle-m801.dts108 /* SFP+ port 2: 10 Gbps indicator */
115 /* SFP+ port 2: 1 Gbps indicator */
121 led-4 {
122 /* SFP+ port 1: 10 Gbps indicator */
124 function-enumerator = <4>;
129 /* SFP+ port 1: 1 Gbps indicator */
422 bus-width = <4>;
/linux/fs/smb/client/
H A Dcifs_debug.c36 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 4, in cifs_dump_mem()
182 return "1Gbps"; in smb_speed_to_str()
184 return "2.5Gbps"; in smb_speed_to_str()
186 return "5Gbps"; in smb_speed_to_str()
188 return "10Gbps"; in smb_speed_to_str()
190 return "14Gbps"; in smb_speed_to_str()
192 return "20Gbps"; in smb_speed_to_str()
194 return "25Gbps"; in smb_speed_to_str()
196 return "40Gbps"; in smb_speed_to_str()
198 return "50Gbps"; in smb_speed_to_str()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c434 return 4; in intel_c10_get_tx_vboost_lvl()
528 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
540 .pll[4] = 0x26,
566 .pll[4] = 0x33,
592 .pll[4] = 0x39,
618 .pll[4] = 0x20,
644 .pll[4] = 0x26,
670 .pll[4] = 0x33,
696 .pll[4] = 0x20,
722 .pll[4] = 0xA8,
[all …]
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c36 #define RTL8211F_INER_LINK_STATUS BIT(4)
48 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4)
49 #define RTL8211E_LEDCR1_MASK BIT(4)
57 #define RTL8211E_LEDCR2_SHIFT 4
85 #define RTL8211F_LEDCR_ACT_TXRX BIT(4)
89 #define RTL8211F_LEDCR_MASK GENMASK(4, 0)
134 #define RTL9000A_GINMR_LINK_STATUS BIT(4)
138 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
511 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); in rtl8211f_set_wol()
1814 .name = "RTL8226 2.5Gbps PHY",
[all …]
/linux/drivers/usb/host/
H A Dxhci-hub.c26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
144 min_ssid = 4; in xhci_create_usb3x_bos_desc()
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-board.c89 return 4; in cvmx_helper_board_get_mii_address()
96 if ((ipd_port >= 0) && (ipd_port < 4)) in cvmx_helper_board_get_mii_address()
99 return ipd_port - 16 + 4; in cvmx_helper_board_get_mii_address()
113 * Board has 4 SGMII ports. The PHYs start right after the MII in cvmx_helper_board_get_mii_address()
116 if ((ipd_port >= 0) && (ipd_port < 4)) in cvmx_helper_board_get_mii_address()
127 * Board has 8 SGMII ports. 4 connect out, two connect in cvmx_helper_board_get_mii_address()
130 if ((ipd_port >= 0) && (ipd_port < 4)) in cvmx_helper_board_get_mii_address()
136 return 4; in cvmx_helper_board_get_mii_address()
140 /* Board has 4 SGMII ports. connected QLM3(interface 1) */ in cvmx_helper_board_get_mii_address()
169 return ipd_port - 16 + 4; in cvmx_helper_board_get_mii_address()
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dmicrochip,usb5744.yaml7 title: Microchip USB5744 4-port Hub Controller
10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS),
15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
/linux/drivers/net/ethernet/intel/igc/
H A Digc_mac.c331 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); in igc_rar_set()
488 * Register (Address 4) and the Auto_Negotiation Base in igc_config_fc_after_link_up()
501 * (Address 4) and two bits in the Auto Negotiation Base in igc_config_fc_after_link_up()
678 /* For I225, STATUS will indicate 1G speed in both 1 Gbps in igc_get_speed_and_duplex_copper()
679 * and 2.5 Gbps link modes. An additional bit is used in igc_get_speed_and_duplex_copper()
680 * to differentiate between 1 Gbps and 2.5 Gbps. in igc_get_speed_and_duplex_copper()
798 * of 8 bits of shifting, then mc_addr[4] will shift right the in igc_hash_mc_addr()
806 * we can see that the bit_shift for case 0 is 4. These are the hash in igc_hash_mc_addr()
808 * [0] [1] [2] [3] [4] [5] in igc_hash_mc_addr()
812 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 in igc_hash_mc_addr()
[all …]
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dixgbe.rst96 cables that comply with SFF-8431 v4.1 and SFF-8472 v10.4 specifications.
111 - 82599-based QSFP+ adapters only support 4x10 Gbps connections. 1x40 Gbps
113 4x10 Gbps.
115 The link speed must be configured to either 10 Gbps or 1 Gbps to match the link
156 SFF-8431 v4.1 and SFF-8472 v10.4 specifications. Active direct attach cables
201 modprobe ixgbe max_vfs=4
203 This will spawn 4 VFs on the first port.
207 modprobe ixgbe max_vfs=2,4
209 This will spawn 2 VFs on the first port and 4 VFs on the second port.
252 16 - 31 VFs = Up to 4 traffic classes
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
77 #define PLL_READY_TX_BIT BIT(4)
110 #define CLK100M_125M_EN BIT(4)
130 #define PRD_TXSWING_MASK BIT(4)
137 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
152 #define MODE_REFDIV_MASK GENMASK(5, 4)
162 #define BUNDLE_SAMPLE_CTRL BIT(4)
222 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
300 /* 0 1 2 3 4 5 6 7 */
573 /* 4. Reset reserved bit */ in mvebu_a3700_comphy_sata_power_on()
[all …]
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.h83 #define H_QPCB0_QP_AER EHEA_BMASK_IBM(4, 4)
114 #define H_QPCB1_SGEL_NB_SQ EHEA_BMASK_IBM(4, 4)
161 #define H_PORT_CB4 4
189 #define H_SPEED_100M_F 4 /* 100 Mbps, Full Duplex */
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */

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