Lines Matching +full:4 +full:gbps
434 return 4; in intel_c10_get_tx_vboost_lvl()
528 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
540 .pll[4] = 0x26,
566 .pll[4] = 0x33,
592 .pll[4] = 0x39,
618 .pll[4] = 0x20,
644 .pll[4] = 0x26,
670 .pll[4] = 0x33,
696 .pll[4] = 0x20,
722 .pll[4] = 0xA8,
748 .pll[4] = 0x30,
890 .clock = 1000000, /* 10 Gbps */
914 .clock = 1350000, /* 13.5 Gbps */
939 .clock = 2000000, /* 20 Gbps */
1116 .clock = 1350000, /* 13.5 Gbps */
1178 .pll[4] = 0,
1204 .pll[4] = 0,
1230 .pll[4] = 0,
1256 .pll[4] = 0,
1282 .pll[4] = 0,
1305 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1315 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1325 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1335 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1345 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1355 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1365 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1375 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1385 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1395 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1405 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1415 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1425 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1435 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1445 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1455 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1465 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1475 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1485 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1495 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1505 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1515 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1525 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1535 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1545 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1555 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1565 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1575 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1585 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1595 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1605 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1615 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1625 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1635 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1645 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1655 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1665 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1675 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1685 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1695 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
2055 for (i = 4; i < 9; i++) in intel_c10pll_update_pll()
2148 (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED); in intel_c10_pll_program()
2192 BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); in intel_c10pll_dump_hw_state()
2193 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) in intel_c10pll_dump_hw_state()
2224 tx_term_ctrl = 4; in intel_c20_hdmi_tmds_tx_cgf_1()
2260 multiplier = div64_u64((vco_freq << 28), (REFCLK_38_4_MHZ >> 4)); in intel_c20_compute_hdmi_tmds_pll()
2297 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2500 "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2503 "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2508 drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, in intel_c20pll_dump_hw_state()
2512 drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i, in intel_c20pll_dump_hw_state()
2529 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2531 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2533 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2535 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2537 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2538 return 4; in intel_c20_get_dp_rate()
2539 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2541 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2543 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2545 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2547 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2549 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2551 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2553 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2567 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2568 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2569 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2571 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2573 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2593 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2594 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2595 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2596 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2597 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2641 for (i = 0; i < 4; i++) in intel_c20_pll_program()
2696 /* 4. Program custom width to match the link protocol */ in intel_c20_pll_program()
2969 for (i = 0; i < 4; i++) { in intel_cx0_program_phy_lane()
3040 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000. in __intel_cx0pll_enable()
3195 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL. in intel_mtl_tbt_pll_enable()
3258 for (i = 0; i < 4; i++) { in intel_lnl_mac_transmit_lfps()
3310 /* 4. Program DDI_CLK_VALFREQ to 0. */ in intel_cx0pll_disable()
3372 * 4. Follow the Display Voltage Frequency Switching Sequence After in intel_mtl_tbt_pll_disable()
3613 * system power. After a system reset (cold boot, S3/4/5, warm reset) if a dedicated
3656 __intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4); in intel_cx0_pll_power_save_wa()