Lines Matching +full:4 +full:gbps

55 #define REF_FREF_SEL_MASK		GENMASK(4, 0)
77 #define PLL_READY_TX_BIT		BIT(4)
110 #define CLK100M_125M_EN			BIT(4)
130 #define PRD_TXSWING_MASK		BIT(4)
137 #define GEN2_TX_DATA_DLY_MASK		GENMASK(4, 3)
152 #define MODE_REFDIV_MASK		GENMASK(5, 4)
162 #define BUNDLE_SAMPLE_CTRL		BIT(4)
222 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT	BIT(4)
300 	/* 0       1       2       3       4       5       6       7 */
573 	/* 4. Reset reserved bit */  in mvebu_a3700_comphy_sata_power_on()
608 		 * All PHY register values are defined in full for 3.125Gbps  in comphy_gbe_phy_init()
609 		 * SERDES speed. The values required for 1.25 Gbps are almost  in comphy_gbe_phy_init()
611 		 * comparison to 3.125 Gbps values. These register values are  in comphy_gbe_phy_init()
650 	/* 4. Release reset to the PHY by setting PIN_RESET=0. */  in mvebu_a3700_comphy_ethernet_power_on()
715 	 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or  in mvebu_a3700_comphy_ethernet_power_on()
716 	 * PCIe speed 2.5/5 Gbps  in mvebu_a3700_comphy_ethernet_power_on()
835 	 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The  in mvebu_a3700_comphy_usb3_power_on()
849 	 *    Set BIT[3:4]: delay 2 clock cycles for HiZ off latency  in mvebu_a3700_comphy_usb3_power_on()
866 	 * 4. Set Override Margining Controls From the MAC:  in mvebu_a3700_comphy_usb3_power_on()
882 	 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K  in mvebu_a3700_comphy_usb3_power_on()
956 	 * 14. Set max speed generation to USB3.0 5Gbps  in mvebu_a3700_comphy_usb3_power_on()
1008 	/* 4. Change RX wait */  in mvebu_a3700_comphy_pcie_power_on()