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/linux/arch/riscv/kernel/
H A Dkexec_relocate.S24 mv s0, a0
25 mv s1, a1
26 mv s2, a2
27 mv s3, a3
28 mv s4, a4
29 mv s5, zero
30 mv s6, zero
45 la s6, 1f
58 1:
66 j 1b
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_aldebaran.h39 #define FEATURE_DPM_GFXCLK_BIT 1
106 #define I2C_CONTROLLER_ENABLED 1
112 #define THROTTLER_PPT1_BIT 1
140 #define I2C_CONTROLLER_ENABLED 1
186 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
187 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode)
199 #define CMDCONFIG_RESTART_BIT 1
200 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write
202 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
203 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
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H A Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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H A Dsmu11_driver_if_arcturus.h44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
57 #define FEATURE_DPM_GFXCLK_BIT 1
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H A Dsmu11_driver_if_navi10.h50 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
51 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
52 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
53 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
54 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
55 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
56 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
57 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
58 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
59 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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H A Dsmu13_driver_if_v13_0_0.h49 #define FEATURE_DPM_GFXCLK_BIT 1
115 #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \
116 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
117 (1 << FEATURE_DPM_UCLK_BIT) | \
118 (1 << FEATURE_DPM_FCLK_BIT) | \
119 (1 << FEATURE_DPM_SOCCLK_BIT) | \
120 (1 << FEATURE_DPM_MP0CLK_BIT) | \
121 (1 << FEATURE_DPM_LINK_BIT) | \
122 (1 << FEATURE_DPM_DCN_BIT) | \
123 (1 << FEATURE_DS_GFXCLK_BIT) | \
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H A Dsmu13_driver_if_v13_0_7.h50 #define FEATURE_DPM_GFXCLK_BIT 1
116 #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \
117 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
118 (1 << FEATURE_DPM_UCLK_BIT) | \
119 (1 << FEATURE_DPM_FCLK_BIT) | \
120 (1 << FEATURE_DPM_SOCCLK_BIT) | \
121 (1 << FEATURE_DPM_MP0CLK_BIT) | \
122 (1 << FEATURE_DPM_LINK_BIT) | \
123 (1 << FEATURE_DPM_DCN_BIT) | \
124 (1 << FEATURE_DS_GFXCLK_BIT) | \
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/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l33.txt22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
24 8000mV.
31 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
54 LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
55 depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
62 stage enters LDO operation. Starts as a default value of 50mV for a value
63 of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
81 by 100mV per step to a maximum of 5500mV.
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H A Dcs35l36.txt14 converter's output voltage in mV. The range is from 2550mV to 12000mV with
15 increments of 50mV.
28 1000 = 1uH (Default)
65 1 = 5ms
75 weak-FET operation. The range is 50mV to 700mV in 50mV increments.
84 1 = 115C
92 1 = Push-pull (Default)
98 1 = GPIO
106 1 = VBST brownout prevention enabled
108 See Section 7.31.1 VPBR Config for configuration options & further details
/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml21 enum: [0, 1, 2, 3]
36 maxItems: 1
42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
46 - 0: 32mV/us
47 - 1: 16mV/us
48 - 2: 8mV/us
49 - 3: 4mV/us
50 - 4: 2mV/us
51 - 5: 1mV/us
52 - 6: 0.5mV/us
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/linux/include/linux/usb/
H A Dpd.h16 PD_CTRL_GOOD_CRC = 1,
41 PD_DATA_SOURCE_CAP = 1,
56 PD_EXT_SOURCE_CAP_EXT = 1,
208 PDO_TYPE_BATT = 1,
232 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
235 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
238 #define PDO_FIXED(mv, ma, flags) \ argument
240 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
242 #define VSAFE5V 5000 /* mv units */
244 #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c53 /* Idx NT mV d T mV d db */
55 { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */
126 /* Idx NT mV d T mV df db */
128 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */
362 /* Idx NT mV diff db */
364 { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */
372 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */
381 /* Idx NT mV diff db */
383 { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */
403 /* Idx NT mV diff db */
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/linux/drivers/clk/tegra/
H A Dcvb.c17 int mv; in get_cvb_voltage() local
19 /* apply only speedo scale: output mv = cvb_mv * v_scale */ in get_cvb_voltage()
20 mv = DIV_ROUND_CLOSEST(cvb->c2 * speedo, s_scale); in get_cvb_voltage()
21 mv = DIV_ROUND_CLOSEST((mv + cvb->c1) * speedo, s_scale) + cvb->c0; in get_cvb_voltage()
22 return mv; in get_cvb_voltage()
25 static int round_cvb_voltage(int mv, int v_scale, in round_cvb_voltage() argument
33 uv = max(mv * 1000, offset) - offset; in round_cvb_voltage()
43 static int round_voltage(int mv, const struct rail_alignment *align, int up) in round_voltage() argument
48 uv = max(mv * 1000, align->offset_uv) - align->offset_uv; in round_voltage()
49 uv = (uv + (up ? align->step_uv - 1 : 0)) / align->step_uv; in round_voltage()
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/linux/arch/sh/kernel/
H A Dmachvec.c22 #define for_each_mv(mv) \ argument
23 for ((mv) = (struct sh_machine_vector *)__machvec_start; \
24 (mv) && (unsigned long)(mv) < (unsigned long)__machvec_end; \
25 (mv)++)
29 struct sh_machine_vector *mv; in get_mv_byname() local
31 for_each_mv(mv) in get_mv_byname()
32 if (strcasecmp(name, mv->mv_name) == 0) in get_mv_byname()
33 return mv; in get_mv_byname()
54 if (mv_len > (MV_NAME_SIZE-1)) in early_parse_mv()
55 mv_len = MV_NAME_SIZE-1; in early_parse_mv()
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/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c20 #define VP9_RESET_FRAME_CONTEXT_NONE1 1
58 u8 class0[1];
91 u32 padding0[1];
181 u8 padding0[1];
214 u8 padding1[1];
340 * @mv: mv working buffer
359 struct vdec_vp9_slice_mem mv[2]; member
429 * @mv: mv working buffer
468 * mv[0]/seg[0]/tile/prob/counts is used for LAT
469 * mv[1]/seg[1] is used for CORE
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/linux/include/dt-bindings/usb/
H A Dpd.h7 #define PDO_TYPE_BATT 1
20 #define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */
21 #define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */
22 #define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */
23 #define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */
24 #define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */
25 #define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */
26 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
29 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
32 #define PDO_FIXED(mv, ma, flags) \ argument
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/linux/Documentation/hwmon/
H A Dltc4245.rst35 on I2C bus #1::
38 $ echo ltc4245 0x23 > /sys/bus/i2c/devices/i2c-1/new_device
52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
72 in5_input 12v output voltage (mV)
73 in6_input 5v output voltage (mV)
74 in7_input 3v output voltage (mV)
75 in8_input Vee (-12v) output voltage (mV)
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/linux/arch/arm/mach-omap2/
H A Dboard-n8x0.c36 #define TUSB6010_ASYNC_CS 1
40 #define NOKIA_N810_WIMAX (1 << 2)
41 #define NOKIA_N810 (1 << 1)
42 #define NOKIA_N800 (1 << 0)
66 .multipoint = 1,
67 .dyn_fifo = 1,
132 * VMMC slot 1 on both N800 and N810
155 /* Slot index 1, VSD power, GPIO 23 */
156 GPIO_LOOKUP_IDX("gpio-0-31", 23, "vsd", 1, GPIO_ACTIVE_HIGH),
157 /* Slot index 1, VIO power, GPIO 9 */
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/linux/include/linux/mfd/
H A Dmenelaus.h21 extern int menelaus_set_vmem(unsigned int mV);
22 extern int menelaus_set_vio(unsigned int mV);
23 extern int menelaus_set_vmmc(unsigned int mV);
24 extern int menelaus_set_vaux(unsigned int mV);
25 extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
30 #define EN_VPLL_SLEEP (1 << 7)
31 #define EN_VMMC_SLEEP (1 << 6)
32 #define EN_VAUX_SLEEP (1 << 5)
33 #define EN_VIO_SLEEP (1 << 4)
34 #define EN_VMEM_SLEEP (1 << 3)
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/linux/drivers/media/platform/verisilicon/
H A Dhantro_g2_vp9_dec.c21 LAST_FRAME = 1,
55 * if ( frame_type == KEY_FRAME || error_resilient_mode == 1 || in start_prepare_run()
74 * probs in a special way. All probs which need updating, except MV-related, in start_prepare_run()
78 * inv_map_table[]), or zero to indicate no update. All MV-related probs which need in start_prepare_run()
79 * updating have been read from the bitstream and (mv_prob << 1) | 1 has been in start_prepare_run()
112 buf->vp9.width = dec_params->frame_width_minus_1 + 1; in update_dec_buf_info()
113 buf->vp9.height = dec_params->frame_height_minus_1 + 1; in update_dec_buf_info()
221 config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts); in config_ref_registers()
229 dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_LAST ? 1 : 0); in config_ref_registers()
232 dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_GOLDEN ? 1 : 0); in config_ref_registers()
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/linux/Documentation/devicetree/bindings/input/
H A Dti,drv260x.yaml20 maxItems: 1
41 enum: [ 0, 1, 2 ]
58 enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
61 maxItems: 1
65 maxItems: 1
67 vib-rated-mv:
71 If this is not set then the value will be defaulted to 3200 mV.
74 vib-overdrive-mv:
78 If this is not set then the value will be defaulted to 3200 mV.
96 #address-cells = <1>;
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/linux/drivers/staging/media/rkvdec/
H A Drkvdec-vp9.c69 } mv; member
79 u8 tx8[2][1];
118 /* add 1 element for align */
119 u32 classes[2][11 + 1];
145 u32 valid : 1;
146 u32 segmapid : 1;
289 /* mv related 6 x 128 */ in init_inter_probs()
290 memcpy(rkprobs->mv.joint, probs->mv.joint, in init_inter_probs()
291 sizeof(rkprobs->mv.joint)); in init_inter_probs()
292 memcpy(rkprobs->mv.sign, probs->mv.sign, in init_inter_probs()
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/linux/drivers/scsi/
H A Dch.c47 static int init = 1;
62 static int verbose = 1;
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
103 #define MAX_RETRIES 1
236 return i+1; in ch_elem_to_typecode()
255 cmd[1] = ((ch->device->lun & 0x7) << 5) | in ch_read_element_status()
260 cmd[5] = 1; in ch_read_element_status()
292 cmd[1] = (ch->device->lun & 0x7) << 5; in ch_init_elem()
312 cmd[1] = (ch->device->lun & 0x7) << 5; in ch_readconfig()
317 cmd[1] |= (1<<3); in ch_readconfig()
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-stm32-usbphyc.yaml19 |_ PHY port#1 _________________ HOST controller
21 | / 1|________________|
34 maxItems: 1
37 maxItems: 1
40 maxItems: 1
43 const: 1
49 description: regulator providing 1V1 power supply to the PLL block
52 description: regulator providing 1V8 power supply to the PLL block
59 minItems: 1
65 "^usb-phy@[0|1]$":
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/linux/drivers/mfd/
H A Dmenelaus.c100 #define MENELAUS_MMC_S1CD_IRQ 0 /* MMC slot 1 card change */
101 #define MENELAUS_MMC_S2CD_IRQ 1 /* MMC slot 2 card change */
102 #define MENELAUS_MMC_S1D1_IRQ 2 /* MMC DAT1 low in slot 1 */
118 #define VCORE_CTRL1_BYP_COMP (1 << 5)
119 #define VCORE_CTRL1_HW_NSW (1 << 7)
122 #define GPIO_CTRL_SLOTSELEN (1 << 5)
123 #define GPIO_CTRL_SLPCTLEN (1 << 6)
124 #define GPIO1_DIR_INPUT (1 << 0)
125 #define GPIO2_DIR_INPUT (1 << 1)
126 #define GPIO3_DIR_INPUT (1 << 2)
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