| /freebsd/contrib/file/magic/Magdir/ |
| H A D | elf | 2 #------------------------------------------------------------------------------ 15 # Modified by (2): Peter Tobias <tobias@server.et-inf.fho-emden.de> (core support) 20 0 name elf-mips 21 >0 lelong&0xf0000000 0x00000000 MIPS-I 22 >0 lelong&0xf0000000 0x10000000 MIPS-II 23 >0 lelong&0xf0000000 0x20000000 MIPS-III 24 >0 lelong&0xf0000000 0x30000000 MIPS-IV 25 >0 lelong&0xf0000000 0x40000000 MIPS-V 33 0 name elf-sparc 42 0 name elf-pa-risc [all …]
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| H A D | coff | 2 #------------------------------------------------------------------------------ 3 # $File: coff,v 1.15 2024/11/10 18:54:33 christos Exp $ 12 # https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#coff-file-header-object-and-image 16 0 name display-coff-processor 20 >0 uleshort 0x0160 MIPS R3000 (big-endian) 25 >0 uleshort 0x0184 Alpha 32-bit 37 >0 uleshort 0x01f0 PowerPC 32-bit (little-endian) 38 >0 uleshort 0x01f1 PowerPC 32-bit with FPU (little-endian) 39 >0 uleshort 0x01f2 PowerPC 64-bit (big-endian) 43 >0 uleshort 0x0284 Alpha 64-bit [all …]
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| H A D | mach | 2 #------------------------------------------------------------ 8 #------------------------------------------------------------ 9 # if set, it's for the 64-bit version of the architecture 10 # yes, this is separate from the low-order magic number bit 11 # it's also separate from the "64-bit libraries" bit in the 14 # Reference: https://opensource.apple.com/source/cctools/cctools-949.0.1/ 15 # include/mach-o/loader.h 17 0 name mach-o-cpu 20 # 32-bit ABIs. 135 >>0 belong&0x00ffffff 18 ppc [all …]
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7603/ |
| H A D | mac.h | 1 /* SPDX-License-Identifier: ISC */ 10 #define MT_RXD0_NORMAL_IP_SUM BIT(23) 11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) 12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25) 13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26) 14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27) 15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28) 29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23) 30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22) 34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5) [all …]
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| /freebsd/contrib/netbsd-tests/include/ |
| H A D | d_bitstring_27.out | 23 18 2 4 3 34 be: 0 -1 000000000000000000000000000 35 is: 0 -1 000000000000000000000000000 65 18 0 76 be: 0 -1 000000000000000000000000000 77 is: 0 -1 000000000000000000000000000 84 be: 0 -1 000000000000000000000000000 85 is: 0 -1 000000000000000000000000000 88 be: 0 -1 000000000000000000000000000 89 is: 0 -1 000000000000000000000000000 [all …]
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| H A D | d_bitstring_32.out | 23 18 2 4 3 39 be: 0 -1 00000000000000000000000000000000 40 is: 0 -1 00000000000000000000000000000000 70 18 0 86 be: 0 -1 00000000000000000000000000000000 87 is: 0 -1 00000000000000000000000000000000 94 be: 0 -1 00000000000000000000000000000000 95 is: 0 -1 00000000000000000000000000000000 98 be: 0 -1 00000000000000000000000000000000 99 is: 0 -1 00000000000000000000000000000000 [all …]
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| H A D | d_bitstring_49.out | 23 18 2 4 3 56 be: 0 -1 0000000000000000000000000000000000000000000000000 57 is: 0 -1 0000000000000000000000000000000000000000000000000 87 18 0 120 be: 0 -1 0000000000000000000000000000000000000000000000000 121 is: 0 -1 0000000000000000000000000000000000000000000000000 128 be: 0 -1 0000000000000000000000000000000000000000000000000 129 is: 0 -1 0000000000000000000000000000000000000000000000000 132 be: 0 -1 0000000000000000000000000000000000000000000000000 133 is: 0 -1 0000000000000000000000000000000000000000000000000 [all …]
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| H A D | d_bitstring_67.out | 23 18 2 4 3 74 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000 75 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000 105 18 0 156 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000 157 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000 164 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000 165 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000 168 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000 169 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000 [all …]
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| H A D | d_bitstring_64.out | 23 18 2 4 3 71 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000 72 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000 102 18 0 150 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000 151 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000 158 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000 159 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000 162 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000 163 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000 [all …]
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| /freebsd/sys/contrib/dev/mediatek/mt76/ |
| H A D | mt76_connac3_mac.h | 1 /* SPDX-License-Identifier: ISC */ 28 #define MT_RXD0_MESH BIT(18) 29 #define MT_RXD0_MHCP BIT(19) 38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16) 39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17) 40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18) 41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19) 42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20) 44 #define MT_RXD1_NORMAL_CM BIT(23) 45 #define MT_RXD1_NORMAL_CLM BIT(24) [all …]
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| H A D | mt76_connac2_mac.h | 1 /* SPDX-License-Identifier: ISC */ 46 #define MT_TX_FREE_PAIR BIT(31) 55 #define MT_TXD1_LONG_FORMAT BIT(31) 56 #define MT_TXD1_TGID BIT(30) 58 #define MT_TXD1_AMSDU BIT(23) 60 #define MT_TXD1_HDR_PAD GENMASK(19, 18) 63 #define MT_TXD1_ETH_802_3 BIT(15) 64 #define MT_TXD1_VTA BIT(10) 67 #define MT_TXD2_FIX_RATE BIT(31) 68 #define MT_TXD2_FIXED_RATE BIT(30) [all …]
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| H A D | mt76x02_regs.h | 1 /* SPDX-License-Identifier: ISC */ 15 #define MT_CMB_CTRL_XTAL_RDY BIT(22) 16 #define MT_CMB_CTRL_PLL_LD BIT(23) 24 #define MT_EFUSE_CTRL_KICK BIT(30) 25 #define MT_EFUSE_CTRL_SEL BIT(31) 31 #define MT_COEXCFG0_COEX_EN BIT(0) 34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0) 35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1) 36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2) 43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */ [all …]
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7615/ |
| H A D | mac.h | 1 /* SPDX-License-Identifier: ISC */ 15 #define MT_RXD0_NORMAL_IP_SUM BIT(23) 16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) 17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25) 18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26) 19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27) 20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28) 25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1) 26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0) 27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23) [all …]
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| /freebsd/sys/contrib/dev/rtw89/ |
| H A D | reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 9 #define B_AX_AUTOLOAD_SUS BIT(5) 13 #define B_AX_PWC_EV2EF_B15 BIT(15) 14 #define B_AX_PWC_EV2EF_B14 BIT(14) 15 #define B_AX_ISO_EB2CORE BIT(8) 18 #define B_AX_FEN_BB_GLB_RSTN BIT(1) 19 #define B_AX_FEN_BBRSTB BIT(0) 22 #define B_AX_SOP_ASWRM BIT(31) 23 #define B_AX_SOP_PWMM_DSWR BIT(29) [all …]
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| H A D | txrx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode() 41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs() 49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs() 62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss() 71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23) 72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) 73 #define RTW89_TXWD_BODY0_FW_DL BIT(20) 76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10) 77 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7) [all …]
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| H A D | pci.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 18 #define BAC_OOBS_SEL BIT(4) 20 #define B_BAC_EQ_SEL BIT(5) 24 #define B_PCIE_BIT_PSAVE BIT(15) 26 #define OFFSET_CAL_MODE BIT(13) 27 #define BAC_RX_TEST_EN BIT(6) 32 #define B_PCIE_BIT_PINOUT_DIS BIT(3) 37 #define B_PCIE_BIT_RD_SEL BIT(2) 54 #define B_AX_CLK_CALIB_EN BIT(12) 55 #define B_AX_CALIB_EN BIT(13) [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | mc13xxx.txt | 4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892" 7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used 8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used 9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used 10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used 12 Sub-nodes: 13 - codec: Contain the Audio Codec node. 14 - adc-port: Contain PMIC SSI port number used for ADC. 15 - dac-port: Contain PMIC SSI port number used for DAC. 16 - leds : Contain the led nodes and initial register values in property [all …]
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/mfd/ |
| H A D | stm32f4-rcc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 22 #define STM32F4_RCC_AHB1_BKPSRAM 18 34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument 35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument 44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument 45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument 51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument 52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument 68 #define STM32F4_RCC_APB1_UART3 18 81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument [all …]
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| H A D | stm32f7-rcc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 22 #define STM32F7_RCC_AHB1_BKPSRAM 18 34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) argument 35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) argument 45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) argument 46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) argument 52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) argument 53 #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) argument 72 #define STM32F7_RCC_APB1_UART3 18 87 #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) argument [all …]
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| /freebsd/crypto/openssl/doc/man3/ |
| H A D | OPENSSL_s390xcap.pod | 5 OPENSSL_s390xcap - the IBM z processor capabilities vector 23 The environment variable is a semicolon-separated list of tokens which is 34 The name of a processor generation. A bit in the environment variable's 42 The name of an instruction followed by two 64-bit masks. The part of the 44 set to the specified 128-bit mask. Possible values are B<kimd>, B<klmd>, 50 Store-facility-list-extended (stfle) followed by three 64-bit masks. The 52 instruction is set to the specified 192-bit mask. 61 The 64-bit masks are specified in hexadecimal notation. The 0x prefix is 65 rows separate the individual 64-bit masks. The bit numbers in the first 66 column are consistent with [1], that is, 0 denotes the leftmost bit and [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrFormats.td | 1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> { 27 "\n return isInt<"#BSz#">(N->getSExtValue());"> { 31 // e.g. s3 field may encode the signed integers values -1 .. 6 34 "\n return isInt<"#BSz#">(N->getSExtValue());"> { 64 class ExtMode<bit mode, string instSfx, string asmSfx> { [all …]
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| /freebsd/secure/lib/libcrypto/man/man3/ |
| H A D | OPENSSL_s390xcap.3 | 1 .\" -*- mode: troff; coding: utf-8 -*- 58 .TH OPENSSL_S390XCAP 3ossl 2025-09-30 3.5.4 OpenSSL 64 OPENSSL_s390xcap \- the IBM z processor capabilities vector 82 The environment variable is a semicolon-separated list of tokens which is 92 The name of a processor generation. A bit in the environment variable's 99 The name of an instruction followed by two 64\-bit masks. The part of the 101 set to the specified 128\-bit mask. Possible values are \fBkimd\fR, \fBklmd\fR, 106 Store-facility-list-extended (stfle) followed by three 64\-bit masks. The 108 instruction is set to the specified 192\-bit mask. 114 The 64\-bit masks are specified in hexadecimal notation. The 0x prefix is [all …]
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| /freebsd/sys/contrib/dev/rtw88/ |
| H A D | reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 9 #define BIT_FEN_EN_25_1 BIT(13) 10 #define BIT_FEN_ELDR BIT(12) 11 #define BIT_FEN_PCIEA BIT(6) 12 #define BIT_FEN_CPUEN BIT(2) 13 #define BIT_FEN_USBA BIT(2) 14 #define BIT_FEN_BB_GLB_RST BIT(1) 15 #define BIT_FEN_BB_RSTB BIT(0) 16 #define BIT_R_DIS_PRST BIT(6) [all …]
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| H A D | sdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 31 #define REG_SDIO_HIMR_RX_REQUEST BIT(0) 32 #define REG_SDIO_HIMR_AVAL BIT(1) 33 #define REG_SDIO_HIMR_TXERR BIT(2) 34 #define REG_SDIO_HIMR_RXERR BIT(3) 35 #define REG_SDIO_HIMR_TXFOVW BIT(4) 36 #define REG_SDIO_HIMR_RXFOVW BIT(5) 37 #define REG_SDIO_HIMR_TXBCNOK BIT(6) 38 #define REG_SDIO_HIMR_TXBCNERR BIT(7) 39 #define REG_SDIO_HIMR_BCNERLY_INT BIT(16) [all …]
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| /freebsd/sys/contrib/dev/athk/ath11k/ |
| H A D | rx_desc.h | 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 88 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0) 89 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1) 90 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2) 91 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3) 92 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4) 93 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5) 94 #define RX_ATTENTION_INFO1_NON_QOS BIT(6) 95 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7) [all …]
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