1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define STM32F7_RCC_AHB1_BKPSRAM	18
34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))  argument
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)  argument
45 #define STM32F7_AHB2_RESET(bit)	(STM32F7_RCC_AHB2_##bit + (0x14 * 8))  argument
46 #define STM32F7_AHB2_CLOCK(bit)	(STM32F7_RCC_AHB2_##bit + 0x20)  argument
52 #define STM32F7_AHB3_RESET(bit)	(STM32F7_RCC_AHB3_##bit + (0x18 * 8))  argument
53 #define STM32F7_AHB3_CLOCK(bit)	(STM32F7_RCC_AHB3_##bit + 0x40)  argument
72 #define STM32F7_RCC_APB1_UART3		18
87 #define STM32F7_APB1_RESET(bit)	(STM32F7_RCC_APB1_##bit + (0x20 * 8))  argument
88 #define STM32F7_APB1_CLOCK(bit)	(STM32F7_RCC_APB1_##bit + 0x80)  argument
105 #define STM32F7_RCC_APB2_TIM11		18
113 #define STM32F7_APB2_RESET(bit)	(STM32F7_RCC_APB2_##bit + (0x24 * 8))  argument
114 #define STM32F7_APB2_CLOCK(bit)	(STM32F7_RCC_APB2_##bit + 0xA0)  argument