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/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk.h>
32 * [12] mipi HSbyteclk enable.
33 * [11] mipi divider clk selection.
34 * 1: select the mipi DDRCLKHS from clock divider.
36 * [10] mipi clock divider control.
38 * [9] mipi divider output enable.
39 * [8] mipi divider counter enable.
42 * 1 = transfer the high bit first. 0 : transfer the low bit first.
52 /* [31] clk lane tx_hs_en control selection.
[all …]
/linux/drivers/clk/mvebu/
H A Dap-cpu-clk.c1 // SPDX-License-Identifier: GPL-2.0+
11 #define pr_fmt(fmt) "ap-cpu-clk: " fmt
13 #include <linux/clk-provider.h>
14 #include <linux/clk.h>
28 #define APN806_CLUSTER_NUM_MASK BIT(APN806_CLUSTER_NUM_OFFSET)
99 #define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET 12
146 struct ap_cpu_clk *clk = to_ap_cpu_clk(hw); in ap_cpu_clk_recalc_rate() local
150 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_recalc_rate()
151 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_recalc_rate()
152 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio); in ap_cpu_clk_recalc_rate()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
32 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
33 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
48 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl()
53 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl()
65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument
67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
[all …]
H A Dgm20b.c23 #include <subdev/clk.h>
32 #define GPCPLL_CFG_SYNC_MODE BIT(2)
69 #define GPCPLL_DVFS1_DFS_CTRL_WIDTH 12
72 #define GPCPLL_DVFS1_EN_SDM_BIT BIT(28)
75 #define GPCPLL_DVFS1_EN_DFS_BIT BIT(29)
78 #define GPCPLL_DVFS1_EN_DFS_CAL_BIT BIT(30)
81 #define GPCPLL_DVFS1_DFS_CAL_DONE_BIT BIT(31)
84 #define GPC_BCAST_GPCPLL_DVFS2_DFS_EXT_STROBE_BIT BIT(16)
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
[all …]
/linux/drivers/clk/keystone/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
36 * @pllod: PLL register map address for post divider bits
41 * @plld_mask: divider mask
42 * @clkod_mask: output divider mask
43 * @clkod_shift: output divider shift
44 * @plld_mask: divider mask
[all …]
/linux/drivers/clk/ux500/
H A Du8500_of_clk.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
16 #include "reset-prcc.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
[all …]
/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
20 #define CLK_ENB_PLLP_OUT_CPU BIT(31)
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
91 struct clk *tegra_clk_register_sync_source(const char *name,
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
98 * @reg: register containing divider
99 * @flags: hardware-specific flags
[all …]
/linux/drivers/iio/adc/
H A Dingenic-adc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
6 * based on drivers/mfd/jz4740-adc.c
9 #include <dt-bindings/iio/adc/ingenic,adc.h>
10 #include <linux/clk.h>
36 #define JZ_ADC_REG_ENABLE_PD BIT(7)
37 #define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1))
38 #define JZ_ADC_REG_CFG_BAT_MD BIT(4)
41 #define JZ_ADC_REG_CFG_CMD_SEL BIT(22)
42 #define JZ_ADC_REG_CFG_VBAT_SEL BIT(30)
[all …]
/linux/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
29 #define WZRD_CLKOUT0_FRAC_EN BIT(18)
41 #define WZRD_CLKFBOUT_FRAC_EN BIT(1)
42 #define WZRD_CLKFBOUT_PREDIV2 (BIT(11) | BIT(12) | BIT(9))
43 #define WZRD_MULT_PREDIV2 (BIT(10) | BIT(9) | BIT(12))
44 #define WZRD_CLKFBOUT_EDGE BIT(8)
45 #define WZRD_P5EN BIT(13)
[all …]
H A Dxlnx_vcu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
17 #include <linux/mfd/syscon/xlnx-vcu.h>
23 #include <dt-bindings/clock/xlnx-vcu.h>
26 #define VCU_PLL_CTRL_RESET BIT(0)
27 #define VCU_PLL_CTRL_POR_IN BIT(1)
28 #define VCU_PLL_CTRL_PWR_POR BIT(2)
29 #define VCU_PLL_CTRL_BYPASS BIT(3)
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
[all …]
H A Dclk-sun9i-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include "clk-factors.h"
18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
33 n = DIV_ROUND_UP(req->rate, 6000000); in sun9i_a80_get_pll4_factors()
35 /* If n is too large switch to steps of 12 MHz */ in sun9i_a80_get_pll4_factors()
47 /* n must be between 12 and 255 */ in sun9i_a80_get_pll4_factors()
[all …]
/linux/drivers/clk/versatile/
H A Dclk-icst.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2012-2015 Linus Walleij
17 #include <linux/clk-provider.h>
23 #include "clk-icst.h"
34 #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
37 * struct clk_icst - ICST VCO clock wrapper
59 * vco_get() - get ICST VCO settings from a certain ICST
68 ret = regmap_read(icst->map, icst->vcoreg_off, &val); in vco_get()
74 * bits of the v PLL divider. Bit 8 is tied low and always zero, in vco_get()
75 * r is hardwired to 22 and output divider s is hardwired to 1 in vco_get()
[all …]
/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
33 #define NR_PSCS 12
70 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
176 return 12; in soc_max_pscnum()
215 /* common clk API wrappers {{{ */
217 /* convenience wrappers around the common clk API */
[all …]
/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
18 #define PLL_CTRL_ENABLE BIT(16)
19 #define PLL_CTRL_BYPASS BIT(15)
20 #define PLL_CTRL_DIRECT BIT(14)
21 #define PLL_CTRL_FEEDBACK BIT(13)
22 #define PLL_CTRL_POSTDIV (BIT(12)|BIT(11))
23 #define PLL_CTRL_PREDIV (BIT(10)|BIT(9))
[all …]
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun50i-h616.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
25 #include "ccu-sun50i-h616.h"
39 .enable = BIT(31),
40 .lock = BIT(28),
41 .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
53 .enable = BIT(31),
54 .lock = BIT(28),
55 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-clkgen.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
19 #include "clk-sg2042.h"
23 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
24 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
25 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
26 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
27 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
[all …]
/linux/drivers/watchdog/
H A Drenesas_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
9 #include <linux/clk.h>
24 #define RWTCSRA_WOVF BIT(4)
25 #define RWTCSRA_WRFLG BIT(5)
26 #define RWTCSRA_TME BIT(7)
32 * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
33 * divider (12 bits). d is only a factor to fully utilize the WDT counter and
37 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
[all …]
/linux/sound/soc/stm/
H A Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
38 /* Bit definition for SPI2S_CR1 register */
39 #define I2S_CR1_SPE BIT(0)
40 #define I2S_CR1_CSTART BIT(9)
41 #define I2S_CR1_CSUSP BIT(10)
42 #define I2S_CR1_HDDIR BIT(11)
43 #define I2S_CR1_SSI BIT(12)
[all …]
/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
26 #define AST2500_HPLL_BYPASS_EN BIT(20)
27 #define AST2400_HPLL_PROGRAMMED BIT(18)
28 #define AST2400_HPLL_BYPASS_EN BIT(17)
30 #define UART_DIV13_EN BIT(12)
33 #define CLKIN_25MHZ_EN BIT(23)
34 #define AST2400_CLK_SOURCE_SEL BIT(18)
[all …]
H A Dclk-axi-clkgen.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/adi-axi-common.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
26 #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
27 #define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
29 #define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
30 #define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
[all …]
/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
24 struct clk;
45 #define SSACD (0x3C) /* SSP Audio Clock Divider */
46 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
55 #define SSCR0_ECS BIT(6) /* External clock select */
56 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */
60 #define SSCR0_EDSS BIT(20) /* Extended data size select */
61 #define SSCR0_NCS BIT(21) /* Network clock select */
[all …]
/linux/drivers/clk/ti/
H A Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/clk.h>
5 #include <linux/clk-provider.h>
32 #define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
39 #define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
81 #define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
82 BIT(ADPLL_STATUS_FREQLOCK))
145 struct clk *clk; member
147 void (*unregister)(struct clk *clk);
169 struct clk *parent_clocks[MAX_ADPLL_INPUTS];
[all …]
/linux/drivers/clk/microchip/
H A Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <asm/mach-pic32/pic32.h>
15 #include "clk-core.h"
19 #define OSC_CUR_SHIFT 12
22 #define OSC_SWEN BIT(0)
42 #define PB_DIV_READY BIT(11)
43 #define PB_DIV_ENABLE BIT(15)
50 #define REFO_ACTIVE BIT(8)
51 #define REFO_DIVSW_EN BIT(9)
[all …]

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