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/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
/freebsd/sys/arm64/qoriq/clk/
H A Dls1028a_flexspi_clk.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 #include <dev/clk/clk_div.h>
62 { .value = 0, .divider = 1, },
63 { .value = 1, .divider = 2, },
64 { .value = 2, .divider = 3, },
65 { .value = 3, .divider = 4, },
66 { .value = 4, .divider = 5, },
67 { .value = 5, .divider = 6, },
68 { .value = 6, .divider = 7, },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
[all …]
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
[all …]
/freebsd/sys/dev/usb/serial/
H A Dumcs.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
69 #define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */
78 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */
109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
112 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port
115 #define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c1 /*-
36 #include <dev/clk/clk.h>
38 #include <dt-bindings/clock/tegra124-car.h>
213 /* bank L -> 0-31 */
226 GATE(I2C1, "i2c1", "pc_i2c1", L(12)),
241 /* bank H -> 32-63 */
253 GATE(SBC2, "spi2", "pc_spi2", H(12)),
270 /* bank U -> 64-95 */
299 /* bank V -> 96-127 */
311 GATE(DAM0, "dam0", "pc_dam0", V(12)),
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #include <dev/clk/clk.h>
39 #include <dt-bindings/clock/tegra210-car.h>
40 #include <dt-bindings/reset/tegra210-car.h>
285 #define TEGRA210_CLK_SATA_IOBIST W(12)
308 /* bank L -> 0-31 */
319 GATE(I2C1, "i2c1", "pc_i2c1", L(12)),
332 /* bank H -> 32-63 */
341 GATE(SBC2, "spi2", "pc_spi2", H(12)),
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_a64.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-a64-ccu.h>
48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 /* Non-exported clocks */
63 #define CLK_PLL_PERIPH0_2X 12
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_spi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
58 {"broadcom,bcm2835-spi", 1},
59 {"brcm,bcm2835-spi", 1},
76 "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN" in bcm_spi_printr()
81 reg--; in bcm_spi_printr()
84 device_printf(dev, "CLK=%uMhz/%d=%luhz\n", in bcm_spi_printr()
105 mtx_assert(&sc->sc_mtx, MA_OWNED); in bcm_spi_modifyreg()
116 uint32_t clk; in bcm_spi_clock_proc() local
122 clk = BCM_SPI_READ(sc, SPI_CLK); in bcm_spi_clock_proc()
[all …]
/freebsd/sys/dev/pwm/controller/rockchip/
H A Drk_pwm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk.h>
85 #define RK_PWM_CTRL_PRESCALE_MASK (7 << 12)
86 #define RK_PWM_CTRL_PRESCALE_SHIFT 12
97 { "rockchip,rk3288-pwm", 1 },
98 { "rockchip,rk3399-pwm", 1 },
104 { -1, 0 }
110 clk_t clk; member
123 #define RK_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))
[all …]
/freebsd/sys/contrib/device-tree/src/arc/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
H A Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/freebsd/sys/dev/mmc/host/
H A Ddwmmc_reg.h1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
43 #define SDMMC_CLKDIV 0x8 /* Clock Divider Register */
46 #define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
56 #define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
58 #define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
59 #define SDMMC_INTMASK_HLE (1 << 12) /* Hardware locked write err */
76 #define SDMMC_CMD_UPD_CLK_ONLY (1 << 21) /* Update clk only */
80 #define SDMMC_CMD_SEND_ASTOP (1 << 12) /* Send stop command at end of data tx/rx */
104 #define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */
[all …]
/freebsd/sys/dev/spibus/controller/allwinner/
H A Daw_spi.c1 /*-
43 #include <dev/clk/clk.h>
58 #define AW_SPI_TCR_FBS (1 << 12) /* First Transmit Bit Select (1 == LSB) */
72 #define AW_SPI_IER_TC (1 << 12) /* Transfer complete */
102 #define AW_SPI_FSR_RB_CNT_SHIFT 12
109 #define AW_SPI_CCR_DRS (1 << 12) /* Clock divider select */
126 { "allwinner,sun8i-h3-spi", 1 },
133 { -1, 0 }
156 #define AW_SPI_LOCK(sc) mtx_lock(&(sc)->mtx)
157 #define AW_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
[all …]
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_subr.c1 /*-
2 * SPDX-License-Identifier: ISC
10 * distributed with the Asus RT-N16 firmware source code release.
41 if (_sc->dev != NULL) \
42 device_printf(_sc->dev, _fmt, ##__VA_ARGS__); \
91 ((uint8_t)BHND_PMU_GET_BITS((_sc)->caps, BHND_PMU_CAP_REV))
94 bhnd_core_clkctl_wait((_sc)->clkctl, (_val), (_mask))
100 CHIPC_CST4330_CHIPMODE_SDIOD((_sc)->io->rd_chipst((_sc)->io_ctx))
113 * @retval non-zero if the query state could not be initialized.
119 query->dev = dev; in bhnd_pmu_query_init()
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
473 /* [0x8] PCS clock divider configuration */
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
621 * [0x84] SERDES 32-bit interface bit selection
625 * [0x88] SERDES 32-bit interface bit selection
694 #define ETH_10G_MAC_CMD_CFG_SW_RESET (1 << 12)
724 #define ETH_10G_MAC_CONTROL_AN_EN_SHIFT 12
766 * 0 - 10/100/1000
[all …]
/freebsd/sys/dev/sdhci/
H A Dsdhci_fsl_fdt.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2020 - 2021 Alstom Group.
5 * Copyright (c) 2020 - 2021 Semihalf.
42 #include <dev/clk/clk.h>
56 #define RD4 (sc->read)
57 #define WR4 (sc->write)
77 #define SDHCI_FSL_IRQSTAT_RTE (1 << 12)
166 * In HS400 mode only 4, 8, 12 clock dividers can be used.
219 .syscon_compat = "fsl,ls1012a-scfg",
[all …]
H A Dsdhci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
[all …]
/freebsd/sys/arm/ti/
H A Dti_i2c.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
36 * 32 bit data access is not allowed and can corrupt register content.
100 uint8_t psc; /* Fast/Standard mode prescale divider */
123 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
124 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
126 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
128 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
129 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
[all …]
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2010-2015 Broadcom Corporation
10 * distributed with the Asus RT-N16 firmware source code release.
72 #define CHIPC_SFLASH_SIZE 12
77 /* siba backplane configuration broadcast (siba-only) */
81 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */
97 #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */
100 /* clock control registers (non-PMU devices) */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
38 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
54 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
57 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
78 …Bit 0 - For ending "endless completion". 0 - When receiving a completion timeout while receiving a…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 … // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo push overflow…
[all …]

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