| /linux/arch/arm64/boot/dts/broadcom/bcmbca/ |
| H A D | bcm4908.dtsi | 26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 cpu-release-addr = <0x0 0xff8>;
40 reg = <0x1>;
42 cpu-release-addr = <0x0 0xff8>;
49 reg = <0x2>;
51 cpu-release-addr = <0x0 0xff8>;
58 reg = <0x3>;
60 cpu-release-addr = <0x0 0xff8>;
[all …]
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| /linux/drivers/accel/habanalabs/include/hw_ip/pci/ |
| H A D | pci_general.h | 12 #define mmPCI_CONFIG_ELBI_ADDR 0xFF0
13 #define mmPCI_CONFIG_ELBI_DATA 0xFF4
14 #define mmPCI_CONFIG_ELBI_CTRL 0xFF8
17 #define mmPCI_CONFIG_ELBI_STS 0xFFC
24 /* PCI revision ID 0 is not legal */
25 REV_ID_INVALID = 0x00,
26 REV_ID_A = 0x01,
27 REV_ID_B = 0x02,
28 REV_ID_C = 0x03,
29 REV_ID_D = 0x04
|
| /linux/include/linux/amba/ |
| H A D | sp810.h | 18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
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| /linux/arch/arm64/kernel/ |
| H A D | reloc_test_syms.S | 9 ldr x0, 0f
11 0: .quad sym64_abs
15 ldr w0, 0f
17 0: .long sym32_abs
21 adr x0, 0f
24 0: .short sym16_abs, 0
43 .space 0xff8
51 .space 0xffc
64 adr x1, 0f
68 0: .quad sym64_rel - .
[all …]
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| /linux/arch/arm/mach-omap2/ |
| H A D | omap4-sar-layout.h | 14 #define SAR_BANK1_OFFSET 0x0000
15 #define SAR_BANK2_OFFSET 0x1000
16 #define SAR_BANK3_OFFSET 0x2000
17 #define SAR_BANK4_OFFSET 0x3000
20 #define SCU_OFFSET0 0xfe4
21 #define SCU_OFFSET1 0xfe8
22 #define OMAP_TYPE_OFFSET 0xfec
23 #define L2X0_SAVE_OFFSET0 0xff0
24 #define L2X0_SAVE_OFFSET1 0xff4
25 #define L2X0_AUXCTRL_OFFSET 0xff8
[all …]
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| /linux/arch/arm64/include/asm/ |
| H A D | module.h | 42 __le32 add; /* add x16, x16, #0x.... */
49 ((u64)place & 0xfff) >= 0xff8; in is_forbidden_offset_for_adrp()
62 if (strcmp(name, secstrs + s->sh_name) == 0) in find_section()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/ |
| H A D | falcon.c | 33 int c = 0; in nvkm_falcon_oclass_get()
65 u32 dest = nvkm_rd32(device, base + 0x01c); in nvkm_falcon_intr()
66 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); in nvkm_falcon_intr()
67 u32 inst = nvkm_rd32(device, base + 0x050) & 0x3fffffff; in nvkm_falcon_intr()
73 if (intr & 0x00000040) { in nvkm_falcon_intr()
76 nvkm_wr32(device, base + 0x004, 0x00000040); in nvkm_falcon_intr()
77 intr &= ~0x00000040; in nvkm_falcon_intr()
81 if (intr & 0x00000010) { in nvkm_falcon_intr()
83 nvkm_wr32(device, base + 0x004, 0x00000010); in nvkm_falcon_intr()
84 intr &= ~0x00000010; in nvkm_falcon_intr()
[all …]
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| /linux/drivers/clocksource/ |
| H A D | nomadik-mtu.c | 28 #define MTU_IMSC 0x00 /* Interrupt mask set/clear */
29 #define MTU_RIS 0x04 /* Raw interrupt status */
30 #define MTU_MIS 0x08 /* Masked interrupt status */
31 #define MTU_ICR 0x0C /* Interrupt clear register */
33 /* per-timer registers take 0..3 as argument */
34 #define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
35 #define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
36 #define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
37 #define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
40 #define MTU_CRn_ENA 0x80
[all …]
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| /linux/sound/hda/codecs/ |
| H A D | ca0132_regs.h | 12 #define DSP_CHIP_OFFSET 0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT 0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT 0x3
19 #define DSP_DBGCNTL_EXEC_MASK 0xF
21 #define DSP_DBGCNTL_SS_LOBIT 0x4
22 #define DSP_DBGCNTL_SS_HIBIT 0x7
23 #define DSP_DBGCNTL_SS_MASK 0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT 0xA
26 #define DSP_DBGCNTL_STATE_HIBIT 0xD
[all …]
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| /linux/include/linux/mlx4/ |
| H A D | cmd.h | 43 MLX4_CMD_SYS_EN = 0x1,
44 MLX4_CMD_SYS_DIS = 0x2,
45 MLX4_CMD_MAP_FA = 0xfff,
46 MLX4_CMD_UNMAP_FA = 0xffe,
47 MLX4_CMD_RUN_FW = 0xff6,
48 MLX4_CMD_MOD_STAT_CFG = 0x34,
49 MLX4_CMD_QUERY_DEV_CAP = 0x3,
50 MLX4_CMD_QUERY_FW = 0x4,
51 MLX4_CMD_ENABLE_LAM = 0xff8,
52 MLX4_CMD_DISABLE_LAM = 0xff7,
[all …]
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| /linux/drivers/dma/ |
| H A D | ste_dma40_ll.h | 10 #define D40_DREG_PCBASE 0x400
35 #define D40_SREG_CFG_PHY_EVTL_POS 0
40 #define D40_SREG_ELEM_PHY_EIDX_POS 0
42 #define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
45 #define D40_SREG_LNK_PHY_TCP_POS 0
52 #define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
60 #define D40_SREG_ELEM_LOG_TCP_POS 0
62 #define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
66 #define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
72 #define D40_MEM_LCSP0_SPTR_POS 0
[all …]
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| /linux/sound/soc/ux500/ |
| H A D | ux500_msp_i2s.h | 32 #define MSP_BIG_ENDIAN 0x00000000
33 #define MSP_LITTLE_ENDIAN 0x00001000
34 #define MSP_UNEXPECTED_FS_ABORT 0x00000000
35 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000
36 #define MSP_NON_MODE_BIT_MASK 0x00009000
39 #define RX_ENABLE 0x00000001
40 #define RX_FIFO_ENABLE 0x00000002
41 #define RX_SYNC_SRG 0x00000010
42 #define RX_CLK_POL_RISING 0x00000020
43 #define RX_CLK_SEL_SRG 0x00000040
[all …]
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| /linux/arch/powerpc/boot/ |
| H A D | 4xx.c | 30 switch (pvr & 0xf0000ff0) { in chip_11_errata()
31 case 0x40000850: in chip_11_errata()
32 case 0x400008d0: in chip_11_errata()
33 case 0x200008d0: in chip_11_errata()
49 memsize = 0; in ibm4xx_sdram_fixup_memsize()
50 for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) { in ibm4xx_sdram_fixup_memsize()
57 dt_fixup_memory(0, memsize); in ibm4xx_sdram_fixup_memsize()
61 #define DCRN_MQ0_B0BAS 0x40
62 #define DCRN_MQ0_B1BAS 0x41
63 #define DCRN_MQ0_B2BAS 0x42
[all …]
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| /linux/tools/testing/selftests/powerpc/stringloops/ |
| H A D | memcmp_64.S | 48 cmpwi cr1,r3,0; \
75 * | y y y y y y y y y y y y y 0 1 2 | 3 4 5 6 7 8 9 a b c d e f z z z |
77 * 0xbbbb10 0xbbbb20 0xbbb30
84 * for example: 0xyyyyyyyyyyyyy012 for big endian
86 * for example: 0x3456789abcdefzzz for big endian
88 * for example: 0x0123456789abcdef for big endian.
102 cmpdi cr1,r5,0
120 1: lbz rA,0(r3)
121 lbz rB,0(r4)
149 li r3,0
[all …]
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| /linux/arch/powerpc/lib/ |
| H A D | memcmp_64.S | 48 cmpwi cr1,r3,0; \
75 * | y y y y y y y y y y y y y 0 1 2 | 3 4 5 6 7 8 9 a b c d e f z z z |
77 * 0xbbbb10 0xbbbb20 0xbbb30
84 * for example: 0xyyyyyyyyyyyyy012 for big endian
86 * for example: 0x3456789abcdefzzz for big endian
88 * for example: 0x0123456789abcdef for big endian.
102 cmpdi cr1,r5,0
120 1: lbz rA,0(r3)
121 lbz rB,0(r4)
149 li r3,0
[all …]
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| /linux/arch/arm/mach-lpc32xx/ |
| H A D | lpc32xx.h | 17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
|
| /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| H A D | aiutils.c | 35 #define SCC_SS_MASK 0x00000007
37 #define SCC_SS_LPO 0x00000000
39 #define SCC_SS_XTAL 0x00000001
41 #define SCC_SS_PCI 0x00000002
42 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
43 #define SCC_LF 0x00000200
44 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
45 #define SCC_LP 0x00000400
46 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
47 #define SCC_FS 0x00000800
[all …]
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| /linux/drivers/comedi/drivers/ |
| H A D | dt3000.c | 51 #define DPR_DAC_BUFFER (4 * 0x000)
52 #define DPR_ADC_BUFFER (4 * 0x800)
53 #define DPR_COMMAND (4 * 0xfd3)
54 #define DPR_SUBSYS (4 * 0xfd3)
55 #define DPR_SUBSYS_AI 0
61 #define DPR_ENCODE (4 * 0xfd4)
62 #define DPR_PARAMS(x) (4 * (0xfd5 + (x)))
63 #define DPR_TICK_REG_LO (4 * 0xff5)
64 #define DPR_TICK_REG_HI (4 * 0xff6)
65 #define DPR_DA_BUF_FRONT (4 * 0xff7)
[all …]
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| /linux/drivers/staging/vme_user/ |
| H A D | vme_tsi148.h | 16 #define PCI_VENDOR_ID_TUNDRA 0x10e3
20 #define PCI_DEVICE_ID_TUNDRA_TSI148 0x148
93 #define TSI148_PCFS_ID 0x0
94 #define TSI148_PCFS_CSR 0x4
95 #define TSI148_PCFS_CLASS 0x8
96 #define TSI148_PCFS_MISC0 0xC
97 #define TSI148_PCFS_MBARL 0x10
98 #define TSI148_PCFS_MBARU 0x14
99 #define TSI148_PCFS_SUBID 0x28
100 #define TSI148_PCFS_CAPP 0x34
[all …]
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| /linux/include/linux/ |
| H A D | coresight.h | 17 /* Peripheral id registers (0xFD0-0xFEC) */
18 #define CORESIGHT_PERIPHIDR4 0xfd0
19 #define CORESIGHT_PERIPHIDR5 0xfd4
20 #define CORESIGHT_PERIPHIDR6 0xfd8
21 #define CORESIGHT_PERIPHIDR7 0xfdC
22 #define CORESIGHT_PERIPHIDR0 0xfe0
23 #define CORESIGHT_PERIPHIDR1 0xfe4
24 #define CORESIGHT_PERIPHIDR2 0xfe8
25 #define CORESIGHT_PERIPHIDR3 0xfeC
26 /* Component id registers (0xFF0-0xFFC) */
[all …]
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| /linux/drivers/clk/stm32/ |
| H A D | stm32mp13_rcc.h | 11 #define RCC_SECCFGR 0x0
12 #define RCC_MP_SREQSETR 0x100
13 #define RCC_MP_SREQCLRR 0x104
14 #define RCC_MP_APRSTCR 0x108
15 #define RCC_MP_APRSTSR 0x10c
16 #define RCC_PWRLPDLYCR 0x110
17 #define RCC_MP_GRSTCSETR 0x114
18 #define RCC_BR_RSTSCLRR 0x118
19 #define RCC_MP_RSTSSETR 0x11c
20 #define RCC_MP_RSTSCLRR 0x120
[all …]
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| /linux/drivers/net/wireless/realtek/rtw88/ |
| H A D | rtw8822c.c | 21 #define IQK_DONE_8822C 0xaa
57 efuse->country_code[0] = map->country_code[0]; in rtw8822c_read_efuse()
60 efuse->regd = map->rf_board_option & 0x7; in rtw8822c_read_efuse()
65 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; in rtw8822c_read_efuse()
67 for (i = 0; i < 4; i++) in rtw8822c_read_efuse()
85 return 0; in rtw8822c_read_efuse()
115 u32 rf_addr[DACK_RF_8822C] = {0x8f}; in rtw8822c_dac_backup_reg()
116 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, in rtw8822c_dac_backup_reg()
117 0x1c3c, 0x1c24, 0x1d70, 0x9b4, in rtw8822c_dac_backup_reg()
118 0x1a00, 0x1a14, 0x1d58, 0x1c38, in rtw8822c_dac_backup_reg()
[all …]
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| /linux/drivers/infiniband/hw/mthca/ |
| H A D | mthca_cmd.c | 49 #define CMD_POLL_TOKEN 0xffff
52 HCR_IN_PARAM_OFFSET = 0x00,
53 HCR_IN_MODIFIER_OFFSET = 0x08,
54 HCR_OUT_PARAM_OFFSET = 0x0c,
55 HCR_TOKEN_OFFSET = 0x14,
56 HCR_STATUS_OFFSET = 0x18,
65 CMD_SYS_EN = 0x1,
66 CMD_SYS_DIS = 0x2,
67 CMD_MAP_FA = 0xfff,
68 CMD_UNMAP_FA = 0xffe,
[all …]
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| /linux/drivers/net/ethernet/microsoft/mana/ |
| H A D | gdma_main.c | 48 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; in mana_gd_init_pf_regs()
66 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; in mana_gd_init_vf_regs()
99 if (hwc && hwc->hwc_timeout == 0) in mana_need_log()
117 dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n", in mana_gd_query_max_resources()
155 return 0; in mana_gd_query_max_resources()
174 return 0; in mana_gd_query_hwc_timeout()
183 int found_dev = 0; in mana_gd_detect_devices()
193 dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err, in mana_gd_detect_devices()
198 for (i = 0; i < GDMA_DEV_LIST_SIZE && in mana_gd_detect_devices()
204 if (dev.as_uint32 == 0) in mana_gd_detect_devices()
[all …]
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| /linux/drivers/spi/ |
| H A D | spi-pl022.c | 54 #define DRIVE_TX 0
57 #define DO_NOT_QUEUE_DMA 0
66 #define SSP_CR0(r) (r + 0x000)
67 #define SSP_CR1(r) (r + 0x004)
68 #define SSP_DR(r) (r + 0x008)
69 #define SSP_SR(r) (r + 0x00C)
70 #define SSP_CPSR(r) (r + 0x010)
71 #define SSP_IMSC(r) (r + 0x014)
72 #define SSP_RIS(r) (r + 0x018)
73 #define SSP_MIS(r) (r + 0x01C)
[all …]
|