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/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-ixdpg425.dts26 memory@0 {
29 reg = <0x00000000 0x02000000>;
43 flash@0,0 {
50 reg = <0 0x00000000 0x1000000>;
58 fis-index-block = <0x7f>;
72 interrupt-map-mask = <0xf800 0 0 7>;
75 <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */
76 <0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */
77 <0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */
78 <0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */
[all …]
H A Dintel-ixp42x-freecom-fsg-3.dts19 memory@0 {
22 reg = <0x00000000 0x4000000>;
65 #size-cells = <0>;
76 reg = <0x28>;
80 reg = <0x6f>;
86 flash@0,0 {
92 reg = <0 0x00000000 0x400000>;
96 /* Eraseblock at 0x3e0000 */
97 fis-index-block = <0x1f>;
102 syscon@2,0 {
[all …]
H A Dintel-ixp42x-goramo-multilink.dts25 memory@0 {
31 reg = <0x00000000 0x4000000>;
53 cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
68 flash@0,0 {
74 reg = <0 0x00000000 0x1000000>;
78 /* Eraseblock at 0x0fe0000 */
79 fis-index-block = <0x7f>;
93 interrupt-map-mask = <0xf800 0 0 7>;
96 <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
97 <0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
[all …]
/linux/arch/powerpc/boot/dts/
H A Dstorcenter.dts30 #size-cells = <0>;
32 PowerPC,8241@0 {
34 reg = <0>;
37 bus-frequency = <0>; /* from bootwrapper */
47 reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
55 store-gathering = <0>; /* 0 == off, !0 == on */
56 ranges = <0x0 0xfc000000 0x100000>;
57 reg = <0xfc000000 0x100000>; /* EUMB */
58 bus-frequency = <0>; /* fixed by loader */
62 #size-cells = <0>;
[all …]
H A Dmvme5100.dts26 #size-cells = <0>;
30 reg = <0x0>;
44 reg = <0x0 0x20000000>;
51 ranges = <0x0 0xfef80000 0x10000>;
52 reg = <0xfef80000 0x10000>;
57 reg = <0x8000 0x80>;
68 reg = <0x8200 0x80>;
78 #address-cells = <0>;
82 reg = <0xf3f80000 0x40000>;
92 reg = <0xfec00000 0x400000>;
[all …]
H A Dstx_gp3_8560.dts27 #size-cells = <0>;
29 PowerPC,8560@0 {
31 reg = <0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x10000000>;
52 ranges = <0 0xfdf00000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dmstar,ssd202d-rtc.yaml10 - Daniel Palmer <daniel@0x0f.com>
33 reg = <0x6800 0x200>;
/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/linux/drivers/gpu/drm/radeon/
H A Devergreen_reg.h28 #define TN_SMC_IND_INDEX_0 0x200
29 #define TN_SMC_IND_DATA_0 0x204
32 #define EVERGREEN_PIF_PHY0_INDEX 0x8
33 #define EVERGREEN_PIF_PHY0_DATA 0xc
34 #define EVERGREEN_PIF_PHY1_INDEX 0x10
35 #define EVERGREEN_PIF_PHY1_DATA 0x14
36 #define EVERGREEN_MM_INDEX_HI 0x18
38 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
39 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
40 #define EVERGREEN_D3VGA_CONTROL 0x3e0
[all …]
H A Dr500_reg.h32 #define R300_GA_POLY_MODE 0x4288
33 # define R300_FRONT_PTYPE_POINT (0 << 4)
36 # define R300_BACK_PTYPE_POINT (0 << 7)
39 #define R300_GA_ROUND_MODE 0x428c
40 # define R300_GEOMETRY_ROUND_TRUNC (0 << 0)
41 # define R300_GEOMETRY_ROUND_NEAREST (1 << 0)
42 # define R300_COLOR_ROUND_TRUNC (0 << 2)
44 #define R300_GB_MSPOS0 0x4010
45 # define R300_MS_X0_SHIFT 0
53 #define R300_GB_MSPOS1 0x4014
[all …]
/linux/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv10.c34 u32 pipe_0x0000[0x040/4];
35 u32 pipe_0x0040[0x010/4];
36 u32 pipe_0x0200[0x0c0/4];
37 u32 pipe_0x4400[0x080/4];
38 u32 pipe_0x6400[0x3b0/4];
39 u32 pipe_0x6800[0x2f0/4];
40 u32 pipe_0x6c00[0x030/4];
41 u32 pipe_0x7000[0x130/4];
42 u32 pipe_0x7400[0x0c0/4];
43 u32 pipe_0x7800[0x0c0/4];
[all …]
/linux/drivers/media/usb/gspca/
H A Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
H A Dtouptek.c24 * 0.000400, 0x0002
25 * 0.001000, 0x0005
26 * 0.005000, 0x0019
27 * 0.020000, 0x0064
28 * 0.080000, 0x0190
29 * 0.400000, 0x07D0
30 * 1.000000, 0x1388
31 * 2.000000, 0x2710
34 * 0x1000: master channel enable bit
35 * 0x007F: low gain bits
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson64-2k1000.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
20 reg = <0x0>;
27 #clock-cells = <0>;
33 #address-cells = <0>;
43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
44 0 0x40000000 0 0x40000000 0 0x40000000
45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
51 ranges = <1 0x0 0x0 0x18000000 0x4000>;
56 reg = <0 0x1fe07000 0 0x422>;
[all …]
/linux/drivers/gpu/drm/amd/display/include/
H A Ddal_asic_id.h34 #define SI_TAHITI_P_A0 0x01
35 #define SI_TAHITI_P_B0 0x05
36 #define SI_TAHITI_P_B1 0x06
37 #define SI_PITCAIRN_PM_A0 0x14
38 #define SI_PITCAIRN_PM_A1 0x15
39 #define SI_CAPEVERDE_M_A0 0x28
40 #define SI_CAPEVERDE_M_A1 0x29
41 #define SI_OLAND_M_A0 0x3C
42 #define SI_HAINAN_V_A0 0x46
44 #define SI_UNKNOWN 0xFF
[all …]
/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0x0>;
28 d-cache-size = <0x8000>;
31 i-cache-size = <0xc000>;
40 reg = <0x1>;
42 d-cache-size = <0x8000>;
45 i-cache-size = <0xc000>;
54 reg = <0x2>;
56 d-cache-size = <0x8000>;
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8922a.c25 {2, 1641, grp_0}, /* ACH 0 */
37 {0, 0, 0}, /* FWCMDQ */
38 {0, 0, 0}, /* BMC */
39 {0, 0, 0}, /* H2D */
43 1651, /* Group 0 */
46 0, /* WP threshold */
165 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
172 0xf},
175 0x0},
219 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drswitch.h17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
23 for (; i-- > 0; ) \
44 #define RSWITCH_TOP_OFFSET 0x00008000
45 #define RSWITCH_COMA_OFFSET 0x00009000
46 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
47 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
48 #define RSWITCH_GWCA0_OFFSET 0x00010000
49 #define RSWITCH_GWCA1_OFFSET 0x00012000
55 #define GWCA_INDEX 0
57 #define GWCA_IPV_NUM 0
[all …]
/linux/arch/arm/mm/
H A Dalignment.c41 #define CODING_BITS(i) (i & 0x0e000000)
42 #define COND_BITS(i) (i & 0xf0000000)
50 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
59 #define REGMASK_BITS(i) (i & 0xffff)
60 #define OFFSET_BITS(i) (i & 0x0fff)
62 #define IS_SHIFT(i) (i & 0x0ff0)
63 #define SHIFT_BITS(i) ((i >> 7) & 0x1f)
64 #define SHIFT_TYPE(i) (i & 0x60)
65 #define SHIFT_LSL 0x00
66 #define SHIFT_LSR 0x20
[all …]
/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]

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