Lines Matching +full:0 +full:x6800
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
64 #define AR5K_RXDP 0x000c
69 #define AR5K_CFG 0x0014 /* Register Address */
70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
71 #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */
72 #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
73 #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
74 #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
75 #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */
76 #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */
77 #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */
78 #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */
79 #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */
81 #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */
82 #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */
83 #define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */
89 #define AR5K_IER 0x0024 /* Register Address */
90 #define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */
91 #define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */
95 * 0x0028 is Beacon Control Register on 5210
102 #define AR5K_BCR 0x0028 /* Register Address */
103 #define AR5K_BCR_AP 0x00000000 /* AP mode */
104 #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */
105 #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */
106 #define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */
107 #define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */
108 #define AR5K_BCR_BCGET 0x00000010
113 #define AR5K_RTSD0 0x0028 /* Register Address */
114 #define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */
115 #define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */
116 #define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/
118 #define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/
120 #define AR5K_RTSD0_18 0xff000000 /* 16Mb*/
125 * 0x002c is Beacon Status Register on 5210
139 #define AR5K_BSR 0x002c /* Register Address */
140 #define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */
141 #define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */
142 #define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */
143 #define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */
144 #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */
145 #define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */
146 #define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */
147 #define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */
148 #define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */
149 #define AR5K_BSR_SWBA_CNT 0x00ff0000
154 #define AR5K_RTSD1 0x002c /* Register Address */
155 #define AR5K_RTSD1_24 0x000000ff /* 24Mb */
156 #define AR5K_RTSD1_24_S 0
157 #define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */
159 #define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */
161 #define AR5K_RTSD1_54 0xff000000 /* 54Mb */
168 #define AR5K_TXCFG 0x0030 /* Register Address */
169 #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */
170 #define AR5K_TXCFG_SDMAMR_S 0
171 #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */
172 #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */
173 #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Trigger level mask */
175 #define AR5K_TXCFG_TXFULL_0B 0x00000000
176 #define AR5K_TXCFG_TXFULL_64B 0x00000010
177 #define AR5K_TXCFG_TXFULL_128B 0x00000020
178 #define AR5K_TXCFG_TXFULL_192B 0x00000030
179 #define AR5K_TXCFG_TXFULL_256B 0x00000040
180 #define AR5K_TXCFG_TXCONT_EN 0x00000080
181 #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */
182 #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */
183 #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */
184 #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */
185 #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */
186 #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */
187 #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
188 #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */
189 #define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */
190 #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */
195 #define AR5K_RXCFG 0x0034 /* Register Address */
196 #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */
197 #define AR5K_RXCFG_SDMAMW_S 0
198 #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */
199 #define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */
200 #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */
201 #define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */
202 #define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */
208 #define AR5K_RXJLA 0x0038
213 #define AR5K_MIBC 0x0040 /* Register Address */
214 #define AR5K_MIBC_COW 0x00000001 /* Counter Overflow Warning */
215 #define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */
216 #define AR5K_MIBC_CMC 0x00000004 /* Clear MIB Counters */
217 #define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */
222 #define AR5K_TOPS 0x0044
223 #define AR5K_TOPS_M 0x0000ffff
228 #define AR5K_RXNOFRM 0x0048
229 #define AR5K_RXNOFRM_M 0x000003ff
234 #define AR5K_TXNOFRM 0x004c
235 #define AR5K_TXNOFRM_M 0x000003ff
236 #define AR5K_TXNOFRM_QCU 0x000ffc00
242 #define AR5K_RPGTO 0x0050
243 #define AR5K_RPGTO_M 0x000003ff
248 #define AR5K_RFCNT 0x0054
249 #define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */
250 #define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */
256 #define AR5K_MISC 0x0058 /* Register Address */
257 #define AR5K_MISC_DMA_OBS_M 0x000001e0
259 #define AR5K_MISC_MISC_OBS_M 0x00000e00
261 #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
263 #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
265 #define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */
266 #define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */
272 #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */
273 #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */
274 #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */
288 #define AR5K_ISR 0x001c /* Register Address [5210] */
289 #define AR5K_PISR 0x0080 /* Register Address [5211+] */
290 #define AR5K_ISR_RXOK 0x00000001 /* Frame successfully received */
291 #define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */
292 #define AR5K_ISR_RXERR 0x00000004 /* Receive error */
293 #define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */
294 #define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */
295 #define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */
296 #define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */
297 #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */
298 #define AR5K_ISR_TXERR 0x00000100 /* Transmit error */
299 #define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout)
303 #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */
304 #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */
305 #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */
306 #define AR5K_ISR_SWI 0x00002000 /* Software interrupt */
307 #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */
308 #define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */
309 #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */
310 #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
311 #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */
312 #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+]
314 #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */
315 #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
316 #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */
317 #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */
318 #define AR5K_ISR_DPERR 0x00400000 /* Bus parity error [5210] */
319 #define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
320 #define AR5K_ISR_TIM 0x00800000 /* [5211+] */
321 #define AR5K_ISR_BCNMISC 0x00800000 /* Misc beacon related interrupt
324 #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */
325 #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
326 #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
327 #define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
336 * Secondary status registers [5211+] (0 - 4)
338 * These give the status for each QCU, only QCUs 0-9 are
341 #define AR5K_SISR0 0x0084 /* Register Address [5211+] */
342 #define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
343 #define AR5K_SISR0_QCU_TXOK_S 0
344 #define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
347 #define AR5K_SISR1 0x0088 /* Register Address [5211+] */
348 #define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
349 #define AR5K_SISR1_QCU_TXERR_S 0
350 #define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
353 #define AR5K_SISR2 0x008c /* Register Address [5211+] */
354 #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
355 #define AR5K_SISR2_QCU_TXURN_S 0
356 #define AR5K_SISR2_MCABT 0x00010000 /* Master Cycle Abort */
357 #define AR5K_SISR2_SSERR 0x00020000 /* Signaled System Error */
358 #define AR5K_SISR2_DPERR 0x00040000 /* Bus parity error */
359 #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */
360 #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */
361 #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */
362 #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
363 #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
364 #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */
365 #define AR5K_SISR2_TSFOOR 0x80000000 /* TSF Out of range */
367 #define AR5K_SISR3 0x0090 /* Register Address [5211+] */
368 #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
369 #define AR5K_SISR3_QCBRORN_S 0
370 #define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
373 #define AR5K_SISR4 0x0094 /* Register Address [5211+] */
374 #define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */
375 #define AR5K_SISR4_QTRIG_S 0
380 #define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */
381 #define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */
382 #define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */
383 #define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */
384 #define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */
385 #define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */
393 #define AR5K_IMR 0x0020 /* Register Address [5210] */
394 #define AR5K_PIMR 0x00a0 /* Register Address [5211+] */
395 #define AR5K_IMR_RXOK 0x00000001 /* Frame successfully received*/
396 #define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/
397 #define AR5K_IMR_RXERR 0x00000004 /* Receive error*/
398 #define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/
399 #define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/
400 #define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/
401 #define AR5K_IMR_TXOK 0x00000040 /* Frame successfully transmitted*/
402 #define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/
403 #define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/
404 #define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout)*/
405 #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/
406 #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/
407 #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/
408 #define AR5K_IMR_SWI 0x00002000 /* Software interrupt */
409 #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/
410 #define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */
411 #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/
412 #define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
413 #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/
414 #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
415 #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */
416 #define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
417 #define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/
418 #define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */
419 #define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */
420 #define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
421 #define AR5K_IMR_TIM 0x00800000 /* [5211+] */
422 #define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
424 #define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/
425 #define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */
426 #define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */
427 #define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
430 * Secondary interrupt mask registers [5211+] (0 - 4)
432 #define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */
433 #define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
434 #define AR5K_SIMR0_QCU_TXOK_S 0
435 #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
438 #define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */
439 #define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
440 #define AR5K_SIMR1_QCU_TXERR_S 0
441 #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
444 #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */
445 #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
446 #define AR5K_SIMR2_QCU_TXURN_S 0
447 #define AR5K_SIMR2_MCABT 0x00010000 /* Master Cycle Abort */
448 #define AR5K_SIMR2_SSERR 0x00020000 /* Signaled System Error */
449 #define AR5K_SIMR2_DPERR 0x00040000 /* Bus parity error */
450 #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */
451 #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */
452 #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */
453 #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
454 #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
455 #define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */
456 #define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */
458 #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */
459 #define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
460 #define AR5K_SIMR3_QCBRORN_S 0
461 #define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
464 #define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */
465 #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */
466 #define AR5K_SIMR4_QTRIG_S 0
469 * DMA Debug registers 0-7
470 * 0xe0 - 0xfc
476 #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */
477 #define AR5K_DCM_DATA 0x0404 /*Decompression mask data */
482 #define AR5K_WOW_PCFG 0x0410 /* Register Address */
483 #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */
484 #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */
485 #define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */
486 #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */
487 #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */
488 #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */
489 #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */
490 #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */
491 #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */
496 #define AR5K_WOW_PAT_IDX 0x0414
501 #define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */
502 #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */
503 #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */
504 #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */
505 #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */
506 #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */
507 #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */
512 #define AR5K_DCCFG 0x0420 /* Register Address */
513 #define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */
514 #define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */
515 #define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */
516 #define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */
521 #define AR5K_CCFG 0x0600 /* Register Address */
522 #define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */
523 #define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */
525 #define AR5K_CCFG_CCU 0x0604 /* Register Address */
526 #define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */
527 #define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */
528 #define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */
529 #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */
530 #define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */
535 #define AR5K_CPC0 0x0610 /* Compression performance counter 0 */
536 #define AR5K_CPC1 0x0614 /* Compression performance counter 1*/
537 #define AR5K_CPC2 0x0618 /* Compression performance counter 2 */
538 #define AR5K_CPC3 0x061c /* Compression performance counter 3 */
539 #define AR5K_CPCOVF 0x0620 /* Compression performance overflow */
545 * Card has 12 TX Queues but i see that only 0-9 are used (?)
547 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
548 * configuration register (0x08c0 - 0x08ec), a ready time configuration
549 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
550 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
567 #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */
573 #define AR5K_QCU_TXE 0x0840
580 #define AR5K_QCU_TXD 0x0880
587 #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */
588 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */
589 #define AR5K_QCU_CBRCFG_INTVAL_S 0
590 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */
597 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */
598 #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */
599 #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
600 #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */
606 #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */
607 #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff
612 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */
613 #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff
618 #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
619 #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame scheduling mask */
620 #define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */
625 #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */
626 #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */
627 #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */
628 #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */
629 #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */
630 #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */
631 #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */
632 #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */
633 #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */
640 #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */
641 #define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */
642 #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */
648 #define AR5K_QCU_RDYTIMESHDN 0x0a40
649 #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff
654 #define AR5K_QCU_CBB_SELECT 0x0b00
655 #define AR5K_QCU_CBB_ADDR 0x0b04
662 #define AR5K_QCU_CBCFG 0x0b08
673 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
674 * a retry limit register (0x1080 - 0x10ac), a channel time register
675 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
676 * a sequence number register (0x1140 - 0x116c). It seems that "global"
685 #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */
686 #define AR5K_DCU_QCUMASK_M 0x000003ff
692 #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */
693 #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */
694 #define AR5K_DCU_LCL_IFS_CW_MIN_S 0
695 #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */
697 #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */
699 #define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */
706 #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */
707 #define AR5K_DCU_RETRY_LMT_RTS 0x0000000f /* RTS failure limit. Transmission fails if no CTS is re…
708 #define AR5K_DCU_RETRY_LMT_RTS_S 0
709 #define AR5K_DCU_RETRY_LMT_STA_RTS 0x00003f00 /* STA RTS failure limit. If exceeded CW reset */
711 #define AR5K_DCU_RETRY_LMT_STA_DATA 0x000fc000 /* STA data failure limit. If exceeded CW reset. */
718 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */
719 #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */
720 #define AR5K_DCU_CHAN_TIME_DUR_S 0
721 #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */
736 #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
737 #define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */
738 #define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series
741 #define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series
743 #define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */
744 #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */
745 #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
746 #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */
747 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
748 #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */
749 #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
751 #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */
752 #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */
754 #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */
757 #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */
758 #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */
759 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */
760 #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */
761 #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */
762 #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */
768 #define AR5K_DCU_SEQNUM_BASE 0x1140
769 #define AR5K_DCU_SEQNUM_M 0x00000fff
775 #define AR5K_DCU_GBL_IFS_SIFS 0x1030
776 #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
781 #define AR5K_DCU_GBL_IFS_SLOT 0x1070
782 #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
787 #define AR5K_DCU_GBL_IFS_EIFS 0x10b0
788 #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
800 #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */
801 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */
802 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */
803 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */
805 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */
807 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */
808 #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */
809 #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */
810 #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */
815 #define AR5K_DCU_FP 0x1230 /* Register Address */
816 #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */
817 #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */
818 #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */
823 #define AR5K_DCU_TXP 0x1270 /* Register Address */
824 #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */
825 #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */
828 * DCU transmit filter table 0 (32 entries)
832 #define AR5K_DCU_TX_FILTER_0_BASE 0x1038
838 #define AR5K_DCU_TX_FILTER_1_BASE 0x103c
844 #define AR5K_DCU_TX_FILTER_CLR 0x143c
849 #define AR5K_DCU_TX_FILTER_SET 0x147c
854 #define AR5K_RESET_CTL 0x4000 /* Register Address */
855 #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */
856 #define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */
857 #define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */
858 #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */
859 #define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */
860 #define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */
865 #define AR5K_SLEEP_CTL 0x4004 /* Register Address */
866 #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */
867 #define AR5K_SLEEP_CTL_SLDUR_S 0
868 #define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */
870 #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */
871 #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */
872 #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */
873 #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */
874 #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */
875 #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */
876 #define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */
881 #define AR5K_INTPEND 0x4008
882 #define AR5K_INTPEND_M 0x00000001
887 #define AR5K_SFR 0x400c
888 #define AR5K_SFR_EN 0x00000001
894 #define AR5K_PCICFG 0x4010 /* Register Address */
895 #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */
896 #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */
897 #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */
898 #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */
900 #define AR5K_PCICFG_EESIZE_4K 0 /* 4K */
904 #define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */
905 #define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */
906 #define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */
907 #define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */
908 #define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */
909 #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */
910 #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */
911 #define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */
912 #define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */
913 #define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even with pending interrupts*/
914 #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */
915 #define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */
916 #define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */
917 #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */
918 #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */
919 #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */
920 #define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */
922 #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */
926 #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */
936 * Mode 0 -> always input
937 * Mode 1 -> output when GPIODO for this GPIO is set to 0
947 #define AR5K_GPIOCR 0x4014 /* Register Address */
948 #define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */
949 #define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */
950 #define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */
951 #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */
960 #define AR5K_GPIODO 0x4018
965 #define AR5K_GPIODI 0x401c
966 #define AR5K_GPIODI_M 0x0000002f
971 #define AR5K_SREV 0x4020 /* Register Address */
972 #define AR5K_SREV_REV 0x0000000f /* Mask for revision */
973 #define AR5K_SREV_REV_S 0
974 #define AR5K_SREV_VER 0x000000ff /* Mask for version */
980 #define AR5K_TXEPOST 0x4028
985 #define AR5K_QCU_SLEEP_MASK 0x402c
987 /* 0x4068 is compression buffer configuration
995 #define AR5K_5414_CBCFG 0x4068
996 #define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */
1002 #define AR5K_PCIE_PM_CTL 0x4068 /* Register address */
1004 #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1
1006 #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */
1007 #define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */
1008 #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes
1011 #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */
1012 #define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */
1013 #define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */
1014 #define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
1015 #define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
1016 #define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
1017 #define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
1022 #define AR5K_PCIE_WAEN 0x407c
1028 #define AR5K_PCIE_SERDES 0x4080
1029 #define AR5K_PCIE_SERDES_RESET 0x4084
1037 * read data register for 5210 is at 0x6800 and
1038 * status register is at 0x6c00. There is also
1068 #define AR5K_EEPROM_BASE 0x6000
1073 #define AR5K_EEPROM_DATA_5211 0x6004
1074 #define AR5K_EEPROM_DATA_5210 0x6800
1081 #define AR5K_EEPROM_CMD 0x6008 /* Register Address */
1082 #define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */
1083 #define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */
1084 #define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */
1089 #define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */
1090 #define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */
1093 #define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */
1094 #define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */
1095 #define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */
1096 #define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */
1101 #define AR5K_EEPROM_CFG 0x6010 /* Register Address */
1102 #define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */
1103 #define AR5K_EEPROM_CFG_SIZE_AUTO 0
1107 #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */
1108 #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */
1110 #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
1113 #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */
1115 #define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */
1120 * Range 0x7000 - 0x7ce0
1130 #define AR5K_PCU_MIN 0x8000
1131 #define AR5K_PCU_MAX 0x8fff
1136 #define AR5K_STA_ID0 0x8000
1137 #define AR5K_STA_ID0_ARRD_L32 0xffffffff
1142 #define AR5K_STA_ID1 0x8004 /* Register Address */
1143 #define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC address */
1144 #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */
1145 #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
1146 #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */
1147 #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */
1148 #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */
1149 #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */
1150 #define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/
1153 #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */
1154 #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */
1155 #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */
1156 #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Rate to use for ACK/CTS. 0: highest mandatory rate <…
1157 #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* 802.11b base rate. 0: 1, 2, 5.5 and 11Mbps; 1: 1 a…
1158 #define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */
1159 #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */
1160 #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */
1161 #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */
1162 #define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */
1163 #define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */
1173 #define AR5K_BSS_ID0 0x8008
1180 #define AR5K_BSS_ID1 0x800c
1181 #define AR5K_BSS_ID1_AID 0xffff0000
1187 #define AR5K_SLOT_TIME 0x8010
1192 #define AR5K_TIME_OUT 0x8014 /* Register Address */
1193 #define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */
1194 #define AR5K_TIME_OUT_ACK_S 0
1195 #define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */
1201 #define AR5K_RSSI_THR 0x8018 /* Register Address */
1202 #define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */
1203 #define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */
1205 #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */
1224 #define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */
1225 #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */
1226 #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
1227 #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */
1229 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */
1231 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */
1233 #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */
1239 #define AR5K_USEC_5210 0x8020 /* Register Address [5210] */
1240 #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */
1243 #define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */
1244 #define AR5K_USEC_1_S 0
1245 #define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32MHz clock */
1247 #define AR5K_USEC_TX_LATENCY_5211 0x007fc000
1249 #define AR5K_USEC_RX_LATENCY_5211 0x1f800000
1251 #define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */
1253 #define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */
1259 #define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */
1260 #define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */
1263 #define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */
1264 #define AR5K_BEACON_PERIOD_S 0
1265 #define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */
1267 #define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */
1268 #define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */
1273 #define AR5K_CFP_PERIOD_5210 0x8028
1274 #define AR5K_CFP_PERIOD_5211 0x8024
1281 #define AR5K_TIMER0_5210 0x802c
1282 #define AR5K_TIMER0_5211 0x8028
1289 #define AR5K_TIMER1_5210 0x8030
1290 #define AR5K_TIMER1_5211 0x802c
1297 #define AR5K_TIMER2_5210 0x8034
1298 #define AR5K_TIMER2_5211 0x8030
1305 #define AR5K_TIMER3_5210 0x8038
1306 #define AR5K_TIMER3_5211 0x8034
1314 #define AR5K_IFS0 0x8040
1315 #define AR5K_IFS0_SIFS 0x000007ff
1316 #define AR5K_IFS0_SIFS_S 0
1317 #define AR5K_IFS0_DIFS 0x007ff800
1323 #define AR5K_IFS1 0x8044
1324 #define AR5K_IFS1_PIFS 0x00000fff
1325 #define AR5K_IFS1_PIFS_S 0
1326 #define AR5K_IFS1_EIFS 0x03fff000
1328 #define AR5K_IFS1_CS_EN 0x04000000
1334 #define AR5K_CFP_DUR_5210 0x8048
1335 #define AR5K_CFP_DUR_5211 0x8038
1342 #define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */
1343 #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */
1346 #define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */
1347 #define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */
1348 #define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */
1349 #define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */
1350 #define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */
1351 #define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */
1352 #define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */
1353 #define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */
1354 #define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */
1355 #define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */
1356 #define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */
1357 #define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */
1368 #define AR5K_MCAST_FILTER0_5210 0x8050
1369 #define AR5K_MCAST_FILTER0_5211 0x8040
1376 #define AR5K_MCAST_FILTER1_5210 0x8054
1377 #define AR5K_MCAST_FILTER1_5211 0x8044
1385 #define AR5K_TX_MASK0 0x8058
1390 #define AR5K_TX_MASK1 0x805c
1395 #define AR5K_CLR_TMASK 0x8060
1400 #define AR5K_TRIG_LVL 0x8064
1408 #define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */
1409 #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */
1412 #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */
1413 #define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */
1414 #define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */
1415 #define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable HW encryption */
1416 #define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable HW decryption */
1417 #define AR5K_DIAG_SW_DIS_TX_5210 0x00000020 /* Disable transmit [5210] */
1418 #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable receive */
1419 #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
1422 #define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* TX Data Loopback (i guess it goes with DIS_TX) [5…
1423 #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
1426 #define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Generate invalid TX FCS */
1427 #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
1430 #define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Add 56 bytes of channel info before the frame dat…
1431 #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
1434 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */
1435 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200
1438 #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */
1439 #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */
1440 #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */
1442 #define AR5K_DIAG_SW_DIS_SEQ_INC_5210 0x00040000 /* Disable seqnum increment (?)[5210] */
1443 #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
1444 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */
1447 #define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */
1449 #define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x00100000 /* Ignore carrier sense */
1450 #define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x00200000 /* Ignore virtual carrier sense */
1451 #define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH 0x00400000 /* Force channel idle high */
1452 #define AR5K_DIAG_SW_PHEAR_ME 0x00800000 /* ??? */
1457 #define AR5K_TSF_L32_5210 0x806c
1458 #define AR5K_TSF_L32_5211 0x804c
1465 #define AR5K_TSF_U32_5210 0x8070
1466 #define AR5K_TSF_U32_5211 0x8050
1473 #define AR5K_LAST_TSTP 0x8080
1478 #define AR5K_ADDAC_TEST 0x8054 /* Register Address */
1479 #define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */
1480 #define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */
1481 #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */
1482 #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */
1483 #define AR5K_ADDAC_TEST_USE_U8 0x00004000 /* Use upper 8 bits */
1484 #define AR5K_ADDAC_TEST_MSB 0x00008000 /* State of MSB */
1485 #define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000 /* Trigger select */
1486 #define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */
1487 #define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */
1488 #define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */
1489 #define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */
1494 #define AR5K_DEFAULT_ANTENNA 0x8058
1500 #define AR5K_FRAME_CTL_QOSM 0x805c
1505 #define AR5K_SEQ_MASK 0x8060
1510 #define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */
1511 #define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */
1512 #define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */
1517 #define AR5K_BACKOFF 0x8088 /* Register Address [5210] */
1518 #define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */
1519 #define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */
1526 #define AR5K_NAV_5210 0x808c
1527 #define AR5K_NAV_5211 0x8084
1534 * max value is 0xc000, if this is reached we get a MIB interrupt.
1541 #define AR5K_RTS_OK_5210 0x8090
1542 #define AR5K_RTS_OK_5211 0x8088
1549 #define AR5K_RTS_FAIL_5210 0x8094
1550 #define AR5K_RTS_FAIL_5211 0x808c
1557 #define AR5K_ACK_FAIL_5210 0x8098
1558 #define AR5K_ACK_FAIL_5211 0x8090
1565 #define AR5K_FCS_FAIL_5210 0x809c
1566 #define AR5K_FCS_FAIL_5211 0x8094
1573 #define AR5K_BEACON_CNT_5210 0x80a0
1574 #define AR5K_BEACON_CNT_5211 0x8098
1584 #define AR5K_TPC 0x80e8
1585 #define AR5K_TPC_ACK 0x0000003f /* ack frames */
1586 #define AR5K_TPC_ACK_S 0
1587 #define AR5K_TPC_CTS 0x00003f00 /* cts frames */
1589 #define AR5K_TPC_CHIRP 0x003f0000 /* chirp frames */
1591 #define AR5K_TPC_DOPPLER 0x0f000000 /* doppler chirp span */
1597 #define AR5K_XRMODE 0x80c0 /* Register Address */
1598 #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */
1599 #define AR5K_XRMODE_POLL_TYPE_S 0
1600 #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */
1602 #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 /* Wait for poll */
1603 #define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */
1604 #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */
1610 #define AR5K_XRDELAY 0x80c4 /* Register Address */
1611 #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */
1612 #define AR5K_XRDELAY_SLOT_DELAY_S 0
1613 #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */
1619 #define AR5K_XRTIMEOUT 0x80c8 /* Register Address */
1620 #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */
1621 #define AR5K_XRTIMEOUT_CHIRP_S 0
1622 #define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */
1628 #define AR5K_XRCHIRP 0x80cc /* Register Address */
1629 #define AR5K_XRCHIRP_SEND 0x00000001 /* Send CHIRP */
1630 #define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */
1635 #define AR5K_XRSTOMP 0x80d0 /* Register Address */
1636 #define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */
1637 #define AR5K_XRSTOMP_RX 0x00000002 /* Stomp Rx (?) */
1638 #define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */
1639 #define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */
1640 #define AR5K_XRSTOMP_DATA 0x00000010 /* Stomp data (?)*/
1641 #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */
1646 #define AR5K_SLEEP0 0x80d4 /* Register Address */
1647 #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */
1648 #define AR5K_SLEEP0_NEXT_DTIM_S 0
1649 #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */
1650 #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enhanced sleep control */
1651 #define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */
1657 #define AR5K_SLEEP1 0x80d8 /* Register Address */
1658 #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */
1659 #define AR5K_SLEEP1_NEXT_TIM_S 0
1660 #define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */
1666 #define AR5K_SLEEP2 0x80dc /* Register Address */
1667 #define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */
1668 #define AR5K_SLEEP2_TIM_PER_S 0
1669 #define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */
1678 #define AR5K_TXPC 0x80e8 /* Register Address */
1679 #define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */
1680 #define AR5K_TXPC_ACK_S 0
1681 #define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */
1683 #define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */
1685 #define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */
1697 #define AR5K_PROFCNT_TX 0x80ec /* Tx count */
1698 #define AR5K_PROFCNT_RX 0x80f0 /* Rx count */
1699 #define AR5K_PROFCNT_RXCLR 0x80f4 /* Busy count */
1700 #define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle counter */
1705 #define AR5K_QUIET_CTL1 0x80fc /* Register Address */
1706 #define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */
1707 #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0
1708 #define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */
1709 #define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 /* Send ACK/CTS during quiet period */
1711 #define AR5K_QUIET_CTL2 0x8100 /* Register Address */
1712 #define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */
1713 #define AR5K_QUIET_CTL2_QT_PER_S 0
1714 #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */
1720 #define AR5K_TSF_PARM 0x8104 /* Register Address */
1721 #define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */
1722 #define AR5K_TSF_PARM_INC_S 0
1727 #define AR5K_QOS_NOACK 0x8108 /* Register Address */
1728 #define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f /* ??? */
1729 #define AR5K_QOS_NOACK_2BIT_VALUES_S 0
1730 #define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */
1732 #define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */
1738 #define AR5K_PHY_ERR_FIL 0x810c
1739 #define AR5K_PHY_ERR_FIL_RADAR 0x00000020 /* Radar signal */
1740 #define AR5K_PHY_ERR_FIL_OFDM 0x00020000 /* OFDM false detect (ANI) */
1741 #define AR5K_PHY_ERR_FIL_CCK 0x02000000 /* CCK false detect (ANI) */
1746 #define AR5K_XRLAT_TX 0x8110
1751 #define AR5K_ACKSIFS 0x8114 /* Register Address */
1752 #define AR5K_ACKSIFS_INC 0x00000000 /* ACK SIFS Increment (field) */
1757 #define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */
1759 #define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */
1764 #define AR5K_MIC_QOS_SEL 0x811c
1770 #define AR5K_MISC_MODE 0x8120 /* Register Address */
1771 #define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001 /* Force BSSID match */
1772 #define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 /* ACK SIFS memory (?) */
1773 #define AR5K_MISC_MODE_COMBINED_MIC 0x00000004 /* use rx/tx MIC key */
1779 #define AR5K_OFDM_FIL_CNT 0x8124
1784 #define AR5K_CCK_FIL_CNT 0x8128
1789 #define AR5K_PHYERR_CNT1 0x812c
1790 #define AR5K_PHYERR_CNT1_MASK 0x8130
1792 #define AR5K_PHYERR_CNT2 0x8134
1793 #define AR5K_PHYERR_CNT2_MASK 0x8138
1796 #define ATH5K_PHYERR_CNT_MAX 0x00c00000
1801 #define AR5K_TSF_THRES 0x813c
1805 * Range: 0x8147 - 0x818c
1811 #define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */
1813 #define AR5K_RATE_ACKSIFS_NORMAL 0x00000001 /* Normal SIFS (field) */
1814 #define AR5K_RATE_ACKSIFS_TURBO 0x00000400 /* Turbo SIFS (field) */
1819 #define AR5K_RATE_DUR_BASE 0x8700
1826 #define AR5K_RATE2DB_BASE 0x87c0
1833 #define AR5K_DB2RATE_BASE 0x87e0
1846 #define AR5K_PHY_BASE 0x9800
1852 #define AR5K_PHY_TST2 0x9800 /* Register Address */
1853 #define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/
1854 #define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */
1855 #define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */
1856 #define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32kHz external) */
1857 #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */
1858 #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */
1859 #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */
1860 #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */
1861 #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */
1862 #define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */
1863 #define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */
1864 #define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 /* AGC OBS Select 3 (?) */
1865 #define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 /* BB OBS Select (field ?) */
1866 #define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 /* ADC OBS Select (field ?) */
1867 #define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000 /* RX Clear Select (?) */
1868 #define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 /* Force AGC clear (?) */
1869 #define AR5K_PHY_SHIFT_2GHZ 0x00004007 /* Used to access 2GHz radios */
1870 #define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* Used to access 5GHz radios (default) */
1876 * at address 0x9944 (see below) but the 2 first flags
1882 #define AR5K_PHY_TURBO 0x9804 /* Register Address */
1883 #define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */
1884 #define AR5K_PHY_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode */
1885 #define AR5K_PHY_TURBO_MIMO 0x00000004 /* Set turbo for mimo */
1891 #define AR5K_PHY_AGC 0x9808 /* Register Address */
1892 #define AR5K_PHY_TST1 0x9808
1893 #define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/
1894 #define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */
1895 #define AR5K_PHY_TST1_TXSRC_SRC 0x00000002 /* Used with bit 7 (?) */
1897 #define AR5K_PHY_TST1_TXSRC_ALT 0x00000080 /* Set input to tsdac (?) */
1904 #define AR5K_PHY_TIMING_3 0x9814
1905 #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000
1907 #define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000
1913 #define AR5K_PHY_CHIP_ID 0x9818
1918 #define AR5K_PHY_ACT 0x981c /* Register Address */
1919 #define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */
1920 #define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */
1925 #define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */
1926 #define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */
1927 #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
1929 #define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */
1930 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */
1933 #define AR5K_PHY_ADC_CTL 0x982c
1934 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
1935 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0
1936 #define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000
1937 #define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000
1938 #define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000
1939 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000
1942 #define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */
1943 #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */
1944 #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */
1945 #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */
1946 #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */
1952 #define AR5K_PHY_PA_CTL 0x9838 /* Register Address */
1953 #define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 /* XPA A high (?) */
1954 #define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 /* XPA B high (?) */
1955 #define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */
1956 #define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */
1961 #define AR5K_PHY_SETTLING 0x9844 /* Register Address */
1962 #define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */
1963 #define AR5K_PHY_SETTLING_AGC_S 0
1964 #define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settling time */
1970 #define AR5K_PHY_GAIN 0x9848 /* Register Address */
1971 #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */
1973 #define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000
1976 #define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */
1977 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */
1983 #define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */
1984 #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* ADC desired size */
1985 #define AR5K_PHY_DESIRED_SIZE_ADC_S 0
1986 #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* PGA desired size */
1988 #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Total desired size */
1995 #define AR5K_PHY_SIG 0x9858 /* Register Address */
1996 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* FIRSTEP */
1998 #define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* FIPWR */
2005 #define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */
2006 #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* AGC Coarse low */
2008 #define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* AGC Coarse high */
2014 #define AR5K_PHY_AGCCTL 0x9860 /* Register address */
2015 #define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */
2016 #define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */
2017 #define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008 /* Disable antenna diversity on OFDM modes */
2018 #define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */
2019 #define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000 /* Allow filter calibration (?) */
2020 #define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automatically */
2025 #define AR5K_PHY_NF 0x9864 /* Register address */
2026 #define AR5K_PHY_NF_M 0x000001ff /* Noise floor, written to hardware in 1/2 dBm units */
2028 #define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */
2030 #define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000 /* Minimum measured noise level, read from hardware in 1…
2036 #define AR5K_PHY_ADCSAT 0x9868
2037 #define AR5K_PHY_ADCSAT_ICNT 0x0001f800
2039 #define AR5K_PHY_ADCSAT_THR 0x000007e0
2047 #define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868
2048 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f
2049 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0
2050 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000
2052 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000
2056 #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c
2057 #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001
2058 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00
2060 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000
2062 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000
2069 #define AR5K_PHY_SCR 0x9870
2071 #define AR5K_PHY_SLMT 0x9874
2072 #define AR5K_PHY_SLMT_32MHZ 0x0000007f
2074 #define AR5K_PHY_SCAL 0x9878
2075 #define AR5K_PHY_SCAL_32MHZ 0x0000000e
2076 #define AR5K_PHY_SCAL_32MHZ_5311 0x00000008
2077 #define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a
2078 #define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032
2083 #define AR5K_PHY_PLL 0x987c
2084 #define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */
2086 #define AR5K_PHY_PLL_40MHZ_5211 0x00000018
2087 #define AR5K_PHY_PLL_40MHZ_5212 0x000000aa
2088 #define AR5K_PHY_PLL_40MHZ_5413 0x00000004
2092 #define AR5K_PHY_PLL_44MHZ_5211 0x00000019
2093 #define AR5K_PHY_PLL_44MHZ_5212 0x000000ab
2097 #define AR5K_PHY_PLL_RF5111 0x00000000
2098 #define AR5K_PHY_PLL_RF5112 0x00000040
2099 #define AR5K_PHY_PLL_HALF_RATE 0x00000100
2100 #define AR5K_PHY_PLL_QUARTER_RATE 0x00000200
2105 * It's obvious from the code that 0x989c is the buffer register but
2111 #define AR5K_RF_BUFFER 0x989c
2112 #define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */
2113 #define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */
2114 #define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */
2116 #define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 */
2120 #define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 */
2121 /* Bank 0,1,2,6 on 5111 */
2125 #define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 */
2130 #define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */
2135 #define AR5K_PHY_RFSTG 0x98d4
2136 #define AR5K_PHY_RFSTG_DISABLE 0x00000021
2141 #define AR5K_PHY_BIN_MASK_1 0x9900
2142 #define AR5K_PHY_BIN_MASK_2 0x9904
2143 #define AR5K_PHY_BIN_MASK_3 0x9908
2145 #define AR5K_PHY_BIN_MASK_CTL 0x990c
2146 #define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff
2147 #define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0
2148 #define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000
2154 #define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */
2155 #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */
2156 #define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */
2157 #define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */
2158 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */
2164 #define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */
2165 #define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */
2170 #define AR5K_PHY_MAX_RX_LEN 0x991c
2176 #define AR5K_PHY_IQ 0x9920 /* Register Address */
2177 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */
2178 #define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 0
2179 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */
2181 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */
2182 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */
2184 #define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */
2185 #define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */
2186 #define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */
2187 #define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */
2188 #define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */
2189 #define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */
2190 #define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */
2197 #define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */
2198 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */
2199 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */
2201 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */
2202 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */
2203 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */
2204 #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000 /* Long sc threshold hi rssi (?) */
2209 #define AR5K_PHY_WARM_RESET 0x9928
2214 #define AR5K_PHY_CTL 0x992c /* Register Address */
2215 #define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 /* RX drain rate (?) */
2216 #define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */
2217 #define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 /* Generate scrambler */
2218 #define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */
2219 #define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */
2220 #define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020 /* RX antenna select */
2221 #define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 /* Static RX antenna */
2222 #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */
2227 #define AR5K_PHY_PAPD_PROBE 0x9930
2228 #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
2229 #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002
2230 #define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040
2231 #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00
2233 #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000
2234 #define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000
2235 #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */
2237 #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0
2240 #define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000
2242 #define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */
2243 #define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */
2248 #define AR5K_PHY_TXPOWER_RATE1 0x9934
2249 #define AR5K_PHY_TXPOWER_RATE2 0x9938
2250 #define AR5K_PHY_TXPOWER_RATE_MAX 0x993c
2251 #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040
2252 #define AR5K_PHY_TXPOWER_RATE3 0xa234
2253 #define AR5K_PHY_TXPOWER_RATE4 0xa238
2258 #define AR5K_PHY_FRAME_CTL_5210 0x9804
2259 #define AR5K_PHY_FRAME_CTL_5211 0x9944
2263 #define AR5K_PHY_FRAME_CTL_WIN_LEN 0x00000003 /* Force window length (?) */
2264 #define AR5K_PHY_FRAME_CTL_WIN_LEN_S 0
2265 #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */
2267 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */
2268 #define AR5K_PHY_FRAME_CTL_EMU 0x80000000
2271 #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */
2272 #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */
2273 #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* Illegal rate */
2274 #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */
2275 #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000
2276 #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */
2288 #define AR5K_PHY_TX_PWR_ADJ 0x994c
2289 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0
2291 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000
2297 #define AR5K_PHY_RADAR 0x9954
2298 #define AR5K_PHY_RADAR_ENABLE 0x00000001
2299 #define AR5K_PHY_RADAR_DISABLE 0x00000000
2300 #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold
2301 5-bits, units unknown {0..31}
2305 #define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold
2306 6-bits, dBm range {0..63}
2310 #define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold
2311 6-bits, dBm range {0..63}
2315 #define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold.
2316 6-bits, dBm range {0..63}
2320 #define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 /* Finite Impulse Response
2323 {0..127} in 1/2 dBm units. */
2329 #define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960
2330 #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
2335 #define AR5K_PHY_NFTHRES 0x9968
2340 #define AR5K_PHY_SIGMA_DELTA 0x996C
2341 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
2342 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0
2343 #define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8
2345 #define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
2347 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
2353 #define AR5K_PHY_RESTART 0x9970 /* restart */
2354 #define AR5K_PHY_RESTART_DIV_GC 0x001c0000 /* Fast diversity gc_limit (?) */
2360 #define AR5K_PHY_RFBUS_REQ 0x997C
2361 #define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001
2366 #define AR5K_PHY_TIMING_7 0x9980
2367 #define AR5K_PHY_TIMING_8 0x9984
2368 #define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff
2369 #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0
2371 #define AR5K_PHY_BIN_MASK2_1 0x9988
2372 #define AR5K_PHY_BIN_MASK2_2 0x998c
2373 #define AR5K_PHY_BIN_MASK2_3 0x9990
2375 #define AR5K_PHY_BIN_MASK2_4 0x9994
2376 #define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
2377 #define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
2379 #define AR5K_PHY_TIMING_9 0x9998
2380 #define AR5K_PHY_TIMING_10 0x999c
2381 #define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
2382 #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
2387 #define AR5K_PHY_TIMING_11 0x99a0 /* Register address */
2388 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
2389 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
2390 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
2392 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
2393 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
2398 #define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */
2400 #define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplifier Gain table base address */
2406 #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */
2407 #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */
2408 #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */
2413 #define AR5K_PHY_CURRENT_RSSI 0x9c1c
2418 #define AR5K_PHY_RFBUS_GRANT 0x9c20
2419 #define AR5K_PHY_RFBUS_GRANT_OK 0x00000001
2424 #define AR5K_PHY_ADC_TEST 0x9c24
2425 #define AR5K_PHY_ADC_TEST_I 0x00000001
2426 #define AR5K_PHY_ADC_TEST_Q 0x00000200
2431 #define AR5K_PHY_DAC_TEST 0x9c28
2432 #define AR5K_PHY_DAC_TEST_I 0x00000001
2433 #define AR5K_PHY_DAC_TEST_Q 0x00000200
2438 #define AR5K_PHY_PTAT 0x9c2c
2443 #define AR5K_PHY_BAD_TX_RATE 0x9c30
2448 #define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */
2449 #define AR5K_PHY_SPUR_PWR_I 0x00000001 /* SPUR Power estimate for I (field) */
2450 #define AR5K_PHY_SPUR_PWR_Q 0x00000100 /* SPUR Power estimate for Q (field) */
2451 #define AR5K_PHY_SPUR_PWR_FILT 0x00010000 /* Power with SPUR removed (field) */
2456 #define AR5K_PHY_CHAN_STATUS 0x9c38
2457 #define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001
2458 #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002
2459 #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004
2460 #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
2465 #define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0
2470 #define AR5K_PHY_SCLOCK 0x99f0
2471 #define AR5K_PHY_SCLOCK_32MHZ 0x0000000c
2472 #define AR5K_PHY_SDELAY 0x99f4
2473 #define AR5K_PHY_SDELAY_32MHZ 0x000000ff
2474 #define AR5K_PHY_SPENDING 0x99f8
2481 #define AR5K_PHY_PAPD_I_BASE 0xa000
2487 #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
2493 #define AR5K_PHY_MODE 0x0a200 /* Register Address */
2494 #define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */
2495 #define AR5K_PHY_MODE_MOD_OFDM 0
2497 #define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */
2498 #define AR5K_PHY_MODE_FREQ_5GHZ 0
2500 #define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */
2501 #define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */
2502 #define AR5K_PHY_MODE_RAD_RF5111 0
2504 #define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */
2505 #define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */
2506 #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */
2511 #define AR5K_PHY_CCKTXCTL 0xa204
2512 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000
2513 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010
2514 #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001
2515 #define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004
2520 #define AR5K_PHY_CCK_CROSSCORR 0xa208
2521 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000003f
2522 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0
2525 #define AR5K_PHY_FAST_ANT_DIV 0xa208
2526 #define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000
2531 #define AR5K_PHY_GAIN_2GHZ 0xa20c
2532 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
2534 #define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c
2536 #define AR5K_PHY_CCK_RX_CTL_4 0xa21c
2537 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000
2540 #define AR5K_PHY_DAG_CCK_CTL 0xa228
2541 #define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200
2542 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00
2545 #define AR5K_PHY_FAST_ADC 0xa24c
2547 #define AR5K_PHY_BLUETOOTH 0xa254
2553 #define AR5K_PHY_TPC_RG1 0xa258
2554 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000
2556 #define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000
2558 #define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000
2560 #define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000
2563 #define AR5K_PHY_TPC_RG5 0xa26C
2564 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F
2565 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0
2566 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0
2568 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00
2570 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000
2572 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
2578 #define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
2584 #define AR5K_AR5312_RESET 0xbc003020
2585 #define AR5K_AR5312_RESET_BB0_COLD 0x00000004
2586 #define AR5K_AR5312_RESET_BB1_COLD 0x00000200
2587 #define AR5K_AR5312_RESET_WMAC0 0x00002000
2588 #define AR5K_AR5312_RESET_BB0_WARM 0x00004000
2589 #define AR5K_AR5312_RESET_WMAC1 0x00020000
2590 #define AR5K_AR5312_RESET_BB1_WARM 0x00040000
2592 #define AR5K_AR5312_ENABLE 0xbc003080
2593 #define AR5K_AR5312_ENABLE_WLAN0 0x00000001
2594 #define AR5K_AR5312_ENABLE_WLAN1 0x00000008
2596 #define AR5K_AR2315_RESET 0xb1000004
2597 #define AR5K_AR2315_RESET_WMAC 0x00000001
2598 #define AR5K_AR2315_RESET_BB_WARM 0x00000002
2600 #define AR5K_AR2315_AHB_ARB_CTL 0xb1000008
2601 #define AR5K_AR2315_AHB_ARB_CTL_WLAN 0x00000002
2603 #define AR5K_AR2315_BYTESWAP 0xb100000c
2604 #define AR5K_AR2315_BYTESWAP_WMAC 0x00000002