Lines Matching +full:0 +full:x6800
41 #define CODING_BITS(i) (i & 0x0e000000)
42 #define COND_BITS(i) (i & 0xf0000000)
50 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
59 #define REGMASK_BITS(i) (i & 0xffff)
60 #define OFFSET_BITS(i) (i & 0x0fff)
62 #define IS_SHIFT(i) (i & 0x0ff0)
63 #define SHIFT_BITS(i) ((i >> 7) & 0x1f)
64 #define SHIFT_TYPE(i) (i & 0x60)
65 #define SHIFT_LSL 0x00
66 #define SHIFT_LSR 0x20
67 #define SHIFT_ASR 0x40
68 #define SHIFT_RORRRX 0x60
70 #define BAD_INSTR 0xdeadc0de
74 (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
89 #define UM_WARN (1 << 0)
143 return 0; in alignment_proc_show()
156 if (count > 0) { in alignment_proc_write()
159 if (mode >= '0' && mode <= '5') in alignment_proc_write()
160 ai_usermode = safe_usermode(mode - '0', true); in alignment_proc_write()
179 #define TYPE_ERROR 0
190 #define BE 0
204 "3: mov %0, #1\n" \
212 : "0" (err), "2" (addr))
216 unsigned int err = 0, v, a = addr; \
218 val = v << ((BE) ? 8 : 0); \
220 val |= v << ((BE) ? 0 : 8); \
223 } while (0)
233 unsigned int err = 0, v, a = addr; \
235 val = v << ((BE) ? 24 : 0); \
241 val |= v << ((BE) ? 0 : 24); \
244 } while (0)
254 unsigned int err = 0, v = val, a = addr; \
264 "4: mov %0, #1\n" \
273 : "0" (err), "1" (v), "2" (a)); \
276 } while (0)
286 unsigned int err = 0, v = val, a = addr; \
304 "6: mov %0, #1\n" \
315 : "0" (err), "1" (v), "2" (a)); \
318 } while (0)
354 if (instr & 0x40) in do_alignment_ldrhstrh()
372 if (instr & 0x40) in do_alignment_ldrhstrh()
395 if ((instr & 0xfe000000) == 0xe8000000) { in do_alignment_ldrdstrd()
397 rd2 = (instr >> 8) & 0xf; in do_alignment_ldrdstrd()
402 load = ((instr & 0xf0) == 0xd0); in do_alignment_ldrdstrd()
550 for (regbits = REGMASK_BITS(instr), rd = 0; regbits; in do_alignment_ldmstm()
563 for (regbits = REGMASK_BITS(instr), rd = 0; regbits; in do_alignment_ldmstm()
602 * decode, we return 0xdeadc0de. This should never happen under normal
612 switch ((tinstr & 0xf800) >> 11) { in thumb2arm()
614 case 0x6000 >> 11: /* 7.1.52 STR(1) */ in thumb2arm()
615 case 0x6800 >> 11: /* 7.1.26 LDR(1) */ in thumb2arm()
616 case 0x7000 >> 11: /* 7.1.55 STRB(1) */ in thumb2arm()
617 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */ in thumb2arm()
618 return 0xe5800000 | in thumb2arm()
621 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ in thumb2arm()
624 (6 - ((tinstr & (1<<12)) ? 0 : 2))); in thumb2arm()
625 case 0x8000 >> 11: /* 7.1.57 STRH(1) */ in thumb2arm()
626 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */ in thumb2arm()
627 return 0xe1c000b0 | in thumb2arm()
629 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ in thumb2arm()
631 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */ in thumb2arm()
635 case 0x5000 >> 11: in thumb2arm()
636 case 0x5800 >> 11: in thumb2arm()
639 0xe7800000, /* 7.1.53 STR(2) */ in thumb2arm()
640 0xe18000b0, /* 7.1.58 STRH(2) */ in thumb2arm()
641 0xe7c00000, /* 7.1.56 STRB(2) */ in thumb2arm()
642 0xe19000d0, /* 7.1.34 LDRSB */ in thumb2arm()
643 0xe7900000, /* 7.1.27 LDR(2) */ in thumb2arm()
644 0xe19000b0, /* 7.1.33 LDRH(2) */ in thumb2arm()
645 0xe7d00000, /* 7.1.31 LDRB(2) */ in thumb2arm()
646 0xe19000f0 /* 7.1.35 LDRSH */ in thumb2arm()
649 ((tinstr & (7<<0)) << (12-0)) | /* Rd */ in thumb2arm()
651 ((tinstr & (7<<6)) >> (6-0)); /* Rm */ in thumb2arm()
655 case 0x4800 >> 11: /* 7.1.28 LDR(3) */ in thumb2arm()
661 return 0xe59f0000 | in thumb2arm()
663 ((tinstr & 255) << (2-0)); /* immed_8 */ in thumb2arm()
666 case 0x9000 >> 11: /* 7.1.54 STR(3) */ in thumb2arm()
667 case 0x9800 >> 11: /* 7.1.29 LDR(4) */ in thumb2arm()
668 return 0xe58d0000 | in thumb2arm()
674 case 0xc000 >> 11: /* 7.1.51 STMIA */ in thumb2arm()
675 case 0xc800 >> 11: /* 7.1.25 LDMIA */ in thumb2arm()
678 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21; in thumb2arm()
680 return 0xe8800000 | W | (L<<20) | (Rn<<16) | in thumb2arm()
685 case 0xb000 >> 11: /* 7.1.48 PUSH */ in thumb2arm()
686 case 0xb800 >> 11: /* 7.1.47 POP */ in thumb2arm()
687 if ((tinstr & (3 << 9)) == 0x0400) { in thumb2arm()
689 0xe92d0000, /* STMDB sp!,{registers} */ in thumb2arm()
690 0xe92d4000, /* STMDB sp!,{registers,lr} */ in thumb2arm()
691 0xe8bd0000, /* LDMIA sp!,{registers} */ in thumb2arm()
692 0xe8bd8000 /* LDMIA sp!,{registers,pc} */ in thumb2arm()
722 u16 tinst1 = (instr >> 16) & 0xffff; in do_alignment_t32_to_handler()
723 u16 tinst2 = instr & 0xffff; in do_alignment_t32_to_handler()
725 switch (tinst1 & 0xffe0) { in do_alignment_t32_to_handler()
727 case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */ in do_alignment_t32_to_handler()
728 case 0xe8a0: /* ...above writeback version */ in do_alignment_t32_to_handler()
729 case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */ in do_alignment_t32_to_handler()
730 case 0xe920: /* ...above writeback version */ in do_alignment_t32_to_handler()
734 case 0xf840: /* POP/PUSH T3 (single register) */ in do_alignment_t32_to_handler()
735 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) { in do_alignment_t32_to_handler()
738 0xe92d0000, /* STMDB sp!,{registers} */ in do_alignment_t32_to_handler()
739 0xe8bd0000, /* LDMIA sp!,{registers} */ in do_alignment_t32_to_handler()
748 case 0xe860: in do_alignment_t32_to_handler()
749 case 0xe960: in do_alignment_t32_to_handler()
750 case 0xe8e0: in do_alignment_t32_to_handler()
751 case 0xe9e0: in do_alignment_t32_to_handler()
752 poffset->un = (tinst2 & 0xff) << 2; in do_alignment_t32_to_handler()
755 case 0xe940: in do_alignment_t32_to_handler()
756 case 0xe9c0: in do_alignment_t32_to_handler()
771 u32 instr = 0; in alignment_get_arm()
786 u16 instr = 0; in alignment_get_thumb()
806 u32 instr = 0; in do_alignment()
807 u16 tinstr = 0; in do_alignment()
809 int thumb2_32b = 0; in do_alignment()
854 case 0x00000000: /* 3.13.4 load/store instruction extensions */ in do_alignment()
856 offset.un = (instr & 0xf00) >> 4 | (instr & 15); in do_alignment()
860 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */ in do_alignment()
861 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */ in do_alignment()
863 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */ in do_alignment()
864 (instr & 0x001000f0) == 0x000000f0) /* STRD */ in do_alignment()
866 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */ in do_alignment()
872 case 0x04000000: /* ldr or str immediate */ in do_alignment()
873 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */ in do_alignment()
879 case 0x06000000: /* ldr or str register */ in do_alignment()
899 if (shiftval == 0) { in do_alignment()
912 case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */ in do_alignment()
914 offset.un = 0; in do_alignment()
917 offset.un = 0; in do_alignment()
941 return 0; in do_alignment()
950 return 0; in do_alignment()
960 "%0*x at [<%08lx>]\n", in do_alignment()
970 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*x " in do_alignment()
971 "Address=0x%08lx FSR 0x%03x\n", current->comm, in do_alignment()
1000 return 0; in do_alignment()
1038 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section in alignment_init()
1049 return 0; in alignment_init()