Lines Matching +full:0 +full:x6800

15 #define ADE_CTRL			0x0004
16 #define FRM_END_START_OFST		0
18 #define AUTO_CLK_GATE_EN_OFST		0
19 #define AUTO_CLK_GATE_EN		BIT(0)
20 #define ADE_DISP_SRC_CFG		0x0018
21 #define ADE_CTRL1			0x008C
22 #define ADE_EN				0x0100
23 #define ADE_DISABLE			0
26 #define ADE_SOFT_RST_SEL(x)		(0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x)		(0x00AC + (x) * 0x4)
28 #define RDMA_OFST			0
34 #define RD_CH_CTRL(x)			(0x1004 + (x) * 0x80)
35 #define RD_CH_ADDR(x)			(0x1008 + (x) * 0x80)
36 #define RD_CH_SIZE(x)			(0x100C + (x) * 0x80)
37 #define RD_CH_STRIDE(x)			(0x1010 + (x) * 0x80)
38 #define RD_CH_SPACE(x)			(0x1014 + (x) * 0x80)
39 #define RD_CH_EN(x)			(0x1020 + (x) * 0x80)
41 #define ADE_OVLY1_TRANS_CFG		0x002C
42 #define ADE_OVLY_CTL			0x0098
43 #define ADE_OVLY_CH_XY0(x)		(0x2004 + (x) * 4)
44 #define ADE_OVLY_CH_XY1(x)		(0x2024 + (x) * 4)
45 #define ADE_OVLY_CH_CTL(x)		(0x204C + (x) * 4)
46 #define ADE_OVLY_OUTPUT_SIZE(x)		(0x2070 + (x) * 8)
48 #define ADE_OVLYX_CTL(x)		(0x209C + (x) * 4)
52 #define CH_ALP_MODE_OFST		0
59 #define ADE_CTRAN_DIS(x)		(0x5004 + (x) * 0x100)
61 #define CTRAN_BYPASS_OFF		0
62 #define ADE_CTRAN_IMAGE_SIZE(x)		(0x503C + (x) * 0x100)
64 #define ADE_CLIP_DISABLE(x)		(0x6800 + (x) * 0x100)
65 #define ADE_CLIP_SIZE0(x)		(0x6804 + (x) * 0x100)
66 #define ADE_CLIP_SIZE1(x)		(0x6808 + (x) * 0x100)
71 #define LDI_HRZ_CTRL0			0x7400
73 #define LDI_HRZ_CTRL1			0x7404
74 #define LDI_VRT_CTRL0			0x7408
76 #define LDI_VRT_CTRL1			0x740C
77 #define LDI_PLR_CTRL			0x7410
78 #define FLAG_NVSYNC			BIT(0)
82 #define LDI_DSP_SIZE			0x7414
84 #define LDI_INT_EN			0x741C
86 #define LDI_CTRL			0x7420
89 #define LDI_EN				BIT(0)
90 #define LDI_MSK_INT			0x7428
91 #define LDI_INT_CLR			0x742C
92 #define LDI_WORK_MODE			0x7430
93 #define LDI_HDMI_DSI_GT			0x7434
98 #define ADE0_QOSGENERATOR_MODE		0x010C
100 #define ADE0_QOSGENERATOR_EXTCONTROL	0x0118
101 #define SOCKET_QOS_EN			BIT(0)
102 #define ADE1_QOSGENERATOR_MODE		0x020C
103 #define ADE1_QOSGENERATOR_EXTCONTROL	0x0218
110 	REG_EFFECTIVE_IN_VSYNC = 0,
120 	ADE_RGB_565 = 0,
134 	ADE_CH1 = 0,	/* channel 1 for primary plane */
139 	ADE_SCL1 = 0,
146 	ADE_CTRAN1 = 0,
156 	ADE_OVLY1 = 0,
163 	ADE_ALP_GLOBAL = 0,
169 	ADE_ALP_MUL_COEFF_0 = 0,	/* alpha */
171 	ADE_ALP_MUL_COEFF_2,		/* 0 */
179 	DSI_PCLK_ON = 0,
184 	LDI_OUT_RGB_565 = 0,
190 	TEST_MODE = 0,
195 	DISP_SRC_NONE = 0,
206 	FIXED_MODE = 0,