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/linux/drivers/tty/serial/8250/
H A D8250_fourport.c16 SERIAL8250_FOURPORT(0x1a0, 9),
17 SERIAL8250_FOURPORT(0x1a8, 9),
18 SERIAL8250_FOURPORT(0x1b0, 9),
19 SERIAL8250_FOURPORT(0x1b8, 9),
20 SERIAL8250_FOURPORT(0x2a0, 5),
21 SERIAL8250_FOURPORT(0x2a8, 5),
22 SERIAL8250_FOURPORT(0x2b0, 5),
23 SERIAL8250_FOURPORT(0x2b8, 5),
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_5nm.h10 #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00
11 #define QSERDES_V5_5NM_TX_BIST_INVERT 0x04
12 #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08
13 #define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL 0x0c
14 #define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP 0x10
15 #define QSERDES_V5_5NM_TX_TX_DRV_LVL 0x14
16 #define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET 0x18
17 #define QSERDES_V5_5NM_TX_RESET_TSYNC_EN 0x1c
18 #define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN 0x20
19 #define QSERDES_V5_5NM_TX_LPB_EN 0x24
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml17 SIUL2_0 @ 0x4009c000
18 SIUL2_1 @ 0x44010000
41 - description: MSCR registers group 0 in SIUL2_0
44 - description: IMCR registers group 0 in SIUL2_0
54 '-grp[0-9]$':
97 reg = <0x4009c240 0x198>,
99 <0x44010400 0x2c>,
101 <0x44010480 0xbc>,
103 <0x4009ca40 0x150>,
105 <0x44010c1c 0x45c>,
[all …]
/linux/Documentation/staging/
H A Dstatic-keys.rst233 ffffffff81044294: e9 00 00 00 00 jmpq ffffffff81044299 <sys_getppid+0x9>
234 ffffffff81044299: 65 48 8b 04 25 c0 b6 mov %gs:0xb6c0,%rax
236 ffffffff810442a2: 48 8b 80 80 02 00 00 mov 0x280(%rax),%rax
237 ffffffff810442a9: 48 8b 80 b0 02 00 00 mov 0x2b0(%rax),%rax
238 ffffffff810442b0: 48 8b b8 e8 02 00 00 mov 0x2e8(%rax),%rdi
243 ffffffff810442c0: 48 c7 c7 e3 54 98 81 mov $0xffffffff819854e3,%rdi
246 ffffffff810442ce: eb c9 jmp ffffffff81044299 <sys_getppid+0x9>
251 …ffffffff810441f0: 8b 05 8a 52 d8 00 mov 0xd8528a(%rip),%eax # ffffffff81dc94…
255 ffffffff810441fc: 75 27 jne ffffffff81044225 <sys_getppid+0x35>
256 ffffffff810441fe: 65 48 8b 04 25 c0 b6 mov %gs:0xb6c0,%rax
[all …]
/linux/tools/perf/util/kvm-stat-arch/
H A Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.h10 #define GRF_SOC_CON0 0x150
13 #define DDC_SEGMENT_ADDR 0x30
15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
17 #define N_32K 0x1000
18 #define N_441K 0x1880
19 #define N_882K 0x3100
20 #define N_1764K 0x6200
21 #define N_48K 0x1800
22 #define N_96K 0x3000
23 #define N_192K 0x6000
[all …]
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx94/sys/
H A Dmetrics.json5 …_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_ma…
13 …_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_ma…
21 "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
29 "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
37 "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32",
45 "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32",
51 "BriefDescription": "bytes of a55 core 0 read from ddr",
53 "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
59 "BriefDescription": "bytes of a55 core 0 write to ddr",
61 "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi_regs.h9 #define GRL_INT_MASK 0x18
10 #define GRL_IFM_PORT 0x188
11 #define GRL_CH_SWAP 0x198
12 #define LR_SWAP BIT(0)
17 #define GRL_I2S_C_STA0 0x140
18 #define GRL_I2S_C_STA1 0x144
19 #define GRL_I2S_C_STA2 0x148
20 #define GRL_I2S_C_STA3 0x14C
21 #define GRL_I2S_C_STA4 0x150
22 #define GRL_I2S_UV 0x154
[all …]
/linux/drivers/regulator/
H A Dpbias-regulator.c66 .vmode = BIT(0),
67 .disable_val = 0,
117 .offset = 0x230,
121 .offset = 0x2b0,
125 .offset = 0x60,
129 .offset = 0x60,
133 .offset = 0xe00,
162 if (count < 0) in pbias_regulator_probe()
177 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in pbias_regulator_probe()
189 for (idx = 0; idx < PBIAS_NUM_REGS && count; idx++) { in pbias_regulator_probe()
[all …]
/linux/arch/m68k/ifpsp060/
H A Dfplsp.doc87 fmovm.x &0x01,-(%sp) # pass operand on stack
88 bsr.l _060FPLSP_TOP+0x1a8 # branch to fsin routine
89 add.l &0xc,%sp # clear operand from stack
100 bsr.l _060FPLSP_TOP+0x168 # branch to frem routine
101 addq.l &0x8,%sp # clear operands from stack
132 0x000: _060LSP__facoss_
133 0x008: _060LSP__facosd_
134 0x010: _060LSP__facosx_
135 0x018: _060LSP__fasins_
136 0x020: _060LSP__fasind_
[all …]
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dpipeline.json10 "EventCode": "0x1A0",
16 "EventCode": "0x1A1",
22 "EventCode": "0x1A2",
28 "EventCode": "0x1A3",
34 "EventCode": "0x1A4",
40 "EventCode": "0x1A5",
46 "EventCode": "0x1A6",
52 "EventCode": "0x1B4",
58 "EventCode": "0x1B5",
63 "PublicDescription": "This event counts valid cycles of L1D cache pipeline#0.",
[all …]
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_engine_regs.h18 #define RENDER_RING_BASE 0x02000
19 #define BSD_RING_BASE 0x1c0000
20 #define BSD2_RING_BASE 0x1c4000
21 #define BSD3_RING_BASE 0x1d0000
22 #define BSD4_RING_BASE 0x1d4000
23 #define XEHP_BSD5_RING_BASE 0x1e0000
24 #define XEHP_BSD6_RING_BASE 0x1e4000
25 #define XEHP_BSD7_RING_BASE 0x1f0000
26 #define XEHP_BSD8_RING_BASE 0x1f4000
27 #define VEBOX_RING_BASE 0x1c8000
[all …]
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra20.S23 #define EMC_CFG 0xc
24 #define EMC_ADR_CFG 0x10
25 #define EMC_NOP 0xdc
26 #define EMC_SELF_REF 0xe0
27 #define EMC_REQ_CTRL 0x2b0
28 #define EMC_EMC_STATUS 0x2b4
30 #define CLK_RESET_CCLK_BURST 0x20
31 #define CLK_RESET_CCLK_DIVIDER 0x24
32 #define CLK_RESET_SCLK_BURST 0x28
33 #define CLK_RESET_SCLK_DIVIDER 0x2c
[all …]
/linux/drivers/usb/serial/
H A Dsafe_serial.c35 * 0..N-2 data and optional padding
38 * bits 1-0 top two bits of 10 bit CRC
43 * + 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 | 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 +
85 module_param(safe, bool, 0);
88 module_param(padded, bool, 0);
91 #define CDC_DEVICE_CLASS 0x02
93 #define CDC_INTERFACE_CLASS 0x02
94 #define CDC_INTERFACE_SUBCLASS 0x06
96 #define LINEO_INTERFACE_CLASS 0xff
98 #define LINEO_INTERFACE_SUBCLASS_SAFENET 0x01
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dfec_mpc52xx.h34 u32 fec_id; /* FEC + 0x000 */
35 u32 ievent; /* FEC + 0x004 */
36 u32 imask; /* FEC + 0x008 */
38 u32 reserved0[1]; /* FEC + 0x00C */
39 u32 r_des_active; /* FEC + 0x010 */
40 u32 x_des_active; /* FEC + 0x014 */
41 u32 r_des_active_cl; /* FEC + 0x018 */
42 u32 x_des_active_cl; /* FEC + 0x01C */
43 u32 ivent_set; /* FEC + 0x020 */
44 u32 ecntrl; /* FEC + 0x024 */
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_mips.h12 #define ROGUE_MIPSFW_PAGE_SIZE_4K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
15 #define ROGUE_MIPSFW_PAGE_SIZE_64K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_64K)
18 #define ROGUE_MIPSFW_PAGE_SIZE_256K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_256K)
21 #define ROGUE_MIPSFW_PAGE_SIZE_1MB (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_1MB)
24 #define ROGUE_MIPSFW_PAGE_SIZE_4MB (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4MB)
54 #define ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_CLRMSK (0X7FFFFFFF)
55 #define ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000)
58 #define ROGUE_MIPSFW_ENTRYLO_EXEC_INHIBIT_CLRMSK (0XBFFFFFFF)
59 #define ROGUE_MIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000)
65 #define ROGUE_MIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0)
[all …]

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