/linux/Documentation/devicetree/bindings/gpio/ |
H A D | qcom,wcd934x-gpio.yaml | 42 reg = <0x042 0x2>;
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/linux/sound/soc/codecs/ |
H A D | wcd9335.h | 8 * In slimbus mode the reg base starts from 0x800. 9 * In i2s/i2c mode the reg base is 0x0. 12 #define WCD9335_REG_OFFSET(r) (r & 0xFF) 13 #define WCD9335_PAGE_OFFSET(r) ((r >> 8) & 0xFF) 15 /* Page-0 Registers */ 16 #define WCD9335_PAGE0_PAGE_REGISTER WCD9335_REG(0x00, 0x000) 17 #define WCD9335_CODEC_RPM_CLK_GATE WCD9335_REG(0x00, 0x002) 18 #define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK GENMASK(1, 0) 19 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG WCD9335_REG(0x00, 0x003) 20 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0) [all …]
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/linux/drivers/net/wireless/mediatek/mt76/mt7603/ |
H A D | eeprom.h | 9 MT_EE_CHIP_ID = 0x000, 10 MT_EE_VERSION = 0x002, 11 MT_EE_MAC_ADDR = 0x004, 12 MT_EE_NIC_CONF_0 = 0x034, 13 MT_EE_NIC_CONF_1 = 0x036, 14 MT_EE_NIC_CONF_2 = 0x042, 16 MT_EE_XTAL_TRIM_1 = 0x03a, 18 MT_EE_RSSI_OFFSET_2G = 0x046, 19 MT_EE_WIFI_RF_SETTING = 0x048, 20 MT_EE_RSSI_OFFSET_5G = 0x04a, [all …]
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/linux/Documentation/admin-guide/perf/ |
H A D | qcom_l2_pmu.rst | 22 Events are specified as 0xCCG, where CC is 2 hex digits specifying 23 the code (array row) and G specifies the group (column) 0-7. 25 In addition there is a cycle counter event specified by the value 0xFE 34 perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1 36 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1
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/linux/drivers/net/wireless/mediatek/mt76/ |
H A D | mt76x02_eeprom.h | 13 MT_EE_CHIP_ID = 0x000, 14 MT_EE_VERSION = 0x002, 15 MT_EE_MAC_ADDR = 0x004, 16 MT_EE_PCI_ID = 0x00A, 17 MT_EE_ANTENNA = 0x022, 18 MT_EE_CFG1_INIT = 0x024, 19 MT_EE_NIC_CONF_0 = 0x034, 20 MT_EE_NIC_CONF_1 = 0x036, 21 MT_EE_COUNTRY_REGION_5GHZ = 0x038, 22 MT_EE_COUNTRY_REGION_2GHZ = 0x039, [all …]
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/linux/drivers/media/pci/zoran/ |
H A D | zr36060.h | 44 #define ZR060_LOAD 0x000 45 #define ZR060_CFSR 0x001 46 #define ZR060_CIR 0x002 47 #define ZR060_CMR 0x003 48 #define ZR060_MBZ 0x004 49 #define ZR060_MBCVR 0x005 50 #define ZR060_MER 0x006 51 #define ZR060_IMR 0x007 52 #define ZR060_ISR 0x008 53 #define ZR060_TCV_NET_HI 0x009 [all …]
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/linux/drivers/media/i2c/ |
H A D | saa717x.c | 36 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 76 #define TUNER_AUDIO_MONO 0 /* LL */ 90 int fw_addr = reg == 0x454 || (reg >= 0x464 && reg <= 0x478) || reg == 0x480 || reg == 0x488; in saa717x_write() 94 msg.flags = 0; in saa717x_write() 96 mm1[0] = (reg >> 8) & 0xff; in saa717x_write() 97 mm1[1] = reg & 0xff; in saa717x_write() 100 mm1[4] = (value >> 16) & 0xff; in saa717x_write() 101 mm1[3] = (value >> 8) & 0xff; in saa717x_write() 102 mm1[2] = value & 0xff; in saa717x_write() 104 mm1[2] = value & 0xff; in saa717x_write() [all …]
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap4-var-som-om44.dtsi | 15 reg = <0x80000000 0x40000000>; /* 1 GB */ 38 pinctrl-0 = < 45 #phy-cells = <0>; 64 pinctrl-0 = < 70 OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ 71 OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ 77 OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ 78 OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ 84 OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ 85 OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ [all …]
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/ |
H A D | table.c | 6 0x800, 0x80040000, 7 0x804, 0x00000003, 8 0x808, 0x0000FC00, 9 0x80C, 0x0000000A, 10 0x810, 0x10001331, 11 0x814, 0x020C3D10, 12 0x818, 0x02220385, 13 0x81C, 0x00000000, 14 0x820, 0x01000100, 15 0x824, 0x00390204, [all …]
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/linux/include/linux/mfd/da9062/ |
H A D | registers.h | 9 #define DA9062_PMIC_DEVICE_ID 0x62 10 #define DA9062_PMIC_VARIANT_MRC_AA 0x01 11 #define DA9062_PMIC_VARIANT_VRC_DA9061 0x01 12 #define DA9062_PMIC_VARIANT_VRC_DA9062 0x02 20 #define DA9062AA_PAGE_CON 0x000 21 #define DA9062AA_STATUS_A 0x001 22 #define DA9062AA_STATUS_B 0x002 23 #define DA9062AA_STATUS_D 0x004 24 #define DA9062AA_FAULT_LOG 0x005 25 #define DA9062AA_EVENT_A 0x006 [all …]
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/linux/drivers/net/ethernet/freescale/dpaa2/ |
H A D | dpsw-cmd.h | 25 #define DPSW_CMDID_CLOSE DPSW_CMD_ID(0x800) 26 #define DPSW_CMDID_OPEN DPSW_CMD_ID(0x802) 28 #define DPSW_CMDID_GET_API_VERSION DPSW_CMD_ID(0xa02) 30 #define DPSW_CMDID_ENABLE DPSW_CMD_ID(0x002) 31 #define DPSW_CMDID_DISABLE DPSW_CMD_ID(0x003) 32 #define DPSW_CMDID_GET_ATTR DPSW_CMD_V2(0x004) 33 #define DPSW_CMDID_RESET DPSW_CMD_ID(0x005) 35 #define DPSW_CMDID_SET_IRQ_ENABLE DPSW_CMD_ID(0x012) 37 #define DPSW_CMDID_SET_IRQ_MASK DPSW_CMD_ID(0x014) 39 #define DPSW_CMDID_GET_IRQ_STATUS DPSW_CMD_ID(0x016) [all …]
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/linux/drivers/net/wireless/broadcom/b43/ |
H A D | radio_2057.h | 9 #define R2057_DACBUF_VINCM_CORE0 0x000 10 #define R2057_IDCODE 0x001 11 #define R2057_RCCAL_MASTER 0x002 12 #define R2057_RCCAL_CAP_SIZE 0x003 13 #define R2057_RCAL_CONFIG 0x004 14 #define R2057_GPAIO_CONFIG 0x005 15 #define R2057_GPAIO_SEL1 0x006 16 #define R2057_GPAIO_SEL0 0x007 17 #define R2057_CLPO_CONFIG 0x008 18 #define R2057_BANDGAP_CONFIG 0x009 [all …]
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H A D | phy_lp.h | 9 #define B43_LPPHY_B_VERSION B43_PHY_CCK(0x00) /* B PHY version */ 10 #define B43_LPPHY_B_BBCONFIG B43_PHY_CCK(0x01) /* B PHY BBConfig */ 11 #define B43_LPPHY_B_RX_STAT0 B43_PHY_CCK(0x04) /* B PHY RX Status0 */ 12 #define B43_LPPHY_B_RX_STAT1 B43_PHY_CCK(0x05) /* B PHY RX Status1 */ 13 #define B43_LPPHY_B_CRS_THRESH B43_PHY_CCK(0x06) /* B PHY CRS Thresh */ 14 #define B43_LPPHY_B_TXERROR B43_PHY_CCK(0x07) /* B PHY TxError */ 15 #define B43_LPPHY_B_CHANNEL B43_PHY_CCK(0x08) /* B PHY Channel */ 16 #define B43_LPPHY_B_WORKAROUND B43_PHY_CCK(0x09) /* B PHY workaround */ 17 #define B43_LPPHY_B_TEST B43_PHY_CCK(0x0A) /* B PHY Test */ 18 #define B43_LPPHY_B_FOURWIRE_ADDR B43_PHY_CCK(0x0B) /* B PHY Fourwire Address */ [all …]
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H A D | phy_lcn.c | 66 b43_radio_set(dev, 0x09d, 0x4); in b43_radio_2064_channel_setup() 67 b43_radio_write(dev, 0x09e, 0xf); in b43_radio_2064_channel_setup() 70 b43_radio_write(dev, 0x02a, 0xb); in b43_radio_2064_channel_setup() 71 b43_radio_maskset(dev, 0x030, ~0x3, 0xa); in b43_radio_2064_channel_setup() 72 b43_radio_maskset(dev, 0x091, ~0x3, 0); in b43_radio_2064_channel_setup() 73 b43_radio_maskset(dev, 0x038, ~0xf, 0x7); in b43_radio_2064_channel_setup() 74 b43_radio_maskset(dev, 0x030, ~0xc, 0x8); in b43_radio_2064_channel_setup() 75 b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); in b43_radio_2064_channel_setup() 76 b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); in b43_radio_2064_channel_setup() 77 b43_radio_write(dev, 0x06c, 0x80); in b43_radio_2064_channel_setup() [all …]
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/linux/sound/drivers/opl4/ |
H A D | opl4_synth.c | 41 #define MIDI_CTL_RELEASE_TIME 0x48 42 #define MIDI_CTL_ATTACK_TIME 0x49 43 #define MIDI_CTL_DECAY_TIME 0x4b 44 #define MIDI_CTL_VIBRATO_RATE 0x4c 45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d 46 #define MIDI_CTL_VIBRATO_DELAY 0x4e 52 static const s16 snd_opl4_pitch_map[0x600] = { 53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003, 54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007, 55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b, [all …]
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/linux/include/linux/soundwire/ |
H A D | sdw_intel.h | 15 #define SDW_SHIM_BASE 0x2C000 16 #define SDW_ALH_BASE 0x2C800 17 #define SDW_SHIM_BASE_ACE 0x38000 18 #define SDW_ALH_BASE_ACE 0x24000 19 #define SDW_LINK_BASE 0x30000 20 #define SDW_LINK_SIZE 0x10000 24 #define SDW_SHIM_LCAP 0x0 25 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0) 29 #define SDW_SHIM_LCTL 0x4 31 #define SDW_SHIM_LCTL_SPA BIT(0) [all …]
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/ |
H A D | table.c | 6 0x800, 0x80040000, 7 0x804, 0x00000003, 8 0x808, 0x0000FC00, 9 0x80C, 0x0000000A, 10 0x810, 0x10001331, 11 0x814, 0x020C3D10, 12 0x818, 0x02200385, 13 0x81C, 0x00000000, 14 0x820, 0x01000100, 15 0x824, 0x00390204, [all …]
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/linux/tools/testing/selftests/tpm2/ |
H A D | tpm2.py | 12 TPM2_ST_NO_SESSIONS = 0x8001 13 TPM2_ST_SESSIONS = 0x8002 15 TPM2_CC_FIRST = 0x01FF 17 TPM2_CC_CREATE_PRIMARY = 0x0131 18 TPM2_CC_DICTIONARY_ATTACK_LOCK_RESET = 0x0139 19 TPM2_CC_CREATE = 0x0153 20 TPM2_CC_LOAD = 0x0157 21 TPM2_CC_UNSEAL = 0x015E 22 TPM2_CC_FLUSH_CONTEXT = 0x0165 23 TPM2_CC_START_AUTH_SESSION = 0x0176 [all …]
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/linux/sound/pci/ice1712/ |
H A D | maya44.c | 23 #define WM8776_REG_HEADPHONE_L 0x00 24 #define WM8776_REG_HEADPHONE_R 0x01 25 #define WM8776_REG_HEADPHONE_MASTER 0x02 26 #define WM8776_REG_DAC_ATTEN_L 0x03 27 #define WM8776_REG_DAC_ATTEN_R 0x04 28 #define WM8776_REG_DAC_ATTEN_MASTER 0x05 29 #define WM8776_REG_DAC_PHASE 0x06 30 #define WM8776_REG_DAC_CONTROL 0x07 31 #define WM8776_REG_DAC_MUTE 0x08 32 #define WM8776_REG_DAC_DEEMPH 0x09 [all …]
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/linux/drivers/gpu/drm/tegra/ |
H A D | dc.h | 176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 [all …]
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/linux/arch/sparc/math-emu/ |
H A D | math_64.c | 29 #define FMOVQ 0x003 30 #define FNEGQ 0x007 31 #define FABSQ 0x00b 32 #define FSQRTQ 0x02b 33 #define FADDQ 0x043 34 #define FSUBQ 0x047 35 #define FMULQ 0x04b 36 #define FDIVQ 0x04f 37 #define FDMULQ 0x06e 38 #define FQTOX 0x083 [all …]
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H A D | math_32.c | 86 #define FSQRTQ 0x02b /* v8 */ 87 #define FADDQ 0x043 /* v8 */ 88 #define FSUBQ 0x047 /* v8 */ 89 #define FMULQ 0x04b /* v8 */ 90 #define FDIVQ 0x04f /* v8 */ 91 #define FDMULQ 0x06e /* v8 */ 92 #define FQTOS 0x0c7 /* v8 */ 93 #define FQTOD 0x0cb /* v8 */ 94 #define FITOQ 0x0cc /* v8 */ 95 #define FSTOQ 0x0cd /* v8 */ [all …]
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/linux/include/linux/ |
H A D | psp-sev.h | 17 #define SEV_FW_BLOB_MAX_SIZE 0x4000 /* 16KB */ 23 SEV_STATE_UNINIT = 0x0, 24 SEV_STATE_INIT = 0x1, 25 SEV_STATE_WORKING = 0x2, 35 SEV_CMD_INIT = 0x001, 36 SEV_CMD_SHUTDOWN = 0x002, 37 SEV_CMD_FACTORY_RESET = 0x003, 38 SEV_CMD_PLATFORM_STATUS = 0x004, 39 SEV_CMD_PEK_GEN = 0x005, 40 SEV_CMD_PEK_CSR = 0x006, [all …]
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/linux/drivers/usb/serial/ |
H A D | io_usbvend.h | 28 #define USB_VENDOR_ID_ION 0x1608 // Our VID 29 #define USB_VENDOR_ID_TI 0x0451 // TI VID 30 #define USB_VENDOR_ID_AXIOHM 0x05D9 /* Axiohm VID */ 41 #define ION_OEM_ID_ION 0 // 00h Inside Out Networks 53 #define ION_DEVICE_ID_80251_NETCHIP 0x020 // This bit is set in the PID if this edgeport hardware$ 56 #define ION_DEVICE_ID_GENERATION_1 0x00 // Value for 930 based edgeports 57 #define ION_DEVICE_ID_GENERATION_2 0x01 // Value for 80251+Netchip. 58 #define ION_DEVICE_ID_GENERATION_3 0x02 // Value for Texas Instruments TUSB5052 chip 59 #define ION_DEVICE_ID_GENERATION_4 0x03 // Watchport Family of products 60 #define ION_GENERATION_MASK 0x03 [all …]
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/linux/drivers/net/wireless/realtek/rtw89/ |
H A D | rtw8852c_rfk_table.c | 8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1), 9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1), 10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1), 11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1), 17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0), 18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1), 24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0), 25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1), 31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1), 32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1), [all …]
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