86 #define FSQRTQ	0x02b		/* v8 */
87 #define FADDQ	0x043		/* v8 */
88 #define FSUBQ	0x047		/* v8 */
89 #define FMULQ	0x04b		/* v8 */
90 #define FDIVQ	0x04f		/* v8 */
91 #define FDMULQ	0x06e		/* v8 */
92 #define FQTOS	0x0c7		/* v8 */
93 #define FQTOD	0x0cb		/* v8 */
94 #define FITOQ	0x0cc		/* v8 */
95 #define FSTOQ	0x0cd		/* v8 */
96 #define FDTOQ	0x0ce		/* v8 */
97 #define FQTOI	0x0d3		/* v8 */
98 #define FCMPQ	0x053		/* v8 */
99 #define FCMPEQ	0x057		/* v8 */
101 #define FSQRTS	0x029		/* v7 */
102 #define FSQRTD	0x02a		/* v7 */
103 #define FADDS	0x041		/* v6 */
104 #define FADDD	0x042		/* v6 */
105 #define FSUBS	0x045		/* v6 */
106 #define FSUBD	0x046		/* v6 */
107 #define FMULS	0x049		/* v6 */
108 #define FMULD	0x04a		/* v6 */
109 #define FDIVS	0x04d		/* v6 */
110 #define FDIVD	0x04e		/* v6 */
111 #define FSMULD	0x069		/* v6 */
112 #define FDTOS	0x0c6		/* v6 */
113 #define FSTOD	0x0c9		/* v6 */
114 #define FSTOI	0x0d1		/* v6 */
115 #define FDTOI	0x0d2		/* v6 */
116 #define FABSS	0x009		/* v6 */
117 #define FCMPS	0x051		/* v6 */
118 #define FCMPES	0x055		/* v6 */
119 #define FCMPD	0x052		/* v6 */
120 #define FCMPED	0x056		/* v6 */
121 #define FMOVS	0x001		/* v6 */
122 #define FNEGS	0x005		/* v6 */
123 #define FITOS	0x0c4		/* v6 */
124 #define FITOD	0x0c8		/* v6 */
127 #define FSR_TEM_MASK	(0x1fUL << FSR_TEM_SHIFT)
129 #define FSR_AEXC_MASK	(0x1fUL << FSR_AEXC_SHIFT)
130 #define FSR_CEXC_SHIFT	0UL
131 #define FSR_CEXC_MASK	(0x1fUL << FSR_CEXC_SHIFT)
165 	int retcode = 0;                               /* assume all succeed */  in do_mathemu()
168 	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);  in do_mathemu()
173 	for (i = 0; i < fpt->thread.fpqdepth; i++)  in do_mathemu()
178 	if (fpt->thread.fpqdepth == 0) {                   /* no queue, guilty insn is at regs->pc */  in do_mathemu()
194 	for (i = 0; i < fpt->thread.fpqdepth; i++) {  in do_mathemu()
201 		fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK);  in do_mathemu()
203 		fpt->thread.fsr &= ~0x3000;  in do_mathemu()
204 	fpt->thread.fpqdepth = 0;  in do_mathemu()
215  * We return 0 if a SIGFPE should be sent, 1 otherwise.
223 	would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;  in record_exception()
226 	if (would_trap != 0) {  in record_exception()
228 		if ((eflag & (eflag - 1)) != 0) {  in record_exception()
257 	if (would_trap == 0)  in record_exception()
261 	if (would_trap != 0)  in record_exception()
266 	return (would_trap ? 0 : 1);  in record_exception()
278 	int type = 0;  in do_one_mathemu()
280 	   whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)  in do_one_mathemu()
281 	   non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */  in do_one_mathemu()
282 #define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru <…  in do_one_mathemu()
296 	if ((insn & 0xc1f80000) == 0x81a00000)	/* FPOP1 */ {  in do_one_mathemu()
297 		switch ((insn >> 5) & 0x1ff) {  in do_one_mathemu()
298 		case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;  in do_one_mathemu()
304 		case FQTOS: TYPE(3,1,1,3,1,0,0); break;  in do_one_mathemu()
305 		case FQTOD: TYPE(3,2,1,3,1,0,0); break;  in do_one_mathemu()
306 		case FITOQ: TYPE(3,3,1,1,0,0,0); break;  in do_one_mathemu()
307 		case FSTOQ: TYPE(3,3,1,1,1,0,0); break;  in do_one_mathemu()
308 		case FDTOQ: TYPE(3,3,1,2,1,0,0); break;  in do_one_mathemu()
309 		case FQTOI: TYPE(3,1,0,3,1,0,0); break;  in do_one_mathemu()
310 		case FSQRTS: TYPE(2,1,1,1,1,0,0); break;  in do_one_mathemu()
311 		case FSQRTD: TYPE(2,2,1,2,1,0,0); break;  in do_one_mathemu()
321 		case FDTOS: TYPE(2,1,1,2,1,0,0); break;  in do_one_mathemu()
322 		case FSTOD: TYPE(2,2,1,1,1,0,0); break;  in do_one_mathemu()
323 		case FSTOI: TYPE(2,1,0,1,1,0,0); break;  in do_one_mathemu()
324 		case FDTOI: TYPE(2,1,0,2,1,0,0); break;  in do_one_mathemu()
325 		case FITOS: TYPE(2,1,1,1,0,0,0); break;  in do_one_mathemu()
326 		case FITOD: TYPE(2,2,1,1,0,0,0); break;  in do_one_mathemu()
329 		case FNEGS: TYPE(2,1,0,1,0,0,0); break;  in do_one_mathemu()
331 	} else if ((insn & 0xc1f80000) == 0x81a80000)	/* FPOP2 */ {  in do_one_mathemu()
332 		switch ((insn >> 5) & 0x1ff) {  in do_one_mathemu()
333 		case FCMPS: TYPE(3,0,0,1,1,1,1); break;  in do_one_mathemu()
334 		case FCMPES: TYPE(3,0,0,1,1,1,1); break;  in do_one_mathemu()
335 		case FCMPD: TYPE(3,0,0,2,1,2,1); break;  in do_one_mathemu()
336 		case FCMPED: TYPE(3,0,0,2,1,2,1); break;  in do_one_mathemu()
337 		case FCMPQ: TYPE(3,0,0,3,1,3,1); break;  in do_one_mathemu()
338 		case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;  in do_one_mathemu()
346 		return 0;  in do_one_mathemu()
350 	freg = (*pfsr >> 14) & 0xf;  in do_one_mathemu()
352 	*pfsr &= ~0x1c000;				/* clear the traptype bits */  in do_one_mathemu()
354 	freg = ((insn >> 14) & 0x1f);  in do_one_mathemu()
355 	switch (type & 0x3) {				/* is rs1 single, double or quad? */  in do_one_mathemu()
360 			return 0;			/* simulate invalid_fp_register exception */  in do_one_mathemu()
366 			return 0;  in do_one_mathemu()
370 	switch (type & 0x7) {  in do_one_mathemu()
375 	freg = (insn & 0x1f);  in do_one_mathemu()
376 	switch ((type >> 3) & 0x3) {			/* same again for rs2 */  in do_one_mathemu()
381 			return 0;			/* simulate invalid_fp_register exception */  in do_one_mathemu()
387 			return 0;  in do_one_mathemu()
391 	switch ((type >> 3) & 0x7) {  in do_one_mathemu()
396 	freg = ((insn >> 25) & 0x1f);  in do_one_mathemu()
397 	switch ((type >> 6) & 0x3) {			/* and finally rd. This one's a bit different */  in do_one_mathemu()
398 	case 0:						/* dest is fcc. (this must be FCMPQ or FCMPEQ) */  in do_one_mathemu()
400 							/* anything but 0 in the rd field is an error */  in do_one_mathemu()
402 			return 0;			/* but SIGFPE will do :-> ) */  in do_one_mathemu()
409 			return 0;			/* simulate invalid_fp_register exception */  in do_one_mathemu()
415 			return 0;  in do_one_mathemu()
426 	switch ((insn >> 5) & 0x1ff) {  in do_one_mathemu()
453 	case FABSS: rd->s = rs2->s & 0x7fffffff; break;  in do_one_mathemu()
454 	case FNEGS: rd->s = rs2->s ^ 0x80000000; break;  in do_one_mathemu()
475 		    (((insn >> 5) & 0x1ff) == FCMPES ||  in do_one_mathemu()
484 		    (((insn >> 5) & 0x1ff) == FCMPED ||  in do_one_mathemu()
493 		    (((insn >> 5) & 0x1ff) == FCMPEQ ||  in do_one_mathemu()
499 		switch ((type >> 6) & 0x7) {  in do_one_mathemu()
500 		case 0: fsr = *pfsr;  in do_one_mathemu()
503 			fsr &= ~0xc00; fsr |= (IR << 10);  in do_one_mathemu()
512 	if (_fex == 0)  in do_one_mathemu()