1*b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
25115f39cSSam Ravnborg /*
35115f39cSSam Ravnborg * arch/sparc64/math-emu/math.c
45115f39cSSam Ravnborg *
55115f39cSSam Ravnborg * Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)
65115f39cSSam Ravnborg * Copyright (C) 1999 David S. Miller (davem@redhat.com)
75115f39cSSam Ravnborg *
85115f39cSSam Ravnborg * Emulation routines originate from soft-fp package, which is part
95115f39cSSam Ravnborg * of glibc and has appropriate copyrights in it.
105115f39cSSam Ravnborg */
115115f39cSSam Ravnborg
125115f39cSSam Ravnborg #include <linux/types.h>
135115f39cSSam Ravnborg #include <linux/sched.h>
145115f39cSSam Ravnborg #include <linux/errno.h>
15121dd5f2SDavid S. Miller #include <linux/perf_event.h>
165115f39cSSam Ravnborg
175115f39cSSam Ravnborg #include <asm/fpumacro.h>
185115f39cSSam Ravnborg #include <asm/ptrace.h>
197c0f6ba6SLinus Torvalds #include <linux/uaccess.h>
20d550bbd4SDavid Howells #include <asm/cacheflush.h>
215115f39cSSam Ravnborg
225115f39cSSam Ravnborg #include "sfp-util_64.h"
235115f39cSSam Ravnborg #include <math-emu/soft-fp.h>
245115f39cSSam Ravnborg #include <math-emu/single.h>
255115f39cSSam Ravnborg #include <math-emu/double.h>
265115f39cSSam Ravnborg #include <math-emu/quad.h>
275115f39cSSam Ravnborg
285115f39cSSam Ravnborg /* QUAD - ftt == 3 */
295115f39cSSam Ravnborg #define FMOVQ 0x003
305115f39cSSam Ravnborg #define FNEGQ 0x007
315115f39cSSam Ravnborg #define FABSQ 0x00b
325115f39cSSam Ravnborg #define FSQRTQ 0x02b
335115f39cSSam Ravnborg #define FADDQ 0x043
345115f39cSSam Ravnborg #define FSUBQ 0x047
355115f39cSSam Ravnborg #define FMULQ 0x04b
365115f39cSSam Ravnborg #define FDIVQ 0x04f
375115f39cSSam Ravnborg #define FDMULQ 0x06e
385115f39cSSam Ravnborg #define FQTOX 0x083
395115f39cSSam Ravnborg #define FXTOQ 0x08c
405115f39cSSam Ravnborg #define FQTOS 0x0c7
415115f39cSSam Ravnborg #define FQTOD 0x0cb
425115f39cSSam Ravnborg #define FITOQ 0x0cc
435115f39cSSam Ravnborg #define FSTOQ 0x0cd
445115f39cSSam Ravnborg #define FDTOQ 0x0ce
455115f39cSSam Ravnborg #define FQTOI 0x0d3
465115f39cSSam Ravnborg /* SUBNORMAL - ftt == 2 */
475115f39cSSam Ravnborg #define FSQRTS 0x029
485115f39cSSam Ravnborg #define FSQRTD 0x02a
495115f39cSSam Ravnborg #define FADDS 0x041
505115f39cSSam Ravnborg #define FADDD 0x042
515115f39cSSam Ravnborg #define FSUBS 0x045
525115f39cSSam Ravnborg #define FSUBD 0x046
535115f39cSSam Ravnborg #define FMULS 0x049
545115f39cSSam Ravnborg #define FMULD 0x04a
555115f39cSSam Ravnborg #define FDIVS 0x04d
565115f39cSSam Ravnborg #define FDIVD 0x04e
575115f39cSSam Ravnborg #define FSMULD 0x069
585115f39cSSam Ravnborg #define FSTOX 0x081
595115f39cSSam Ravnborg #define FDTOX 0x082
605115f39cSSam Ravnborg #define FDTOS 0x0c6
615115f39cSSam Ravnborg #define FSTOD 0x0c9
625115f39cSSam Ravnborg #define FSTOI 0x0d1
635115f39cSSam Ravnborg #define FDTOI 0x0d2
645115f39cSSam Ravnborg #define FXTOS 0x084 /* Only Ultra-III generates this. */
655115f39cSSam Ravnborg #define FXTOD 0x088 /* Only Ultra-III generates this. */
665115f39cSSam Ravnborg #if 0 /* Optimized inline in sparc64/kernel/entry.S */
675115f39cSSam Ravnborg #define FITOS 0x0c4 /* Only Ultra-III generates this. */
685115f39cSSam Ravnborg #endif
695115f39cSSam Ravnborg #define FITOD 0x0c8 /* Only Ultra-III generates this. */
705115f39cSSam Ravnborg /* FPOP2 */
715115f39cSSam Ravnborg #define FCMPQ 0x053
725115f39cSSam Ravnborg #define FCMPEQ 0x057
735115f39cSSam Ravnborg #define FMOVQ0 0x003
745115f39cSSam Ravnborg #define FMOVQ1 0x043
755115f39cSSam Ravnborg #define FMOVQ2 0x083
765115f39cSSam Ravnborg #define FMOVQ3 0x0c3
775115f39cSSam Ravnborg #define FMOVQI 0x103
785115f39cSSam Ravnborg #define FMOVQX 0x183
795115f39cSSam Ravnborg #define FMOVQZ 0x027
805115f39cSSam Ravnborg #define FMOVQLE 0x047
815115f39cSSam Ravnborg #define FMOVQLZ 0x067
825115f39cSSam Ravnborg #define FMOVQNZ 0x0a7
835115f39cSSam Ravnborg #define FMOVQGZ 0x0c7
845115f39cSSam Ravnborg #define FMOVQGE 0x0e7
855115f39cSSam Ravnborg
865115f39cSSam Ravnborg #define FSR_TEM_SHIFT 23UL
875115f39cSSam Ravnborg #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
885115f39cSSam Ravnborg #define FSR_AEXC_SHIFT 5UL
895115f39cSSam Ravnborg #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
905115f39cSSam Ravnborg #define FSR_CEXC_SHIFT 0UL
915115f39cSSam Ravnborg #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
925115f39cSSam Ravnborg
935115f39cSSam Ravnborg /* All routines returning an exception to raise should detect
945115f39cSSam Ravnborg * such exceptions _before_ rounding to be consistent with
955115f39cSSam Ravnborg * the behavior of the hardware in the implemented cases
965115f39cSSam Ravnborg * (and thus with the recommendations in the V9 architecture
975115f39cSSam Ravnborg * manual).
985115f39cSSam Ravnborg *
995115f39cSSam Ravnborg * We return 0 if a SIGFPE should be sent, 1 otherwise.
1005115f39cSSam Ravnborg */
record_exception(struct pt_regs * regs,int eflag)1015115f39cSSam Ravnborg static inline int record_exception(struct pt_regs *regs, int eflag)
1025115f39cSSam Ravnborg {
1035115f39cSSam Ravnborg u64 fsr = current_thread_info()->xfsr[0];
1045115f39cSSam Ravnborg int would_trap;
1055115f39cSSam Ravnborg
1065115f39cSSam Ravnborg /* Determine if this exception would have generated a trap. */
1075115f39cSSam Ravnborg would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
1085115f39cSSam Ravnborg
1095115f39cSSam Ravnborg /* If trapping, we only want to signal one bit. */
1105115f39cSSam Ravnborg if(would_trap != 0) {
1115115f39cSSam Ravnborg eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
1125115f39cSSam Ravnborg if((eflag & (eflag - 1)) != 0) {
1135115f39cSSam Ravnborg if(eflag & FP_EX_INVALID)
1145115f39cSSam Ravnborg eflag = FP_EX_INVALID;
1155115f39cSSam Ravnborg else if(eflag & FP_EX_OVERFLOW)
1165115f39cSSam Ravnborg eflag = FP_EX_OVERFLOW;
1175115f39cSSam Ravnborg else if(eflag & FP_EX_UNDERFLOW)
1185115f39cSSam Ravnborg eflag = FP_EX_UNDERFLOW;
1195115f39cSSam Ravnborg else if(eflag & FP_EX_DIVZERO)
1205115f39cSSam Ravnborg eflag = FP_EX_DIVZERO;
1215115f39cSSam Ravnborg else if(eflag & FP_EX_INEXACT)
1225115f39cSSam Ravnborg eflag = FP_EX_INEXACT;
1235115f39cSSam Ravnborg }
1245115f39cSSam Ravnborg }
1255115f39cSSam Ravnborg
1265115f39cSSam Ravnborg /* Set CEXC, here is the rule:
1275115f39cSSam Ravnborg *
1285115f39cSSam Ravnborg * In general all FPU ops will set one and only one
1295115f39cSSam Ravnborg * bit in the CEXC field, this is always the case
1305115f39cSSam Ravnborg * when the IEEE exception trap is enabled in TEM.
1315115f39cSSam Ravnborg */
1325115f39cSSam Ravnborg fsr &= ~(FSR_CEXC_MASK);
1335115f39cSSam Ravnborg fsr |= ((long)eflag << FSR_CEXC_SHIFT);
1345115f39cSSam Ravnborg
1355115f39cSSam Ravnborg /* Set the AEXC field, rule is:
1365115f39cSSam Ravnborg *
1375115f39cSSam Ravnborg * If a trap would not be generated, the
1385115f39cSSam Ravnborg * CEXC just generated is OR'd into the
1395115f39cSSam Ravnborg * existing value of AEXC.
1405115f39cSSam Ravnborg */
1415115f39cSSam Ravnborg if(would_trap == 0)
1425115f39cSSam Ravnborg fsr |= ((long)eflag << FSR_AEXC_SHIFT);
1435115f39cSSam Ravnborg
1445115f39cSSam Ravnborg /* If trapping, indicate fault trap type IEEE. */
1455115f39cSSam Ravnborg if(would_trap != 0)
1465115f39cSSam Ravnborg fsr |= (1UL << 14);
1475115f39cSSam Ravnborg
1485115f39cSSam Ravnborg current_thread_info()->xfsr[0] = fsr;
1495115f39cSSam Ravnborg
1505115f39cSSam Ravnborg /* If we will not trap, advance the program counter over
1515115f39cSSam Ravnborg * the instruction being handled.
1525115f39cSSam Ravnborg */
1535115f39cSSam Ravnborg if(would_trap == 0) {
1545115f39cSSam Ravnborg regs->tpc = regs->tnpc;
1555115f39cSSam Ravnborg regs->tnpc += 4;
1565115f39cSSam Ravnborg }
1575115f39cSSam Ravnborg
1585115f39cSSam Ravnborg return (would_trap ? 0 : 1);
1595115f39cSSam Ravnborg }
1605115f39cSSam Ravnborg
1615115f39cSSam Ravnborg typedef union {
1625115f39cSSam Ravnborg u32 s;
1635115f39cSSam Ravnborg u64 d;
1645115f39cSSam Ravnborg u64 q[2];
1655115f39cSSam Ravnborg } *argp;
1665115f39cSSam Ravnborg
do_mathemu(struct pt_regs * regs,struct fpustate * f,bool illegal_insn_trap)167456d3d42SDavid S. Miller int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap)
1685115f39cSSam Ravnborg {
1695115f39cSSam Ravnborg unsigned long pc = regs->tpc;
1705115f39cSSam Ravnborg unsigned long tstate = regs->tstate;
1715115f39cSSam Ravnborg u32 insn = 0;
1725115f39cSSam Ravnborg int type = 0;
1735115f39cSSam Ravnborg /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells
1745115f39cSSam Ravnborg whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
1755115f39cSSam Ravnborg non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
1765115f39cSSam Ravnborg #define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9)
1775115f39cSSam Ravnborg int freg;
1785115f39cSSam Ravnborg static u64 zero[2] = { 0L, 0L };
1795115f39cSSam Ravnborg int flags;
1805115f39cSSam Ravnborg FP_DECL_EX;
1815115f39cSSam Ravnborg FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
1825115f39cSSam Ravnborg FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
1835115f39cSSam Ravnborg FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
1845115f39cSSam Ravnborg int IR;
1855115f39cSSam Ravnborg long XR, xfsr;
1865115f39cSSam Ravnborg
1875115f39cSSam Ravnborg if (tstate & TSTATE_PRIV)
1885115f39cSSam Ravnborg die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
189a8b0ca17SPeter Zijlstra perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
1905115f39cSSam Ravnborg if (test_thread_flag(TIF_32BIT))
1915115f39cSSam Ravnborg pc = (u32)pc;
1925115f39cSSam Ravnborg if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
1935115f39cSSam Ravnborg if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
1945115f39cSSam Ravnborg switch ((insn >> 5) & 0x1ff) {
1955115f39cSSam Ravnborg /* QUAD - ftt == 3 */
1965115f39cSSam Ravnborg case FMOVQ:
1975115f39cSSam Ravnborg case FNEGQ:
1985115f39cSSam Ravnborg case FABSQ: TYPE(3,3,0,3,0,0,0); break;
1995115f39cSSam Ravnborg case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
2005115f39cSSam Ravnborg case FADDQ:
2015115f39cSSam Ravnborg case FSUBQ:
2025115f39cSSam Ravnborg case FMULQ:
2035115f39cSSam Ravnborg case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
2045115f39cSSam Ravnborg case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
2055115f39cSSam Ravnborg case FQTOX: TYPE(3,2,0,3,1,0,0); break;
2065115f39cSSam Ravnborg case FXTOQ: TYPE(3,3,1,2,0,0,0); break;
2075115f39cSSam Ravnborg case FQTOS: TYPE(3,1,1,3,1,0,0); break;
2085115f39cSSam Ravnborg case FQTOD: TYPE(3,2,1,3,1,0,0); break;
2095115f39cSSam Ravnborg case FITOQ: TYPE(3,3,1,1,0,0,0); break;
2105115f39cSSam Ravnborg case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
2115115f39cSSam Ravnborg case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
2125115f39cSSam Ravnborg case FQTOI: TYPE(3,1,0,3,1,0,0); break;
2135115f39cSSam Ravnborg
2145115f39cSSam Ravnborg /* We can get either unimplemented or unfinished
2155115f39cSSam Ravnborg * for these cases. Pre-Niagara systems generate
2165115f39cSSam Ravnborg * unfinished fpop for SUBNORMAL cases, and Niagara
2175115f39cSSam Ravnborg * always gives unimplemented fpop for fsqrt{s,d}.
2185115f39cSSam Ravnborg */
2195115f39cSSam Ravnborg case FSQRTS: {
2205115f39cSSam Ravnborg unsigned long x = current_thread_info()->xfsr[0];
2215115f39cSSam Ravnborg
222456d3d42SDavid S. Miller x = (x >> 14) & 0x7;
2235115f39cSSam Ravnborg TYPE(x,1,1,1,1,0,0);
2245115f39cSSam Ravnborg break;
2255115f39cSSam Ravnborg }
2265115f39cSSam Ravnborg
2275115f39cSSam Ravnborg case FSQRTD: {
2285115f39cSSam Ravnborg unsigned long x = current_thread_info()->xfsr[0];
2295115f39cSSam Ravnborg
230456d3d42SDavid S. Miller x = (x >> 14) & 0x7;
2315115f39cSSam Ravnborg TYPE(x,2,1,2,1,0,0);
2325115f39cSSam Ravnborg break;
2335115f39cSSam Ravnborg }
2345115f39cSSam Ravnborg
2355115f39cSSam Ravnborg /* SUBNORMAL - ftt == 2 */
2365115f39cSSam Ravnborg case FADDD:
2375115f39cSSam Ravnborg case FSUBD:
2385115f39cSSam Ravnborg case FMULD:
2395115f39cSSam Ravnborg case FDIVD: TYPE(2,2,1,2,1,2,1); break;
2405115f39cSSam Ravnborg case FADDS:
2415115f39cSSam Ravnborg case FSUBS:
2425115f39cSSam Ravnborg case FMULS:
2435115f39cSSam Ravnborg case FDIVS: TYPE(2,1,1,1,1,1,1); break;
2445115f39cSSam Ravnborg case FSMULD: TYPE(2,2,1,1,1,1,1); break;
2455115f39cSSam Ravnborg case FSTOX: TYPE(2,2,0,1,1,0,0); break;
2465115f39cSSam Ravnborg case FDTOX: TYPE(2,2,0,2,1,0,0); break;
2475115f39cSSam Ravnborg case FDTOS: TYPE(2,1,1,2,1,0,0); break;
2485115f39cSSam Ravnborg case FSTOD: TYPE(2,2,1,1,1,0,0); break;
2495115f39cSSam Ravnborg case FSTOI: TYPE(2,1,0,1,1,0,0); break;
2505115f39cSSam Ravnborg case FDTOI: TYPE(2,1,0,2,1,0,0); break;
2515115f39cSSam Ravnborg
2525115f39cSSam Ravnborg /* Only Ultra-III generates these */
2535115f39cSSam Ravnborg case FXTOS: TYPE(2,1,1,2,0,0,0); break;
2545115f39cSSam Ravnborg case FXTOD: TYPE(2,2,1,2,0,0,0); break;
2555115f39cSSam Ravnborg #if 0 /* Optimized inline in sparc64/kernel/entry.S */
2565115f39cSSam Ravnborg case FITOS: TYPE(2,1,1,1,0,0,0); break;
2575115f39cSSam Ravnborg #endif
2585115f39cSSam Ravnborg case FITOD: TYPE(2,2,1,1,0,0,0); break;
2595115f39cSSam Ravnborg }
2605115f39cSSam Ravnborg }
2615115f39cSSam Ravnborg else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
2625115f39cSSam Ravnborg IR = 2;
2635115f39cSSam Ravnborg switch ((insn >> 5) & 0x1ff) {
2645115f39cSSam Ravnborg case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
2655115f39cSSam Ravnborg case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
2665115f39cSSam Ravnborg /* Now the conditional fmovq support */
2675115f39cSSam Ravnborg case FMOVQ0:
2685115f39cSSam Ravnborg case FMOVQ1:
2695115f39cSSam Ravnborg case FMOVQ2:
2705115f39cSSam Ravnborg case FMOVQ3:
2715115f39cSSam Ravnborg /* fmovq %fccX, %fY, %fZ */
2725115f39cSSam Ravnborg if (!((insn >> 11) & 3))
2735115f39cSSam Ravnborg XR = current_thread_info()->xfsr[0] >> 10;
2745115f39cSSam Ravnborg else
2755115f39cSSam Ravnborg XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6));
2765115f39cSSam Ravnborg XR &= 3;
2775115f39cSSam Ravnborg IR = 0;
2785115f39cSSam Ravnborg switch ((insn >> 14) & 0x7) {
2795115f39cSSam Ravnborg /* case 0: IR = 0; break; */ /* Never */
2805115f39cSSam Ravnborg case 1: if (XR) IR = 1; break; /* Not Equal */
2815115f39cSSam Ravnborg case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */
2825115f39cSSam Ravnborg case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */
2835115f39cSSam Ravnborg case 4: if (XR == 1) IR = 1; break; /* Less */
2845115f39cSSam Ravnborg case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */
2855115f39cSSam Ravnborg case 6: if (XR == 2) IR = 1; break; /* Greater */
2865115f39cSSam Ravnborg case 7: if (XR == 3) IR = 1; break; /* Unordered */
2875115f39cSSam Ravnborg }
2885115f39cSSam Ravnborg if ((insn >> 14) & 8)
2895115f39cSSam Ravnborg IR ^= 1;
2905115f39cSSam Ravnborg break;
2915115f39cSSam Ravnborg case FMOVQI:
2925115f39cSSam Ravnborg case FMOVQX:
2935115f39cSSam Ravnborg /* fmovq %[ix]cc, %fY, %fZ */
2945115f39cSSam Ravnborg XR = regs->tstate >> 32;
2955115f39cSSam Ravnborg if ((insn >> 5) & 0x80)
2965115f39cSSam Ravnborg XR >>= 4;
2975115f39cSSam Ravnborg XR &= 0xf;
2985115f39cSSam Ravnborg IR = 0;
2995115f39cSSam Ravnborg freg = ((XR >> 2) ^ XR) & 2;
3005115f39cSSam Ravnborg switch ((insn >> 14) & 0x7) {
3015115f39cSSam Ravnborg /* case 0: IR = 0; break; */ /* Never */
3025115f39cSSam Ravnborg case 1: if (XR & 4) IR = 1; break; /* Equal */
3035115f39cSSam Ravnborg case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */
3045115f39cSSam Ravnborg case 3: if (freg) IR = 1; break; /* Less */
3055115f39cSSam Ravnborg case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */
3065115f39cSSam Ravnborg case 5: if (XR & 1) IR = 1; break; /* Carry Set */
3075115f39cSSam Ravnborg case 6: if (XR & 8) IR = 1; break; /* Negative */
3085115f39cSSam Ravnborg case 7: if (XR & 2) IR = 1; break; /* Overflow Set */
3095115f39cSSam Ravnborg }
3105115f39cSSam Ravnborg if ((insn >> 14) & 8)
3115115f39cSSam Ravnborg IR ^= 1;
3125115f39cSSam Ravnborg break;
3135115f39cSSam Ravnborg case FMOVQZ:
3145115f39cSSam Ravnborg case FMOVQLE:
3155115f39cSSam Ravnborg case FMOVQLZ:
3165115f39cSSam Ravnborg case FMOVQNZ:
3175115f39cSSam Ravnborg case FMOVQGZ:
3185115f39cSSam Ravnborg case FMOVQGE:
3195115f39cSSam Ravnborg freg = (insn >> 14) & 0x1f;
3205115f39cSSam Ravnborg if (!freg)
3215115f39cSSam Ravnborg XR = 0;
3225115f39cSSam Ravnborg else if (freg < 16)
3235115f39cSSam Ravnborg XR = regs->u_regs[freg];
324517ffce4SDavid S. Miller else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
3255115f39cSSam Ravnborg struct reg_window32 __user *win32;
3265115f39cSSam Ravnborg flushw_user ();
3275115f39cSSam Ravnborg win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
3285115f39cSSam Ravnborg get_user(XR, &win32->locals[freg - 16]);
3295115f39cSSam Ravnborg } else {
3305115f39cSSam Ravnborg struct reg_window __user *win;
3315115f39cSSam Ravnborg flushw_user ();
3325115f39cSSam Ravnborg win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
3335115f39cSSam Ravnborg get_user(XR, &win->locals[freg - 16]);
3345115f39cSSam Ravnborg }
3355115f39cSSam Ravnborg IR = 0;
3365115f39cSSam Ravnborg switch ((insn >> 10) & 3) {
3375115f39cSSam Ravnborg case 1: if (!XR) IR = 1; break; /* Register Zero */
3385115f39cSSam Ravnborg case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */
3395115f39cSSam Ravnborg case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */
3405115f39cSSam Ravnborg }
3415115f39cSSam Ravnborg if ((insn >> 10) & 4)
3425115f39cSSam Ravnborg IR ^= 1;
3435115f39cSSam Ravnborg break;
3445115f39cSSam Ravnborg }
3455115f39cSSam Ravnborg if (IR == 0) {
3465115f39cSSam Ravnborg /* The fmov test was false. Do a nop instead */
3475115f39cSSam Ravnborg current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
3485115f39cSSam Ravnborg regs->tpc = regs->tnpc;
3495115f39cSSam Ravnborg regs->tnpc += 4;
3505115f39cSSam Ravnborg return 1;
3515115f39cSSam Ravnborg } else if (IR == 1) {
3525115f39cSSam Ravnborg /* Change the instruction into plain fmovq */
3535115f39cSSam Ravnborg insn = (insn & 0x3e00001f) | 0x81a00060;
3545115f39cSSam Ravnborg TYPE(3,3,0,3,0,0,0);
3555115f39cSSam Ravnborg }
3565115f39cSSam Ravnborg }
3575115f39cSSam Ravnborg }
3585115f39cSSam Ravnborg if (type) {
3595115f39cSSam Ravnborg argp rs1 = NULL, rs2 = NULL, rd = NULL;
3605115f39cSSam Ravnborg
361456d3d42SDavid S. Miller /* Starting with UltraSPARC-T2, the cpu does not set the FP Trap
362456d3d42SDavid S. Miller * Type field in the %fsr to unimplemented_FPop. Nor does it
363456d3d42SDavid S. Miller * use the fp_exception_other trap. Instead it signals an
364456d3d42SDavid S. Miller * illegal instruction and leaves the FP trap type field of
365456d3d42SDavid S. Miller * the %fsr unchanged.
366456d3d42SDavid S. Miller */
367456d3d42SDavid S. Miller if (!illegal_insn_trap) {
368456d3d42SDavid S. Miller int ftt = (current_thread_info()->xfsr[0] >> 14) & 0x7;
369456d3d42SDavid S. Miller if (ftt != (type >> 9))
3705115f39cSSam Ravnborg goto err;
371456d3d42SDavid S. Miller }
3725115f39cSSam Ravnborg current_thread_info()->xfsr[0] &= ~0x1c000;
3735115f39cSSam Ravnborg freg = ((insn >> 14) & 0x1f);
3745115f39cSSam Ravnborg switch (type & 0x3) {
3755115f39cSSam Ravnborg case 3: if (freg & 2) {
3765115f39cSSam Ravnborg current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
3775115f39cSSam Ravnborg goto err;
3785115f39cSSam Ravnborg }
3795115f39cSSam Ravnborg case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
3805115f39cSSam Ravnborg case 1: rs1 = (argp)&f->regs[freg];
3815115f39cSSam Ravnborg flags = (freg < 32) ? FPRS_DL : FPRS_DU;
3825115f39cSSam Ravnborg if (!(current_thread_info()->fpsaved[0] & flags))
3835115f39cSSam Ravnborg rs1 = (argp)&zero;
3845115f39cSSam Ravnborg break;
3855115f39cSSam Ravnborg }
3865115f39cSSam Ravnborg switch (type & 0x7) {
3875115f39cSSam Ravnborg case 7: FP_UNPACK_QP (QA, rs1); break;
3885115f39cSSam Ravnborg case 6: FP_UNPACK_DP (DA, rs1); break;
3895115f39cSSam Ravnborg case 5: FP_UNPACK_SP (SA, rs1); break;
3905115f39cSSam Ravnborg }
3915115f39cSSam Ravnborg freg = (insn & 0x1f);
3925115f39cSSam Ravnborg switch ((type >> 3) & 0x3) {
3935115f39cSSam Ravnborg case 3: if (freg & 2) {
3945115f39cSSam Ravnborg current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
3955115f39cSSam Ravnborg goto err;
3965115f39cSSam Ravnborg }
3975115f39cSSam Ravnborg case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
3985115f39cSSam Ravnborg case 1: rs2 = (argp)&f->regs[freg];
3995115f39cSSam Ravnborg flags = (freg < 32) ? FPRS_DL : FPRS_DU;
4005115f39cSSam Ravnborg if (!(current_thread_info()->fpsaved[0] & flags))
4015115f39cSSam Ravnborg rs2 = (argp)&zero;
4025115f39cSSam Ravnborg break;
4035115f39cSSam Ravnborg }
4045115f39cSSam Ravnborg switch ((type >> 3) & 0x7) {
4055115f39cSSam Ravnborg case 7: FP_UNPACK_QP (QB, rs2); break;
4065115f39cSSam Ravnborg case 6: FP_UNPACK_DP (DB, rs2); break;
4075115f39cSSam Ravnborg case 5: FP_UNPACK_SP (SB, rs2); break;
4085115f39cSSam Ravnborg }
4095115f39cSSam Ravnborg freg = ((insn >> 25) & 0x1f);
4105115f39cSSam Ravnborg switch ((type >> 6) & 0x3) {
4115115f39cSSam Ravnborg case 3: if (freg & 2) {
4125115f39cSSam Ravnborg current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
4135115f39cSSam Ravnborg goto err;
4145115f39cSSam Ravnborg }
4155115f39cSSam Ravnborg case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
4165115f39cSSam Ravnborg case 1: rd = (argp)&f->regs[freg];
4175115f39cSSam Ravnborg flags = (freg < 32) ? FPRS_DL : FPRS_DU;
4185115f39cSSam Ravnborg if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
4195115f39cSSam Ravnborg current_thread_info()->fpsaved[0] = FPRS_FEF;
4205115f39cSSam Ravnborg current_thread_info()->gsr[0] = 0;
4215115f39cSSam Ravnborg }
4225115f39cSSam Ravnborg if (!(current_thread_info()->fpsaved[0] & flags)) {
4235115f39cSSam Ravnborg if (freg < 32)
4245115f39cSSam Ravnborg memset(f->regs, 0, 32*sizeof(u32));
4255115f39cSSam Ravnborg else
4265115f39cSSam Ravnborg memset(f->regs+32, 0, 32*sizeof(u32));
4275115f39cSSam Ravnborg }
4285115f39cSSam Ravnborg current_thread_info()->fpsaved[0] |= flags;
4295115f39cSSam Ravnborg break;
4305115f39cSSam Ravnborg }
4315115f39cSSam Ravnborg switch ((insn >> 5) & 0x1ff) {
4325115f39cSSam Ravnborg /* + */
4335115f39cSSam Ravnborg case FADDS: FP_ADD_S (SR, SA, SB); break;
4345115f39cSSam Ravnborg case FADDD: FP_ADD_D (DR, DA, DB); break;
4355115f39cSSam Ravnborg case FADDQ: FP_ADD_Q (QR, QA, QB); break;
4365115f39cSSam Ravnborg /* - */
4375115f39cSSam Ravnborg case FSUBS: FP_SUB_S (SR, SA, SB); break;
4385115f39cSSam Ravnborg case FSUBD: FP_SUB_D (DR, DA, DB); break;
4395115f39cSSam Ravnborg case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
4405115f39cSSam Ravnborg /* * */
4415115f39cSSam Ravnborg case FMULS: FP_MUL_S (SR, SA, SB); break;
4425115f39cSSam Ravnborg case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);
4435115f39cSSam Ravnborg FP_CONV (D, S, 1, 1, DB, SB);
4445115f39cSSam Ravnborg case FMULD: FP_MUL_D (DR, DA, DB); break;
4455115f39cSSam Ravnborg case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);
4465115f39cSSam Ravnborg FP_CONV (Q, D, 2, 1, QB, DB);
4475115f39cSSam Ravnborg case FMULQ: FP_MUL_Q (QR, QA, QB); break;
4485115f39cSSam Ravnborg /* / */
4495115f39cSSam Ravnborg case FDIVS: FP_DIV_S (SR, SA, SB); break;
4505115f39cSSam Ravnborg case FDIVD: FP_DIV_D (DR, DA, DB); break;
4515115f39cSSam Ravnborg case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
4525115f39cSSam Ravnborg /* sqrt */
4535115f39cSSam Ravnborg case FSQRTS: FP_SQRT_S (SR, SB); break;
4545115f39cSSam Ravnborg case FSQRTD: FP_SQRT_D (DR, DB); break;
4555115f39cSSam Ravnborg case FSQRTQ: FP_SQRT_Q (QR, QB); break;
4565115f39cSSam Ravnborg /* mov */
4575115f39cSSam Ravnborg case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;
4585115f39cSSam Ravnborg case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;
4595115f39cSSam Ravnborg case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;
4605115f39cSSam Ravnborg /* float to int */
4615115f39cSSam Ravnborg case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
4625115f39cSSam Ravnborg case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
4635115f39cSSam Ravnborg case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
4645115f39cSSam Ravnborg case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;
4655115f39cSSam Ravnborg case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;
4665115f39cSSam Ravnborg case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;
4675115f39cSSam Ravnborg /* int to float */
4685115f39cSSam Ravnborg case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
4695115f39cSSam Ravnborg case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;
4705115f39cSSam Ravnborg /* Only Ultra-III generates these */
4715115f39cSSam Ravnborg case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break;
4725115f39cSSam Ravnborg case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break;
4735115f39cSSam Ravnborg #if 0 /* Optimized inline in sparc64/kernel/entry.S */
4745115f39cSSam Ravnborg case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
4755115f39cSSam Ravnborg #endif
4765115f39cSSam Ravnborg case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
4775115f39cSSam Ravnborg /* float to float */
4785115f39cSSam Ravnborg case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;
4795115f39cSSam Ravnborg case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;
4805115f39cSSam Ravnborg case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;
4815115f39cSSam Ravnborg case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;
4825115f39cSSam Ravnborg case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;
4835115f39cSSam Ravnborg case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;
4845115f39cSSam Ravnborg /* comparison */
4855115f39cSSam Ravnborg case FCMPQ:
4865115f39cSSam Ravnborg case FCMPEQ:
4875115f39cSSam Ravnborg FP_CMP_Q(XR, QB, QA, 3);
4885115f39cSSam Ravnborg if (XR == 3 &&
4895115f39cSSam Ravnborg (((insn >> 5) & 0x1ff) == FCMPEQ ||
4905115f39cSSam Ravnborg FP_ISSIGNAN_Q(QA) ||
4915115f39cSSam Ravnborg FP_ISSIGNAN_Q(QB)))
4925115f39cSSam Ravnborg FP_SET_EXCEPTION (FP_EX_INVALID);
4935115f39cSSam Ravnborg }
4945115f39cSSam Ravnborg if (!FP_INHIBIT_RESULTS) {
4955115f39cSSam Ravnborg switch ((type >> 6) & 0x7) {
4965115f39cSSam Ravnborg case 0: xfsr = current_thread_info()->xfsr[0];
4975115f39cSSam Ravnborg if (XR == -1) XR = 2;
4985115f39cSSam Ravnborg switch (freg & 3) {
4995115f39cSSam Ravnborg /* fcc0, 1, 2, 3 */
5005115f39cSSam Ravnborg case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break;
5015115f39cSSam Ravnborg case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break;
5025115f39cSSam Ravnborg case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break;
5035115f39cSSam Ravnborg case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break;
5045115f39cSSam Ravnborg }
5055115f39cSSam Ravnborg current_thread_info()->xfsr[0] = xfsr;
5065115f39cSSam Ravnborg break;
5075115f39cSSam Ravnborg case 1: rd->s = IR; break;
5085115f39cSSam Ravnborg case 2: rd->d = XR; break;
5095115f39cSSam Ravnborg case 5: FP_PACK_SP (rd, SR); break;
5105115f39cSSam Ravnborg case 6: FP_PACK_DP (rd, DR); break;
5115115f39cSSam Ravnborg case 7: FP_PACK_QP (rd, QR); break;
5125115f39cSSam Ravnborg }
5135115f39cSSam Ravnborg }
5145115f39cSSam Ravnborg
5155115f39cSSam Ravnborg if(_fex != 0)
5165115f39cSSam Ravnborg return record_exception(regs, _fex);
5175115f39cSSam Ravnborg
5185115f39cSSam Ravnborg /* Success and no exceptions detected. */
5195115f39cSSam Ravnborg current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
5205115f39cSSam Ravnborg regs->tpc = regs->tnpc;
5215115f39cSSam Ravnborg regs->tnpc += 4;
5225115f39cSSam Ravnborg return 1;
5235115f39cSSam Ravnborg }
5245115f39cSSam Ravnborg err: return 0;
5255115f39cSSam Ravnborg }
526