Lines Matching +full:0 +full:x042
29 #define FMOVQ 0x003
30 #define FNEGQ 0x007
31 #define FABSQ 0x00b
32 #define FSQRTQ 0x02b
33 #define FADDQ 0x043
34 #define FSUBQ 0x047
35 #define FMULQ 0x04b
36 #define FDIVQ 0x04f
37 #define FDMULQ 0x06e
38 #define FQTOX 0x083
39 #define FXTOQ 0x08c
40 #define FQTOS 0x0c7
41 #define FQTOD 0x0cb
42 #define FITOQ 0x0cc
43 #define FSTOQ 0x0cd
44 #define FDTOQ 0x0ce
45 #define FQTOI 0x0d3
47 #define FSQRTS 0x029
48 #define FSQRTD 0x02a
49 #define FADDS 0x041
50 #define FADDD 0x042
51 #define FSUBS 0x045
52 #define FSUBD 0x046
53 #define FMULS 0x049
54 #define FMULD 0x04a
55 #define FDIVS 0x04d
56 #define FDIVD 0x04e
57 #define FSMULD 0x069
58 #define FSTOX 0x081
59 #define FDTOX 0x082
60 #define FDTOS 0x0c6
61 #define FSTOD 0x0c9
62 #define FSTOI 0x0d1
63 #define FDTOI 0x0d2
64 #define FXTOS 0x084 /* Only Ultra-III generates this. */
65 #define FXTOD 0x088 /* Only Ultra-III generates this. */
66 #if 0 /* Optimized inline in sparc64/kernel/entry.S */
67 #define FITOS 0x0c4 /* Only Ultra-III generates this. */
69 #define FITOD 0x0c8 /* Only Ultra-III generates this. */
71 #define FCMPQ 0x053
72 #define FCMPEQ 0x057
73 #define FMOVQ0 0x003
74 #define FMOVQ1 0x043
75 #define FMOVQ2 0x083
76 #define FMOVQ3 0x0c3
77 #define FMOVQI 0x103
78 #define FMOVQX 0x183
79 #define FMOVQZ 0x027
80 #define FMOVQLE 0x047
81 #define FMOVQLZ 0x067
82 #define FMOVQNZ 0x0a7
83 #define FMOVQGZ 0x0c7
84 #define FMOVQGE 0x0e7
87 #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
89 #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
90 #define FSR_CEXC_SHIFT 0UL
91 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
99 * We return 0 if a SIGFPE should be sent, 1 otherwise.
103 u64 fsr = current_thread_info()->xfsr[0]; in record_exception()
107 would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL; in record_exception()
110 if(would_trap != 0) { in record_exception()
112 if((eflag & (eflag - 1)) != 0) { in record_exception()
141 if(would_trap == 0) in record_exception()
145 if(would_trap != 0) in record_exception()
148 current_thread_info()->xfsr[0] = fsr; in record_exception()
153 if(would_trap == 0) { in record_exception()
158 return (would_trap ? 0 : 1); in record_exception()
171 u32 insn = 0; in do_mathemu()
172 int type = 0; in do_mathemu()
174 whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack) in do_mathemu()
175 non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */ in do_mathemu()
176 #define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << … in do_mathemu()
178 static u64 zero[2] = { 0L, 0L }; in do_mathemu()
189 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); in do_mathemu()
193 if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ { in do_mathemu()
194 switch ((insn >> 5) & 0x1ff) { in do_mathemu()
198 case FABSQ: TYPE(3,3,0,3,0,0,0); break; in do_mathemu()
199 case FSQRTQ: TYPE(3,3,1,3,1,0,0); break; in do_mathemu()
205 case FQTOX: TYPE(3,2,0,3,1,0,0); break; in do_mathemu()
206 case FXTOQ: TYPE(3,3,1,2,0,0,0); break; in do_mathemu()
207 case FQTOS: TYPE(3,1,1,3,1,0,0); break; in do_mathemu()
208 case FQTOD: TYPE(3,2,1,3,1,0,0); break; in do_mathemu()
209 case FITOQ: TYPE(3,3,1,1,0,0,0); break; in do_mathemu()
210 case FSTOQ: TYPE(3,3,1,1,1,0,0); break; in do_mathemu()
211 case FDTOQ: TYPE(3,3,1,2,1,0,0); break; in do_mathemu()
212 case FQTOI: TYPE(3,1,0,3,1,0,0); break; in do_mathemu()
220 unsigned long x = current_thread_info()->xfsr[0]; in do_mathemu()
222 x = (x >> 14) & 0x7; in do_mathemu()
223 TYPE(x,1,1,1,1,0,0); in do_mathemu()
228 unsigned long x = current_thread_info()->xfsr[0]; in do_mathemu()
230 x = (x >> 14) & 0x7; in do_mathemu()
231 TYPE(x,2,1,2,1,0,0); in do_mathemu()
245 case FSTOX: TYPE(2,2,0,1,1,0,0); break; in do_mathemu()
246 case FDTOX: TYPE(2,2,0,2,1,0,0); break; in do_mathemu()
247 case FDTOS: TYPE(2,1,1,2,1,0,0); break; in do_mathemu()
248 case FSTOD: TYPE(2,2,1,1,1,0,0); break; in do_mathemu()
249 case FSTOI: TYPE(2,1,0,1,1,0,0); break; in do_mathemu()
250 case FDTOI: TYPE(2,1,0,2,1,0,0); break; in do_mathemu()
253 case FXTOS: TYPE(2,1,1,2,0,0,0); break; in do_mathemu()
254 case FXTOD: TYPE(2,2,1,2,0,0,0); break; in do_mathemu()
255 #if 0 /* Optimized inline in sparc64/kernel/entry.S */ in do_mathemu()
256 case FITOS: TYPE(2,1,1,1,0,0,0); break; in do_mathemu()
258 case FITOD: TYPE(2,2,1,1,0,0,0); break; in do_mathemu()
261 else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ { in do_mathemu()
263 switch ((insn >> 5) & 0x1ff) { in do_mathemu()
264 case FCMPQ: TYPE(3,0,0,3,1,3,1); break; in do_mathemu()
265 case FCMPEQ: TYPE(3,0,0,3,1,3,1); break; in do_mathemu()
273 XR = current_thread_info()->xfsr[0] >> 10; in do_mathemu()
275 XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6)); in do_mathemu()
277 IR = 0; in do_mathemu()
278 switch ((insn >> 14) & 0x7) { in do_mathemu()
279 /* case 0: IR = 0; break; */ /* Never */ in do_mathemu()
295 if ((insn >> 5) & 0x80) in do_mathemu()
297 XR &= 0xf; in do_mathemu()
298 IR = 0; in do_mathemu()
300 switch ((insn >> 14) & 0x7) { in do_mathemu()
301 /* case 0: IR = 0; break; */ /* Never */ in do_mathemu()
319 freg = (insn >> 14) & 0x1f; in do_mathemu()
321 XR = 0; in do_mathemu()
335 IR = 0; in do_mathemu()
338 case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */ in do_mathemu()
339 case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */ in do_mathemu()
345 if (IR == 0) { in do_mathemu()
347 current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK); in do_mathemu()
353 insn = (insn & 0x3e00001f) | 0x81a00060; in do_mathemu()
354 TYPE(3,3,0,3,0,0,0); in do_mathemu()
368 int ftt = (current_thread_info()->xfsr[0] >> 14) & 0x7; in do_mathemu()
372 current_thread_info()->xfsr[0] &= ~0x1c000; in do_mathemu()
373 freg = ((insn >> 14) & 0x1f); in do_mathemu()
374 switch (type & 0x3) { in do_mathemu()
376 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; in do_mathemu()
379 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e); in do_mathemu()
382 if (!(current_thread_info()->fpsaved[0] & flags)) in do_mathemu()
386 switch (type & 0x7) { in do_mathemu()
391 freg = (insn & 0x1f); in do_mathemu()
392 switch ((type >> 3) & 0x3) { in do_mathemu()
394 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; in do_mathemu()
397 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e); in do_mathemu()
400 if (!(current_thread_info()->fpsaved[0] & flags)) in do_mathemu()
404 switch ((type >> 3) & 0x7) { in do_mathemu()
409 freg = ((insn >> 25) & 0x1f); in do_mathemu()
410 switch ((type >> 6) & 0x3) { in do_mathemu()
412 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; in do_mathemu()
415 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e); in do_mathemu()
418 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in do_mathemu()
419 current_thread_info()->fpsaved[0] = FPRS_FEF; in do_mathemu()
420 current_thread_info()->gsr[0] = 0; in do_mathemu()
422 if (!(current_thread_info()->fpsaved[0] & flags)) { in do_mathemu()
424 memset(f->regs, 0, 32*sizeof(u32)); in do_mathemu()
426 memset(f->regs+32, 0, 32*sizeof(u32)); in do_mathemu()
428 current_thread_info()->fpsaved[0] |= flags; in do_mathemu()
431 switch ((insn >> 5) & 0x1ff) { in do_mathemu()
457 case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break; in do_mathemu()
458 case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break; in do_mathemu()
459 case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break; in do_mathemu()
473 #if 0 /* Optimized inline in sparc64/kernel/entry.S */ in do_mathemu()
489 (((insn >> 5) & 0x1ff) == FCMPEQ || in do_mathemu()
495 switch ((type >> 6) & 0x7) { in do_mathemu()
496 case 0: xfsr = current_thread_info()->xfsr[0]; in do_mathemu()
500 case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break; in do_mathemu()
501 case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break; in do_mathemu()
502 case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break; in do_mathemu()
503 case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break; in do_mathemu()
505 current_thread_info()->xfsr[0] = xfsr; in do_mathemu()
515 if(_fex != 0) in do_mathemu()
519 current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK); in do_mathemu()
524 err: return 0; in do_mathemu()