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/linux/arch/x86/include/asm/e820/
H A Dtypes.h37 E820_TYPE_SOFT_RESERVED = 0xefffffff,
102 #define ISA_START_ADDRESS 0x000a0000
103 #define ISA_END_ADDRESS 0x00100000
105 #define BIOS_BEGIN 0x000a0000
106 #define BIOS_END 0x00100000
108 #define HIGH_MEMORY 0x00100000
110 #define BIOS_ROM_BASE 0xffe00000
111 #define BIOS_ROM_END 0xffffffff
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-4i-edge-200.dts20 reg = <0x00000000 0x20000000>;
30 pinctrl-0 = <&pmx_led>;
75 reg = <0x0b>;
79 <3 0x10 0xfff0 0xf>; /* Reg 3,16 <- 0xzzzf */
84 reg = <0x11>;
88 #size-cells = <0>;
90 port@0 {
91 reg = <0>;
126 pinctrl-0 = <&pmx_nand>;
129 partition@0 {
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958522er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958525er.dts48 reg = <0x60000000 0x80000000>;
78 nand@0 {
80 reg = <0>;
91 partition@0 {
93 reg = <0x00000000 0x00200000>;
98 reg = <0x00200000 0x00400000>;
102 reg = <0x00600000 0x00a00000>;
106 reg = <0x01000000 0x03000000>;
110 reg = <0x04000000 0x3c000000>;
129 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958525xmc.dts48 reg = <0x60000000 0x40000000>;
78 reg = <0x4c>;
83 reg = <0x52>;
89 reg = <0x68>;
94 nand@0 {
96 reg = <0>;
107 partition@0 {
109 reg = <0x00000000 0x00200000>;
114 reg = <0x00200000 0x00400000>;
118 reg = <0x00600000 0x00a00000>;
[all …]
H A Dbcm958622hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958625hr.dts48 reg = <0x60000000 0x20000000>;
93 nand@0 {
95 reg = <0>;
106 partition@0 {
108 reg = <0x00000000 0x00200000>;
113 reg = <0x00200000 0x00400000>;
117 reg = <0x00600000 0x00a00000>;
121 reg = <0x01000000 0x03000000>;
125 reg = <0x04000000 0x3c000000>;
144 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958623hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm988312hr.dts48 reg = <0x60000000 0x80000000>;
82 nand@0 {
84 reg = <0>;
95 partition@0 {
97 reg = <0x00000000 0x00200000>;
102 reg = <0x00200000 0x00400000>;
106 reg = <0x00600000 0x00a00000>;
110 reg = <0x01000000 0x03000000>;
114 reg = <0x04000000 0x3c000000>;
133 pinctrl-0 = <&nand_sel>;
[all …]
H A Dbcm958625k.dts47 reg = <0x60000000 0x80000000>;
72 nand@0 {
74 reg = <0>;
85 partition@0 {
87 reg = <0x00000000 0x00200000>;
92 reg = <0x00200000 0x00400000>;
96 reg = <0x00600000 0x00a00000>;
100 reg = <0x01000000 0x03000000>;
104 reg = <0x04000000 0x3c000000>;
127 pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>;
[all …]
/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2-svk.dts50 bootargs = "earlycon=uart8250,mmio32,0x66130000";
55 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
110 slic@0 {
112 reg = <0>;
116 pl022,interface = <0>;
117 pl022,slave-tx-disable = <0>;
118 pl022,com-mode = <0>;
122 pl022,wait-state = <0>;
123 pl022,duplex = <0>;
130 at25@0 {
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
H A Domap4-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
/linux/arch/x86/include/uapi/asm/
H A De820.h4 #define E820MAP 0x2d0 /* our map */
29 #define E820NR 0x1e8 /* # entries in E820MAP */
70 #define ISA_START_ADDRESS 0xa0000
71 #define ISA_END_ADDRESS 0x100000
73 #define BIOS_BEGIN 0x000a0000
74 #define BIOS_END 0x00100000
76 #define BIOS_ROM_BASE 0xffe00000
77 #define BIOS_ROM_END 0xffffffff
/linux/arch/arm/mach-footbridge/
H A Debsa285.c22 #define XBUS_AMBER_L BIT(0)
84 for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) { in ebsa285_leds_init()
97 if (led_classdev_register(NULL, &led->cdev) < 0) { in ebsa285_leds_init()
103 return 0; in ebsa285_leds_init()
115 .atag_offset = 0x100,
116 .video_start = 0x000a0000,
117 .video_end = 0x000bffff,
H A Ddc21285.c39 unsigned long addr = 0; in dc21285_base_address()
41 if (bus->number == 0) { in dc21285_base_address()
42 if (PCI_SLOT(devfn) == 0) in dc21285_base_address()
44 * For devfn 0, point at the 21285 in dc21285_base_address()
50 if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) in dc21285_base_address()
51 addr = PCICFG0_BASE | 0xc00000 | (devfn << 8); in dc21285_base_address()
64 u32 v = 0xffffffff; in dc21285_read_config()
69 asm volatile("ldrb %0, [%1, %2]" in dc21285_read_config()
73 asm volatile("ldrh %0, [%1, %2]" in dc21285_read_config()
77 asm volatile("ldr %0, [%1, %2]" in dc21285_read_config()
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/linux/arch/powerpc/boot/dts/
H A Duc101.dts75 phy0: ethernet-phy@0 {
77 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
105 ranges = <0 0 0xff800000 0x00800000
106 1 0 0x80000000 0x00800000
107 3 0 0x80000000 0x00800000>;
109 flash@0,0 {
111 reg = <0 0 0x00800000>;
117 partition@0 {
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/linux/drivers/mtd/maps/
H A Dcfi_flagadm.c36 * 1: bootloader first 128k (0x00000000 - 0x0001FFFF) size 0x020000
37 * 2: kernel 640k (0x00020000 - 0x000BFFFF) size 0x0A0000
38 * 3: compressed 1536k root ramdisk (0x000C0000 - 0x0023FFFF) size 0x180000
39 * 4: writeable diskpartition (jffs)(0x00240000 - 0x003FFFFF) size 0x1C0000
42 #define FLASH_PHYS_ADDR 0x40000000
43 #define FLASH_SIZE 0x400000
45 #define FLASH_PARTITION0_ADDR 0x00000000
46 #define FLASH_PARTITION0_SIZE 0x00020000
48 #define FLASH_PARTITION1_ADDR 0x00020000
49 #define FLASH_PARTITION1_SIZE 0x000A0000
[all …]
/linux/arch/s390/boot/
H A Dhead.S10 * 1) load the image directly into ram at address 0 and do an PSW restart
11 * 2) linload will load the image from address 0x10000 to memory 0x10000
12 * and start the code thru LPSW 0x0008000080010000 (VM only, deprecated)
20 * params for kernel are pushed to 0x10400 (see setup.h)
32 #define EP_OFFSET 0x10008
34 #define IPL_BS 0x730
41 sigp %r1,%r0,0x12 # switch to esame mode
66 clc 0(3,%r4),0(%r13) # if it is HDRx
69 clc 0(3,%r4),0(%r13) # if it is EOFx
91 clc 0(3,%r2),0(%r13)
[all …]
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850-evm.dts29 pinctrl-0 = <&ecap2_pins>;
37 pwms = <&ecap2 0 50000 0>;
38 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
45 pinctrl-0 = <&lcd_pins>;
56 ac-bias-intrpt = <0>;
59 fdd = <0x80>;
60 sync-edge = <0>;
62 raster-order = <0>;
63 fifo-th = <0>;
78 hsync-active = <0>;
[all …]
/linux/drivers/net/ethernet/synopsys/
H A Ddwc-xlgmac-reg.h22 #define MAC_TCR 0x0000
23 #define MAC_RCR 0x0004
24 #define MAC_PFR 0x0008
25 #define MAC_HTR0 0x0010
26 #define MAC_VLANTR 0x0050
27 #define MAC_VLANHTR 0x0058
28 #define MAC_VLANIR 0x0060
29 #define MAC_Q0TFCR 0x0070
30 #define MAC_RFCR 0x0090
31 #define MAC_RQC0R 0x00a0
[all …]

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