Lines Matching +full:0 +full:x000a0000
10 * 1) load the image directly into ram at address 0 and do an PSW restart
11 * 2) linload will load the image from address 0x10000 to memory 0x10000
12 * and start the code thru LPSW 0x0008000080010000 (VM only, deprecated)
20 * params for kernel are pushed to 0x10400 (see setup.h)
32 #define EP_OFFSET 0x10008
34 #define IPL_BS 0x730
41 sigp %r1,%r0,0x12 # switch to esame mode
66 clc 0(3,%r4),0(%r13) # if it is HDRx
69 clc 0(3,%r4),0(%r13) # if it is EOFx
91 clc 0(3,%r2),0(%r13)
94 clc 0(3,%r2),0(%r13)
100 stidp 0(%r13) # store cpuid
101 tm 0(%r13),0xff # running VM ?
107 stsch 0(%r5) # check if irq is pending
108 tm 30(%r5),0x0f # by verifying if any of the
110 tm 31(%r5),0xff # bits is set in the schib
117 tsch 0(%r5)
130 mvc __LC_IO_NEW_PSW(8),0(%r13)
133 lpswe 0(%r13)
146 la %r2,0x50(%r2)
150 lctlg %c6,%c6,0(%r13)
153 ssch 0(%r3) # load chunk of 1600 bytes
159 tsch 0(%r5)
174 aghi %r2,0x640 # add 0x640 to total size
179 aghi %r0,0x640
186 lpsw 0(%r13)
190 .quad 0x0202000180000000,.Lioint
192 .quad 0x0000000180000000
194 .Lorb: .long 0x00000000,0x0080ff00,.Lccws
195 .Lirb: .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
197 .Lcr6: .quad 0x00000000ff000000
199 .Lcrash:.long 0x000a0000,0x00000000
202 .long 0x02600050,0x00000000
204 .long 0x02200050,0x00000000
205 .Lreset:.byte 0xc3,0xc8,0xc1,0xd5,0xc7,0xc5,0x40,0xd9,0xc4,0xd9,0x40
206 .byte 0xc1,0xd3,0xd3,0x40,0xd2,0xc5,0xc5,0xd7,0x40,0xd5,0xd6
207 .byte 0xc8,0xd6,0xd3,0xc4 # "change rdr all keep nohold"
208 .L_eof: .long 0xc5d6c600 /* C'EOF' */
209 .L_hdr: .long 0xc8c4d900 /* C'HDR' */
211 .Lcpuid:.fill 8,1,0
223 # This is a list of s390 kernel entry points. At address 0x1000f the number of
229 .byte 0x00,0x01
240 sigp %r1,%r0,0x12 # switch to esame mode
241 bras %r13,0f
242 .fill 16,4,0x0
243 0: lmh %r0,%r15,0(%r13) # clear high-order half of gprs
246 mvc __LC_EXT_NEW_PSW(16),0(%r13)
248 mvc __LC_PGM_NEW_PSW(16),0(%r13)
250 mvc __LC_IO_NEW_PSW(16),0(%r13)
251 xc 0x200(256),0x200 # partially clear lowcore
252 xc 0x300(256),0x300
253 xc 0xe00(256),0xe00
254 xc 0xf00(256),0xf00
256 lctlg %c0,%c15,0(%r13) # load control registers
260 spt 0(%r13)
261 mvc __LC_LAST_UPDATE_TIMER(8),0(%r13)
269 6: .long 0x7fffffff,0xffffffff
271 .quad 0x0002000180000000,0x1b0 # disabled wait
273 .quad 0x0000000180000000,startup_pgm_check_handler
275 .quad 0x0002000180000000,0x1f0 # disabled wait
276 .Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
277 .quad 0 # cr1: primary space segment table
278 .quad 0 # cr2: dispatchable unit control table
279 .quad 0 # cr3: instruction authorization
280 .quad 0xffff # cr4: instruction authorization
281 .quad 0 # cr5: primary-aste origin
282 .quad 0 # cr6: I/O interrupts
283 .quad 0 # cr7: secondary space segment table
284 .quad 0x0000000000008000 # cr8: access registers translation
285 .quad 0 # cr9: tracing off
286 .quad 0 # cr10: tracing off
287 .quad 0 # cr11: tracing off
288 .quad 0 # cr12: tracing off
289 .quad 0 # cr13: home space segment table
290 .quad 0xc0000000 # cr14: machine check handling off
291 .quad 0 # cr15: linkage stack operations
309 ni __LC_RETURN_PSW,0xfc # remove IO and EX bits
310 ni __LC_RETURN_PSW+1,0xfb # remove MCHK bit
311 oi __LC_RETURN_PSW+1,0x2 # set wait state bit