Lines Matching +full:0 +full:x000a0000
1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
22 <0x00024000 0x00024000 0x001000>, /* ap 4 */
23 <0x00025000 0x00025000 0x001000>, /* ap 5 */
24 <0x00026000 0x00026000 0x001000>, /* ap 6 */
25 <0x00027000 0x00027000 0x001000>, /* ap 7 */
26 <0x00028000 0x00028000 0x001000>, /* ap 8 */
27 <0x00029000 0x00029000 0x001000>, /* ap 9 */
28 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
29 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
30 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
31 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
32 <0x00030000 0x00030000 0x001000>, /* ap 14 */
33 <0x00031000 0x00031000 0x001000>, /* ap 15 */
34 <0x00032000 0x00032000 0x001000>, /* ap 16 */
35 <0x00033000 0x00033000 0x001000>, /* ap 17 */
36 <0x00038000 0x00038000 0x001000>, /* ap 18 */
37 <0x00039000 0x00039000 0x001000>, /* ap 19 */
38 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
39 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
40 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
41 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
42 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
43 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
44 <0x00080000 0x00080000 0x010000>, /* ap 26 */
45 <0x00080000 0x00080000 0x001000>, /* ap 27 */
46 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
47 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
48 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
49 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
50 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
51 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
54 <0x49000000 0x49000000 0x000400>, /* ap 0 */
55 <0x49000400 0x49000400 0x000400>, /* ap 1 */
56 <0x49022000 0x49022000 0x001000>, /* ap 2 */
57 <0x49023000 0x49023000 0x001000>, /* ap 3 */
58 <0x49024000 0x49024000 0x001000>, /* ap 4 */
59 <0x49025000 0x49025000 0x001000>, /* ap 5 */
60 <0x49026000 0x49026000 0x001000>, /* ap 6 */
61 <0x49027000 0x49027000 0x001000>, /* ap 7 */
62 <0x49028000 0x49028000 0x001000>, /* ap 8 */
63 <0x49029000 0x49029000 0x001000>, /* ap 9 */
64 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
65 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
66 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
67 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
68 <0x49030000 0x49030000 0x001000>, /* ap 14 */
69 <0x49031000 0x49031000 0x001000>, /* ap 15 */
70 <0x49032000 0x49032000 0x001000>, /* ap 16 */
71 <0x49033000 0x49033000 0x001000>, /* ap 17 */
72 <0x49038000 0x49038000 0x001000>, /* ap 18 */
73 <0x49039000 0x49039000 0x001000>, /* ap 19 */
74 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
75 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
76 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
77 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
78 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
79 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
80 <0x49080000 0x49080000 0x010000>, /* ap 26 */
81 <0x49080000 0x49080000 0x001000>, /* ap 27 */
82 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
83 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
84 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
85 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
86 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
87 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
89 target-module@22000 { /* 0x40122000, ap 2 02.0 */
91 reg = <0x2208c 0x4>;
100 clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
104 ranges = <0x0 0x22000 0x1000>,
105 <0x49022000 0x49022000 0x1000>;
107 mcbsp1: mcbsp@0 {
109 reg = <0x0 0xff>, /* MPU private access */
110 <0x49022000 0xff>; /* L3 Interconnect */
124 target-module@24000 { /* 0x40124000, ap 4 04.0 */
126 reg = <0x2408c 0x4>;
135 clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
139 ranges = <0x0 0x24000 0x1000>,
140 <0x49024000 0x49024000 0x1000>;
142 mcbsp2: mcbsp@0 {
144 reg = <0x0 0xff>, /* MPU private access */
145 <0x49024000 0xff>; /* L3 Interconnect */
159 target-module@26000 { /* 0x40126000, ap 6 06.0 */
161 reg = <0x2608c 0x4>;
170 clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
174 ranges = <0x0 0x26000 0x1000>,
175 <0x49026000 0x49026000 0x1000>;
177 mcbsp3: mcbsp@0 {
179 reg = <0x0 0xff>, /* MPU private access */
180 <0x49026000 0xff>; /* L3 Interconnect */
194 target-module@28000 { /* 0x40128000, ap 8 08.0 */
199 ranges = <0x0 0x28000 0x1000>,
200 <0x49028000 0x49028000 0x1000>;
203 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
208 ranges = <0x0 0x2a000 0x1000>,
209 <0x4902a000 0x4902a000 0x1000>;
212 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
214 reg = <0x2e000 0x4>,
215 <0x2e010 0x4>;
224 clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
228 ranges = <0x0 0x2e000 0x1000>,
229 <0x4902e000 0x4902e000 0x1000>;
231 dmic: dmic@0 {
233 reg = <0x0 0x7f>, /* MPU private access */
234 <0x4902e000 0x7f>; /* L3 Interconnect */
243 target-module@30000 { /* 0x40130000, ap 14 0e.0 */
248 ranges = <0x0 0x30000 0x1000>,
249 <0x49030000 0x49030000 0x1000>;
252 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
254 reg = <0x32000 0x4>,
255 <0x32010 0x4>;
264 clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
268 ranges = <0x0 0x32000 0x1000>,
269 <0x49032000 0x49032000 0x1000>;
274 mcpdm: mcpdm@0 {
276 reg = <0x0 0x7f>, /* MPU private access */
277 <0x49032000 0x7f>; /* L3 Interconnect */
286 target-module@38000 { /* 0x40138000, ap 18 12.0 */
288 reg = <0x38000 0x4>,
289 <0x38010 0x4>;
298 clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
302 ranges = <0x0 0x38000 0x1000>,
303 <0x49038000 0x49038000 0x1000>;
305 timer5: timer@0 {
307 reg = <0x0 0x80>,
308 <0x49038000 0x80>;
318 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
320 reg = <0x3a000 0x4>,
321 <0x3a010 0x4>;
330 clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
334 ranges = <0x0 0x3a000 0x1000>,
335 <0x4903a000 0x4903a000 0x1000>;
337 timer6: timer@0 {
339 reg = <0x0 0x80>,
340 <0x4903a000 0x80>;
350 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
352 reg = <0x3c000 0x4>,
353 <0x3c010 0x4>;
362 clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
366 ranges = <0x0 0x3c000 0x1000>,
367 <0x4903c000 0x4903c000 0x1000>;
369 timer7: timer@0 {
371 reg = <0x0 0x80>,
372 <0x4903c000 0x80>;
381 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
383 reg = <0x3e000 0x4>,
384 <0x3e010 0x4>;
393 clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
397 ranges = <0x0 0x3e000 0x1000>,
398 <0x4903e000 0x4903e000 0x1000>;
400 timer8: timer@0 {
402 reg = <0x0 0x80>,
403 <0x4903e000 0x80>;
413 target-module@80000 { /* 0x40180000, ap 26 1a.0 */
418 ranges = <0x0 0x80000 0x10000>,
419 <0x49080000 0x49080000 0x10000>;
422 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
427 ranges = <0x0 0xa0000 0x10000>,
428 <0x490a0000 0x490a0000 0x10000>;
431 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
436 ranges = <0x0 0xc0000 0x10000>,
437 <0x490c0000 0x490c0000 0x10000>;
440 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
442 reg = <0xf1000 0x4>,
443 <0xf1010 0x4>;
453 clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
457 ranges = <0x0 0xf1000 0x1000>,
458 <0x490f1000 0x490f1000 0x1000>;