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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
H A Dtegra30-lg-p880.dts17 pinctrl-0 = <&state_default>;
120 emc-timings-0 {
122 nvidia,ram-code = <0>;
127 nvidia,emem-configuration = < 0x00050001 0xc0000010
128 0x00000001 0x00000001 0x00000002 0x00000000
129 0x00000003 0x00000001 0x00000002 0x00000004
130 0x00000001 0x00000000 0x00000002 0x00000002
131 0x02020001 0x00060402 0x77230303 0x001f0000 >;
137 nvidia,emem-configuration = < 0x00020001 0xc0000010
138 0x00000001 0x00000001 0x00000002 0x00000000
[all …]
H A Dtegra30-lg-p895.dts12 pinctrl-0 = <&state_default>;
123 nvidia,emem-configuration = < 0x00020001 0xc0000010
124 0x00000001 0x00000001 0x00000002 0x00000000
125 0x00000003 0x00000001 0x00000002 0x00000004
126 0x00000001 0x00000000 0x00000002 0x00000002
127 0x02020001 0x00060402 0x77230303 0x001f0000 >;
133 nvidia,emem-configuration = < 0x00030003 0xc0000010
134 0x00000001 0x00000001 0x00000002 0x00000000
135 0x00000003 0x00000001 0x00000002 0x00000004
136 0x00000001 0x00000000 0x00000002 0x00000002
[all …]
H A Dtegra30-pegatron-chagall.dts49 reg = <0x80000000 0x40000000>;
59 alloc-ranges = <0x80000000 0x30000000>;
60 size = <0x10000000>; /* 256MiB */
67 reg = <0xbeb00000 0x10000>; /* 64kB */
68 console-size = <0x8000>; /* 32kB */
69 record-size = <0x400>; /* 1kB */
74 reg = <0xbfe00000 0x200000>; /* 2MB */
100 pinctrl-0 = <&state_default>;
144 nvidia,lock = <0>;
145 nvidia,io-reset = <0>;
[all …]
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml33 const: 0
51 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
93 minimum: 0
156 minimum: 0
356 reg = <0x70019000 0x1000>;
369 reg = <0x7001b000 0x1000>;
377 #interconnect-cells = <0>;
379 emc-timings-0 {
382 timing-0 {
[all …]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc3250-phy3250.dts18 reg = <0x80000000 0x4000000>;
25 gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
30 gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
51 gpio = <&gpio 5 4 0>;
61 gpio = <&gpio 5 0 0>;
71 gpio = <&gpio 5 5 0>;
84 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
94 reg = <0x18>;
95 power-gpio = <&gpio 3 10 0>;
96 reset-gpio = <&gpio 3 2 0>;
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-mlc.txt28 reg = <0x200A8000 0x11000>;
29 interrupts = <11 0>;
44 reg = <0x00000000 0x00064000>;
H A Dlpc32xx-slc.txt29 reg = <0x20020000 0x1000>;
46 reg = <0x00000000 0x00064000>;
/linux/drivers/mtd/parsers/
H A Dsharpslpart.c43 #define BLOCK_IS_RESERVED 0xffff
49 #define SHARPSL_PARTINFO1_LADDR 0x00060000
50 #define SHARPSL_PARTINFO2_LADDR 0x00064000
52 #define BOOT_MAGIC 0x424f4f54
53 #define FSRO_MAGIC 0x4653524f
54 #define FSRW_MAGIC 0x46535257
72 u8 freebytes = 0; in sharpsl_nand_check_ooblayout()
73 int section = 0; in sharpsl_nand_check_ooblayout()
91 if (freebytes == 0xff) in sharpsl_nand_check_ooblayout()
92 return 0; in sharpsl_nand_check_ooblayout()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
H A Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x00000004},
15 {0x70C, 0x00000020},
16 {0x704, 0x601E0100},
17 {0x4000, 0x00000000},
18 {0x4004, 0xCA014000},
19 {0x4008, 0xC751D4F0},
[all …]