1724ba675SRob Herring&l4_cfg { /* 0x4a000000 */
2724ba675SRob Herring compatible = "ti,dra7-l4-cfg", "simple-pm-bus";
3724ba675SRob Herring power-domains = <&prm_coreaon>;
4724ba675SRob Herring clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
5724ba675SRob Herring clock-names = "fck";
6724ba675SRob Herring reg = <0x4a000000 0x800>,
7724ba675SRob Herring <0x4a000800 0x800>,
8724ba675SRob Herring <0x4a001000 0x1000>;
9724ba675SRob Herring reg-names = "ap", "la", "ia0";
10724ba675SRob Herring #address-cells = <1>;
11724ba675SRob Herring #size-cells = <1>;
12724ba675SRob Herring ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13724ba675SRob Herring <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14724ba675SRob Herring <0x00200000 0x4a200000 0x100000>; /* segment 2 */
15724ba675SRob Herring
16724ba675SRob Herring segment@0 { /* 0x4a000000 */
17724ba675SRob Herring compatible = "simple-pm-bus";
18724ba675SRob Herring #address-cells = <1>;
19724ba675SRob Herring #size-cells = <1>;
20724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
21724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */
22724ba675SRob Herring <0x00001000 0x00001000 0x001000>, /* ap 2 */
23724ba675SRob Herring <0x00002000 0x00002000 0x002000>, /* ap 3 */
24724ba675SRob Herring <0x00004000 0x00004000 0x001000>, /* ap 4 */
25724ba675SRob Herring <0x00005000 0x00005000 0x001000>, /* ap 5 */
26724ba675SRob Herring <0x00006000 0x00006000 0x001000>, /* ap 6 */
27724ba675SRob Herring <0x00008000 0x00008000 0x002000>, /* ap 7 */
28724ba675SRob Herring <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
29724ba675SRob Herring <0x00056000 0x00056000 0x001000>, /* ap 9 */
30724ba675SRob Herring <0x00057000 0x00057000 0x001000>, /* ap 10 */
31724ba675SRob Herring <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
32724ba675SRob Herring <0x00060000 0x00060000 0x001000>, /* ap 12 */
33724ba675SRob Herring <0x00080000 0x00080000 0x008000>, /* ap 13 */
34724ba675SRob Herring <0x00088000 0x00088000 0x001000>, /* ap 14 */
35724ba675SRob Herring <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
36724ba675SRob Herring <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
37724ba675SRob Herring <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
38724ba675SRob Herring <0x000da000 0x000da000 0x001000>, /* ap 18 */
39724ba675SRob Herring <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
40724ba675SRob Herring <0x000de000 0x000de000 0x001000>, /* ap 20 */
41724ba675SRob Herring <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
42724ba675SRob Herring <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
43724ba675SRob Herring <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
44724ba675SRob Herring <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
45724ba675SRob Herring <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
46724ba675SRob Herring <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
47724ba675SRob Herring <0x00090000 0x00090000 0x008000>, /* ap 59 */
48724ba675SRob Herring <0x00098000 0x00098000 0x001000>; /* ap 60 */
49724ba675SRob Herring
50724ba675SRob Herring target-module@2000 { /* 0x4a002000, ap 3 08.0 */
51724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
52724ba675SRob Herring reg = <0x2000 0x4>;
53724ba675SRob Herring reg-names = "rev";
54724ba675SRob Herring #address-cells = <1>;
55724ba675SRob Herring #size-cells = <1>;
56724ba675SRob Herring ranges = <0x0 0x2000 0x2000>;
57724ba675SRob Herring
58724ba675SRob Herring scm: scm@0 {
59724ba675SRob Herring compatible = "ti,dra7-scm-core", "simple-bus";
60724ba675SRob Herring reg = <0 0x2000>;
61724ba675SRob Herring #address-cells = <1>;
62724ba675SRob Herring #size-cells = <1>;
63724ba675SRob Herring ranges = <0 0 0x2000>;
64724ba675SRob Herring
65724ba675SRob Herring scm_conf: scm_conf@0 {
66724ba675SRob Herring compatible = "syscon", "simple-bus";
67724ba675SRob Herring reg = <0x0 0x1400>;
68724ba675SRob Herring #address-cells = <1>;
69724ba675SRob Herring #size-cells = <1>;
70724ba675SRob Herring ranges = <0 0x0 0x1400>;
71724ba675SRob Herring
72724ba675SRob Herring pbias_regulator: pbias_regulator@e00 {
73724ba675SRob Herring compatible = "ti,pbias-dra7", "ti,pbias-omap";
74724ba675SRob Herring reg = <0xe00 0x4>;
75724ba675SRob Herring syscon = <&scm_conf>;
76724ba675SRob Herring pbias_mmc_reg: pbias_mmc_omap5 {
77724ba675SRob Herring regulator-name = "pbias_mmc_omap5";
78724ba675SRob Herring regulator-min-microvolt = <1800000>;
79724ba675SRob Herring regulator-max-microvolt = <3300000>;
80724ba675SRob Herring };
81724ba675SRob Herring };
82724ba675SRob Herring
83*7d3c7c0aSRomain Naour phy_gmii_sel: phy-gmii-sel@554 {
84724ba675SRob Herring compatible = "ti,dra7xx-phy-gmii-sel";
85724ba675SRob Herring reg = <0x554 0x4>;
86724ba675SRob Herring #phy-cells = <1>;
87724ba675SRob Herring };
88724ba675SRob Herring
89724ba675SRob Herring scm_conf_clocks: clocks {
90724ba675SRob Herring #address-cells = <1>;
91724ba675SRob Herring #size-cells = <0>;
92724ba675SRob Herring };
93724ba675SRob Herring };
94724ba675SRob Herring
95724ba675SRob Herring dra7_pmx_core: pinmux@1400 {
96724ba675SRob Herring compatible = "ti,dra7-padconf",
97724ba675SRob Herring "pinctrl-single";
98724ba675SRob Herring reg = <0x1400 0x0468>;
99724ba675SRob Herring #address-cells = <1>;
100724ba675SRob Herring #size-cells = <0>;
101724ba675SRob Herring #pinctrl-cells = <1>;
102724ba675SRob Herring #interrupt-cells = <1>;
103724ba675SRob Herring interrupt-controller;
104724ba675SRob Herring pinctrl-single,register-width = <32>;
105724ba675SRob Herring pinctrl-single,function-mask = <0x3fffffff>;
106724ba675SRob Herring };
107724ba675SRob Herring
108724ba675SRob Herring scm_conf1: scm_conf@1c04 {
109724ba675SRob Herring compatible = "syscon";
110724ba675SRob Herring reg = <0x1c04 0x0020>;
111724ba675SRob Herring #syscon-cells = <2>;
112724ba675SRob Herring };
113724ba675SRob Herring
114724ba675SRob Herring scm_conf_pcie: scm_conf@1c24 {
115724ba675SRob Herring compatible = "syscon";
116724ba675SRob Herring reg = <0x1c24 0x0024>;
117724ba675SRob Herring };
118724ba675SRob Herring
119724ba675SRob Herring sdma_xbar: dma-router@b78 {
120724ba675SRob Herring compatible = "ti,dra7-dma-crossbar";
121724ba675SRob Herring reg = <0xb78 0xfc>;
122724ba675SRob Herring #dma-cells = <1>;
123724ba675SRob Herring dma-requests = <205>;
124724ba675SRob Herring ti,dma-safe-map = <0>;
125724ba675SRob Herring dma-masters = <&sdma>;
126724ba675SRob Herring };
127724ba675SRob Herring
128724ba675SRob Herring edma_xbar: dma-router@c78 {
129724ba675SRob Herring compatible = "ti,dra7-dma-crossbar";
130724ba675SRob Herring reg = <0xc78 0x7c>;
131724ba675SRob Herring #dma-cells = <2>;
132724ba675SRob Herring dma-requests = <204>;
133724ba675SRob Herring ti,dma-safe-map = <0>;
134724ba675SRob Herring dma-masters = <&edma>;
135724ba675SRob Herring };
136724ba675SRob Herring };
137724ba675SRob Herring };
138724ba675SRob Herring
139724ba675SRob Herring target-module@5000 { /* 0x4a005000, ap 5 10.0 */
140724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
141724ba675SRob Herring reg = <0x5000 0x4>;
142724ba675SRob Herring reg-names = "rev";
143724ba675SRob Herring #address-cells = <1>;
144724ba675SRob Herring #size-cells = <1>;
145724ba675SRob Herring ranges = <0x0 0x5000 0x1000>;
146724ba675SRob Herring
147724ba675SRob Herring cm_core_aon: cm_core_aon@0 {
148724ba675SRob Herring compatible = "ti,dra7-cm-core-aon",
149724ba675SRob Herring "simple-bus";
150724ba675SRob Herring #address-cells = <1>;
151724ba675SRob Herring #size-cells = <1>;
152724ba675SRob Herring reg = <0 0x2000>;
153724ba675SRob Herring ranges = <0 0 0x2000>;
154724ba675SRob Herring
155724ba675SRob Herring cm_core_aon_clocks: clocks {
156724ba675SRob Herring #address-cells = <1>;
157724ba675SRob Herring #size-cells = <0>;
158724ba675SRob Herring };
159724ba675SRob Herring
160724ba675SRob Herring cm_core_aon_clockdomains: clockdomains {
161724ba675SRob Herring };
162724ba675SRob Herring };
163724ba675SRob Herring };
164724ba675SRob Herring
165724ba675SRob Herring target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
166724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
167724ba675SRob Herring reg = <0x8000 0x4>;
168724ba675SRob Herring reg-names = "rev";
169724ba675SRob Herring #address-cells = <1>;
170724ba675SRob Herring #size-cells = <1>;
171724ba675SRob Herring ranges = <0x0 0x8000 0x2000>;
172724ba675SRob Herring
173724ba675SRob Herring cm_core: cm_core@0 {
174724ba675SRob Herring compatible = "ti,dra7-cm-core", "simple-bus";
175724ba675SRob Herring #address-cells = <1>;
176724ba675SRob Herring #size-cells = <1>;
177724ba675SRob Herring reg = <0 0x3000>;
178724ba675SRob Herring ranges = <0 0 0x3000>;
179724ba675SRob Herring
180724ba675SRob Herring cm_core_clocks: clocks {
181724ba675SRob Herring #address-cells = <1>;
182724ba675SRob Herring #size-cells = <0>;
183724ba675SRob Herring };
184724ba675SRob Herring
185724ba675SRob Herring cm_core_clockdomains: clockdomains {
186724ba675SRob Herring };
187724ba675SRob Herring };
188724ba675SRob Herring };
189724ba675SRob Herring
190724ba675SRob Herring target-module@56000 { /* 0x4a056000, ap 9 02.0 */
191724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
192724ba675SRob Herring reg = <0x56000 0x4>,
193724ba675SRob Herring <0x5602c 0x4>,
194724ba675SRob Herring <0x56028 0x4>;
195724ba675SRob Herring reg-names = "rev", "sysc", "syss";
196724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
197724ba675SRob Herring SYSC_OMAP2_EMUFREE |
198724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
199724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
200724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>,
201724ba675SRob Herring <SYSC_IDLE_NO>,
202724ba675SRob Herring <SYSC_IDLE_SMART>,
203724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
204724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
205724ba675SRob Herring <SYSC_IDLE_NO>,
206724ba675SRob Herring <SYSC_IDLE_SMART>,
207724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
208724ba675SRob Herring ti,syss-mask = <1>;
209724ba675SRob Herring /* Domains (P, C): core_pwrdm, dma_clkdm */
210724ba675SRob Herring clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
211724ba675SRob Herring clock-names = "fck";
212724ba675SRob Herring #address-cells = <1>;
213724ba675SRob Herring #size-cells = <1>;
214724ba675SRob Herring ranges = <0x0 0x56000 0x1000>;
215724ba675SRob Herring
216724ba675SRob Herring sdma: dma-controller@0 {
217724ba675SRob Herring compatible = "ti,omap4430-sdma", "ti,omap-sdma";
218724ba675SRob Herring reg = <0x0 0x1000>;
219724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
220724ba675SRob Herring <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
221724ba675SRob Herring <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
222724ba675SRob Herring <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
223724ba675SRob Herring #dma-cells = <1>;
224724ba675SRob Herring dma-channels = <32>;
225724ba675SRob Herring dma-requests = <127>;
226724ba675SRob Herring };
227724ba675SRob Herring };
228724ba675SRob Herring
229724ba675SRob Herring target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
230724ba675SRob Herring compatible = "ti,sysc";
231724ba675SRob Herring status = "disabled";
232724ba675SRob Herring #address-cells = <1>;
233724ba675SRob Herring #size-cells = <1>;
234724ba675SRob Herring ranges = <0x0 0x5e000 0x2000>;
235724ba675SRob Herring };
236724ba675SRob Herring
237724ba675SRob Herring target-module@80000 { /* 0x4a080000, ap 13 20.0 */
238724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
239724ba675SRob Herring reg = <0x80000 0x4>,
240724ba675SRob Herring <0x80010 0x4>,
241724ba675SRob Herring <0x80014 0x4>;
242724ba675SRob Herring reg-names = "rev", "sysc", "syss";
243724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
244724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
245724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
246724ba675SRob Herring <SYSC_IDLE_NO>,
247724ba675SRob Herring <SYSC_IDLE_SMART>;
248724ba675SRob Herring ti,syss-mask = <1>;
249724ba675SRob Herring /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
250724ba675SRob Herring clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
251724ba675SRob Herring clock-names = "fck";
252724ba675SRob Herring #address-cells = <1>;
253724ba675SRob Herring #size-cells = <1>;
254724ba675SRob Herring ranges = <0x0 0x80000 0x8000>;
255724ba675SRob Herring
256724ba675SRob Herring ocp2scp@0 {
257724ba675SRob Herring compatible = "ti,omap-ocp2scp";
258724ba675SRob Herring #address-cells = <1>;
259724ba675SRob Herring #size-cells = <1>;
260724ba675SRob Herring ranges = <0 0 0x8000>;
261724ba675SRob Herring reg = <0x0 0x20>;
262724ba675SRob Herring
263724ba675SRob Herring usb2_phy1: phy@4000 {
264724ba675SRob Herring compatible = "ti,dra7x-usb2", "ti,omap-usb2";
265724ba675SRob Herring reg = <0x4000 0x400>;
266724ba675SRob Herring syscon-phy-power = <&scm_conf 0x300>;
267724ba675SRob Herring clocks = <&usb_phy1_always_on_clk32k>,
268724ba675SRob Herring <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
269724ba675SRob Herring clock-names = "wkupclk",
270724ba675SRob Herring "refclk";
271724ba675SRob Herring #phy-cells = <0>;
272724ba675SRob Herring };
273724ba675SRob Herring
274724ba675SRob Herring usb2_phy2: phy@5000 {
275724ba675SRob Herring compatible = "ti,dra7x-usb2-phy2",
276724ba675SRob Herring "ti,omap-usb2";
277724ba675SRob Herring reg = <0x5000 0x400>;
278724ba675SRob Herring syscon-phy-power = <&scm_conf 0xe74>;
279724ba675SRob Herring clocks = <&usb_phy2_always_on_clk32k>,
280724ba675SRob Herring <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
281724ba675SRob Herring clock-names = "wkupclk",
282724ba675SRob Herring "refclk";
283724ba675SRob Herring #phy-cells = <0>;
284724ba675SRob Herring };
285724ba675SRob Herring
286724ba675SRob Herring usb3_phy1: phy@4400 {
287724ba675SRob Herring compatible = "ti,omap-usb3";
288724ba675SRob Herring reg = <0x4400 0x80>,
289724ba675SRob Herring <0x4800 0x64>,
290724ba675SRob Herring <0x4c00 0x40>;
291724ba675SRob Herring reg-names = "phy_rx", "phy_tx", "pll_ctrl";
292724ba675SRob Herring syscon-phy-power = <&scm_conf 0x370>;
293724ba675SRob Herring clocks = <&usb_phy3_always_on_clk32k>,
294724ba675SRob Herring <&sys_clkin1>,
295724ba675SRob Herring <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
296724ba675SRob Herring clock-names = "wkupclk",
297724ba675SRob Herring "sysclk",
298724ba675SRob Herring "refclk";
299724ba675SRob Herring #phy-cells = <0>;
300724ba675SRob Herring };
301724ba675SRob Herring };
302724ba675SRob Herring };
303724ba675SRob Herring
304724ba675SRob Herring target-module@90000 { /* 0x4a090000, ap 59 42.0 */
305724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
306724ba675SRob Herring reg = <0x90000 0x4>,
307724ba675SRob Herring <0x90010 0x4>,
308724ba675SRob Herring <0x90014 0x4>;
309724ba675SRob Herring reg-names = "rev", "sysc", "syss";
310724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
311724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
312724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
313724ba675SRob Herring <SYSC_IDLE_NO>,
314724ba675SRob Herring <SYSC_IDLE_SMART>;
315724ba675SRob Herring ti,syss-mask = <1>;
316724ba675SRob Herring /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
317724ba675SRob Herring clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
318724ba675SRob Herring clock-names = "fck";
319724ba675SRob Herring #address-cells = <1>;
320724ba675SRob Herring #size-cells = <1>;
321724ba675SRob Herring ranges = <0x0 0x90000 0x8000>;
322724ba675SRob Herring
323724ba675SRob Herring ocp2scp@0 {
324724ba675SRob Herring compatible = "ti,omap-ocp2scp";
325724ba675SRob Herring #address-cells = <1>;
326724ba675SRob Herring #size-cells = <1>;
327724ba675SRob Herring ranges = <0 0 0x8000>;
328724ba675SRob Herring reg = <0x0 0x20>;
329724ba675SRob Herring
330724ba675SRob Herring pcie1_phy: pciephy@4000 {
331724ba675SRob Herring compatible = "ti,phy-pipe3-pcie";
332724ba675SRob Herring reg = <0x4000 0x80>, /* phy_rx */
333724ba675SRob Herring <0x4400 0x64>; /* phy_tx */
334724ba675SRob Herring reg-names = "phy_rx", "phy_tx";
335724ba675SRob Herring syscon-phy-power = <&scm_conf_pcie 0x1c>;
336724ba675SRob Herring syscon-pcs = <&scm_conf_pcie 0x10>;
337724ba675SRob Herring clocks = <&dpll_pcie_ref_ck>,
338724ba675SRob Herring <&dpll_pcie_ref_m2ldo_ck>,
339724ba675SRob Herring <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
340724ba675SRob Herring <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
341724ba675SRob Herring <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
342724ba675SRob Herring <&optfclk_pciephy_div>,
343724ba675SRob Herring <&sys_clkin1>;
344724ba675SRob Herring clock-names = "dpll_ref", "dpll_ref_m2",
345724ba675SRob Herring "wkupclk", "refclk",
346724ba675SRob Herring "div-clk", "phy-div", "sysclk";
347724ba675SRob Herring #phy-cells = <0>;
348724ba675SRob Herring };
349724ba675SRob Herring
350724ba675SRob Herring pcie2_phy: pciephy@5000 {
351724ba675SRob Herring compatible = "ti,phy-pipe3-pcie";
352724ba675SRob Herring reg = <0x5000 0x80>, /* phy_rx */
353724ba675SRob Herring <0x5400 0x64>; /* phy_tx */
354724ba675SRob Herring reg-names = "phy_rx", "phy_tx";
355724ba675SRob Herring syscon-phy-power = <&scm_conf_pcie 0x20>;
356724ba675SRob Herring syscon-pcs = <&scm_conf_pcie 0x10>;
357724ba675SRob Herring clocks = <&dpll_pcie_ref_ck>,
358724ba675SRob Herring <&dpll_pcie_ref_m2ldo_ck>,
359724ba675SRob Herring <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
360724ba675SRob Herring <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
361724ba675SRob Herring <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
362724ba675SRob Herring <&optfclk_pciephy_div>,
363724ba675SRob Herring <&sys_clkin1>;
364724ba675SRob Herring clock-names = "dpll_ref", "dpll_ref_m2",
365724ba675SRob Herring "wkupclk", "refclk",
366724ba675SRob Herring "div-clk", "phy-div", "sysclk";
367724ba675SRob Herring #phy-cells = <0>;
368724ba675SRob Herring status = "disabled";
369724ba675SRob Herring };
370724ba675SRob Herring
371724ba675SRob Herring sata_phy: phy@6000 {
372724ba675SRob Herring compatible = "ti,phy-pipe3-sata";
373724ba675SRob Herring reg = <0x6000 0x80>, /* phy_rx */
374724ba675SRob Herring <0x6400 0x64>, /* phy_tx */
375724ba675SRob Herring <0x6800 0x40>; /* pll_ctrl */
376724ba675SRob Herring reg-names = "phy_rx", "phy_tx", "pll_ctrl";
377724ba675SRob Herring syscon-phy-power = <&scm_conf 0x374>;
378724ba675SRob Herring clocks = <&sys_clkin1>,
379724ba675SRob Herring <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
380724ba675SRob Herring clock-names = "sysclk", "refclk";
381724ba675SRob Herring syscon-pllreset = <&scm_conf 0x3fc>;
382724ba675SRob Herring #phy-cells = <0>;
383724ba675SRob Herring };
384724ba675SRob Herring };
385724ba675SRob Herring };
386724ba675SRob Herring
387724ba675SRob Herring target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
388724ba675SRob Herring compatible = "ti,sysc";
389724ba675SRob Herring status = "disabled";
390724ba675SRob Herring #address-cells = <1>;
391724ba675SRob Herring #size-cells = <1>;
392724ba675SRob Herring ranges = <0x0 0xa0000 0x8000>;
393724ba675SRob Herring };
394724ba675SRob Herring
395724ba675SRob Herring target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
396724ba675SRob Herring compatible = "ti,sysc-omap4-sr", "ti,sysc";
397724ba675SRob Herring reg = <0xd9038 0x4>;
398724ba675SRob Herring reg-names = "sysc";
399724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
400724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
401724ba675SRob Herring <SYSC_IDLE_NO>,
402724ba675SRob Herring <SYSC_IDLE_SMART>,
403724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
404724ba675SRob Herring /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
405724ba675SRob Herring clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
406724ba675SRob Herring clock-names = "fck";
407724ba675SRob Herring #address-cells = <1>;
408724ba675SRob Herring #size-cells = <1>;
409724ba675SRob Herring ranges = <0x0 0xd9000 0x1000>;
410724ba675SRob Herring
411724ba675SRob Herring /* SmartReflex child device marked reserved in TRM */
412724ba675SRob Herring };
413724ba675SRob Herring
414724ba675SRob Herring target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
415724ba675SRob Herring compatible = "ti,sysc-omap4-sr", "ti,sysc";
416724ba675SRob Herring reg = <0xdd038 0x4>;
417724ba675SRob Herring reg-names = "sysc";
418724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
419724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
420724ba675SRob Herring <SYSC_IDLE_NO>,
421724ba675SRob Herring <SYSC_IDLE_SMART>,
422724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
423724ba675SRob Herring /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
424724ba675SRob Herring clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
425724ba675SRob Herring clock-names = "fck";
426724ba675SRob Herring #address-cells = <1>;
427724ba675SRob Herring #size-cells = <1>;
428724ba675SRob Herring ranges = <0x0 0xdd000 0x1000>;
429724ba675SRob Herring
430724ba675SRob Herring /* SmartReflex child device marked reserved in TRM */
431724ba675SRob Herring };
432724ba675SRob Herring
433724ba675SRob Herring target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
434724ba675SRob Herring compatible = "ti,sysc";
435724ba675SRob Herring status = "disabled";
436724ba675SRob Herring #address-cells = <1>;
437724ba675SRob Herring #size-cells = <1>;
438724ba675SRob Herring ranges = <0x0 0xe0000 0x1000>;
439724ba675SRob Herring };
440724ba675SRob Herring
441724ba675SRob Herring target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
442724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
443724ba675SRob Herring reg = <0xf4000 0x4>,
444724ba675SRob Herring <0xf4010 0x4>;
445724ba675SRob Herring reg-names = "rev", "sysc";
446724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
447724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
448724ba675SRob Herring <SYSC_IDLE_NO>,
449724ba675SRob Herring <SYSC_IDLE_SMART>;
450724ba675SRob Herring /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
451724ba675SRob Herring clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
452724ba675SRob Herring clock-names = "fck";
453724ba675SRob Herring #address-cells = <1>;
454724ba675SRob Herring #size-cells = <1>;
455724ba675SRob Herring ranges = <0x0 0xf4000 0x1000>;
456724ba675SRob Herring
457724ba675SRob Herring mailbox1: mailbox@0 {
458724ba675SRob Herring compatible = "ti,omap4-mailbox";
459724ba675SRob Herring reg = <0x0 0x200>;
460724ba675SRob Herring interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
461724ba675SRob Herring <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
462724ba675SRob Herring <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
463724ba675SRob Herring #mbox-cells = <1>;
464724ba675SRob Herring ti,mbox-num-users = <3>;
465724ba675SRob Herring ti,mbox-num-fifos = <8>;
466724ba675SRob Herring status = "disabled";
467724ba675SRob Herring };
468724ba675SRob Herring };
469724ba675SRob Herring
470724ba675SRob Herring target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
471724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
472724ba675SRob Herring reg = <0xf6000 0x4>,
473724ba675SRob Herring <0xf6010 0x4>,
474724ba675SRob Herring <0xf6014 0x4>;
475724ba675SRob Herring reg-names = "rev", "sysc", "syss";
476724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
477724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
478724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
479724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
480724ba675SRob Herring <SYSC_IDLE_NO>,
481724ba675SRob Herring <SYSC_IDLE_SMART>;
482724ba675SRob Herring ti,syss-mask = <1>;
483724ba675SRob Herring /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
484724ba675SRob Herring clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
485724ba675SRob Herring clock-names = "fck";
486724ba675SRob Herring #address-cells = <1>;
487724ba675SRob Herring #size-cells = <1>;
488724ba675SRob Herring ranges = <0x0 0xf6000 0x1000>;
489724ba675SRob Herring
490724ba675SRob Herring hwspinlock: spinlock@0 {
491724ba675SRob Herring compatible = "ti,omap4-hwspinlock";
492724ba675SRob Herring reg = <0x0 0x1000>;
493724ba675SRob Herring #hwlock-cells = <1>;
494724ba675SRob Herring };
495724ba675SRob Herring };
496724ba675SRob Herring };
497724ba675SRob Herring
498724ba675SRob Herring segment@100000 { /* 0x4a100000 */
499724ba675SRob Herring compatible = "simple-pm-bus";
500724ba675SRob Herring #address-cells = <1>;
501724ba675SRob Herring #size-cells = <1>;
502724ba675SRob Herring ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
503724ba675SRob Herring <0x00003000 0x00103000 0x001000>, /* ap 28 */
504724ba675SRob Herring <0x00008000 0x00108000 0x001000>, /* ap 29 */
505724ba675SRob Herring <0x00009000 0x00109000 0x001000>, /* ap 30 */
506724ba675SRob Herring <0x00040000 0x00140000 0x010000>, /* ap 31 */
507724ba675SRob Herring <0x00050000 0x00150000 0x001000>, /* ap 32 */
508724ba675SRob Herring <0x00051000 0x00151000 0x001000>, /* ap 33 */
509724ba675SRob Herring <0x00052000 0x00152000 0x001000>, /* ap 34 */
510724ba675SRob Herring <0x00053000 0x00153000 0x001000>, /* ap 35 */
511724ba675SRob Herring <0x00054000 0x00154000 0x001000>, /* ap 36 */
512724ba675SRob Herring <0x00055000 0x00155000 0x001000>, /* ap 37 */
513724ba675SRob Herring <0x00056000 0x00156000 0x001000>, /* ap 38 */
514724ba675SRob Herring <0x00057000 0x00157000 0x001000>, /* ap 39 */
515724ba675SRob Herring <0x00058000 0x00158000 0x001000>, /* ap 40 */
516724ba675SRob Herring <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
517724ba675SRob Herring <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
518724ba675SRob Herring <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
519724ba675SRob Herring <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
520724ba675SRob Herring <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
521724ba675SRob Herring <0x00060000 0x00160000 0x001000>, /* ap 48 */
522724ba675SRob Herring <0x00061000 0x00161000 0x001000>, /* ap 49 */
523724ba675SRob Herring <0x00062000 0x00162000 0x001000>, /* ap 50 */
524724ba675SRob Herring <0x00063000 0x00163000 0x001000>, /* ap 51 */
525724ba675SRob Herring <0x00064000 0x00164000 0x001000>, /* ap 52 */
526724ba675SRob Herring <0x00065000 0x00165000 0x001000>, /* ap 53 */
527724ba675SRob Herring <0x00066000 0x00166000 0x001000>, /* ap 54 */
528724ba675SRob Herring <0x00067000 0x00167000 0x001000>, /* ap 55 */
529724ba675SRob Herring <0x00068000 0x00168000 0x001000>, /* ap 56 */
530724ba675SRob Herring <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
531724ba675SRob Herring <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
532724ba675SRob Herring <0x00071000 0x00171000 0x001000>, /* ap 61 */
533724ba675SRob Herring <0x00072000 0x00172000 0x001000>, /* ap 62 */
534724ba675SRob Herring <0x00073000 0x00173000 0x001000>, /* ap 63 */
535724ba675SRob Herring <0x00074000 0x00174000 0x001000>, /* ap 64 */
536724ba675SRob Herring <0x00075000 0x00175000 0x001000>, /* ap 65 */
537724ba675SRob Herring <0x00076000 0x00176000 0x001000>, /* ap 66 */
538724ba675SRob Herring <0x00077000 0x00177000 0x001000>, /* ap 67 */
539724ba675SRob Herring <0x00078000 0x00178000 0x001000>, /* ap 68 */
540724ba675SRob Herring <0x00081000 0x00181000 0x001000>, /* ap 69 */
541724ba675SRob Herring <0x00082000 0x00182000 0x001000>, /* ap 70 */
542724ba675SRob Herring <0x00083000 0x00183000 0x001000>, /* ap 71 */
543724ba675SRob Herring <0x00084000 0x00184000 0x001000>, /* ap 72 */
544724ba675SRob Herring <0x00085000 0x00185000 0x001000>, /* ap 73 */
545724ba675SRob Herring <0x00086000 0x00186000 0x001000>, /* ap 74 */
546724ba675SRob Herring <0x00087000 0x00187000 0x001000>, /* ap 75 */
547724ba675SRob Herring <0x00088000 0x00188000 0x001000>, /* ap 76 */
548724ba675SRob Herring <0x00069000 0x00169000 0x001000>, /* ap 103 */
549724ba675SRob Herring <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
550724ba675SRob Herring <0x00079000 0x00179000 0x001000>, /* ap 105 */
551724ba675SRob Herring <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
552724ba675SRob Herring <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
553724ba675SRob Herring <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
554724ba675SRob Herring <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
555724ba675SRob Herring <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
556724ba675SRob Herring <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
557724ba675SRob Herring <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
558724ba675SRob Herring <0x00059000 0x00159000 0x001000>, /* ap 125 */
559724ba675SRob Herring <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
560724ba675SRob Herring
561724ba675SRob Herring target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
562724ba675SRob Herring compatible = "ti,sysc";
563724ba675SRob Herring status = "disabled";
564724ba675SRob Herring #address-cells = <1>;
565724ba675SRob Herring #size-cells = <1>;
566724ba675SRob Herring ranges = <0x0 0x2000 0x1000>;
567724ba675SRob Herring };
568724ba675SRob Herring
569724ba675SRob Herring target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
570724ba675SRob Herring compatible = "ti,sysc";
571724ba675SRob Herring status = "disabled";
572724ba675SRob Herring #address-cells = <1>;
573724ba675SRob Herring #size-cells = <1>;
574724ba675SRob Herring ranges = <0x0 0x8000 0x1000>;
575724ba675SRob Herring };
576724ba675SRob Herring
577724ba675SRob Herring target-module@40000 { /* 0x4a140000, ap 31 06.0 */
578724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
579724ba675SRob Herring reg = <0x400fc 4>,
580724ba675SRob Herring <0x41100 4>;
581724ba675SRob Herring reg-names = "rev", "sysc";
582724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>,
583724ba675SRob Herring <SYSC_IDLE_NO>,
584724ba675SRob Herring <SYSC_IDLE_SMART>;
585724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
586724ba675SRob Herring <SYSC_IDLE_NO>,
587724ba675SRob Herring <SYSC_IDLE_SMART>,
588724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
589724ba675SRob Herring power-domains = <&prm_l3init>;
590724ba675SRob Herring clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;
591724ba675SRob Herring clock-names = "fck";
592724ba675SRob Herring #size-cells = <1>;
593724ba675SRob Herring #address-cells = <1>;
594724ba675SRob Herring ranges = <0x0 0x40000 0x10000>;
595724ba675SRob Herring
596724ba675SRob Herring sata: sata@0 {
597724ba675SRob Herring compatible = "snps,dwc-ahci";
598724ba675SRob Herring reg = <0 0x1100>, <0x1100 0x8>;
599724ba675SRob Herring interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
600724ba675SRob Herring phys = <&sata_phy>;
601724ba675SRob Herring phy-names = "sata-phy";
602724ba675SRob Herring clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
603724ba675SRob Herring ports-implemented = <0x1>;
604724ba675SRob Herring };
605724ba675SRob Herring };
606724ba675SRob Herring
607724ba675SRob Herring target-module@51000 { /* 0x4a151000, ap 33 50.0 */
608724ba675SRob Herring compatible = "ti,sysc";
609724ba675SRob Herring status = "disabled";
610724ba675SRob Herring #address-cells = <1>;
611724ba675SRob Herring #size-cells = <1>;
612724ba675SRob Herring ranges = <0x0 0x51000 0x1000>;
613724ba675SRob Herring };
614724ba675SRob Herring
615724ba675SRob Herring target-module@53000 { /* 0x4a153000, ap 35 54.0 */
616724ba675SRob Herring compatible = "ti,sysc";
617724ba675SRob Herring status = "disabled";
618724ba675SRob Herring #address-cells = <1>;
619724ba675SRob Herring #size-cells = <1>;
620724ba675SRob Herring ranges = <0x0 0x53000 0x1000>;
621724ba675SRob Herring };
622724ba675SRob Herring
623724ba675SRob Herring target-module@55000 { /* 0x4a155000, ap 37 46.0 */
624724ba675SRob Herring compatible = "ti,sysc";
625724ba675SRob Herring status = "disabled";
626724ba675SRob Herring #address-cells = <1>;
627724ba675SRob Herring #size-cells = <1>;
628724ba675SRob Herring ranges = <0x0 0x55000 0x1000>;
629724ba675SRob Herring };
630724ba675SRob Herring
631724ba675SRob Herring target-module@57000 { /* 0x4a157000, ap 39 58.0 */
632724ba675SRob Herring compatible = "ti,sysc";
633724ba675SRob Herring status = "disabled";
634724ba675SRob Herring #address-cells = <1>;
635724ba675SRob Herring #size-cells = <1>;
636724ba675SRob Herring ranges = <0x0 0x57000 0x1000>;
637724ba675SRob Herring };
638724ba675SRob Herring
639724ba675SRob Herring target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
640724ba675SRob Herring compatible = "ti,sysc";
641724ba675SRob Herring status = "disabled";
642724ba675SRob Herring #address-cells = <1>;
643724ba675SRob Herring #size-cells = <1>;
644724ba675SRob Herring ranges = <0x0 0x59000 0x1000>;
645724ba675SRob Herring };
646724ba675SRob Herring
647724ba675SRob Herring target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
648724ba675SRob Herring compatible = "ti,sysc";
649724ba675SRob Herring status = "disabled";
650724ba675SRob Herring #address-cells = <1>;
651724ba675SRob Herring #size-cells = <1>;
652724ba675SRob Herring ranges = <0x0 0x5b000 0x1000>;
653724ba675SRob Herring };
654724ba675SRob Herring
655724ba675SRob Herring target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
656724ba675SRob Herring compatible = "ti,sysc";
657724ba675SRob Herring status = "disabled";
658724ba675SRob Herring #address-cells = <1>;
659724ba675SRob Herring #size-cells = <1>;
660724ba675SRob Herring ranges = <0x0 0x5d000 0x1000>;
661724ba675SRob Herring };
662724ba675SRob Herring
663724ba675SRob Herring target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
664724ba675SRob Herring compatible = "ti,sysc";
665724ba675SRob Herring status = "disabled";
666724ba675SRob Herring #address-cells = <1>;
667724ba675SRob Herring #size-cells = <1>;
668724ba675SRob Herring ranges = <0x0 0x5f000 0x1000>;
669724ba675SRob Herring };
670724ba675SRob Herring
671724ba675SRob Herring target-module@61000 { /* 0x4a161000, ap 49 32.0 */
672724ba675SRob Herring compatible = "ti,sysc";
673724ba675SRob Herring status = "disabled";
674724ba675SRob Herring #address-cells = <1>;
675724ba675SRob Herring #size-cells = <1>;
676724ba675SRob Herring ranges = <0x0 0x61000 0x1000>;
677724ba675SRob Herring };
678724ba675SRob Herring
679724ba675SRob Herring target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
680724ba675SRob Herring compatible = "ti,sysc";
681724ba675SRob Herring status = "disabled";
682724ba675SRob Herring #address-cells = <1>;
683724ba675SRob Herring #size-cells = <1>;
684724ba675SRob Herring ranges = <0x0 0x63000 0x1000>;
685724ba675SRob Herring };
686724ba675SRob Herring
687724ba675SRob Herring target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
688724ba675SRob Herring compatible = "ti,sysc";
689724ba675SRob Herring status = "disabled";
690724ba675SRob Herring #address-cells = <1>;
691724ba675SRob Herring #size-cells = <1>;
692724ba675SRob Herring ranges = <0x0 0x65000 0x1000>;
693724ba675SRob Herring };
694724ba675SRob Herring
695724ba675SRob Herring target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
696724ba675SRob Herring compatible = "ti,sysc";
697724ba675SRob Herring status = "disabled";
698724ba675SRob Herring #address-cells = <1>;
699724ba675SRob Herring #size-cells = <1>;
700724ba675SRob Herring ranges = <0x0 0x67000 0x1000>;
701724ba675SRob Herring };
702724ba675SRob Herring
703724ba675SRob Herring target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
704724ba675SRob Herring compatible = "ti,sysc";
705724ba675SRob Herring status = "disabled";
706724ba675SRob Herring #address-cells = <1>;
707724ba675SRob Herring #size-cells = <1>;
708724ba675SRob Herring ranges = <0x0 0x69000 0x1000>;
709724ba675SRob Herring };
710724ba675SRob Herring
711724ba675SRob Herring target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
712724ba675SRob Herring compatible = "ti,sysc";
713724ba675SRob Herring status = "disabled";
714724ba675SRob Herring #address-cells = <1>;
715724ba675SRob Herring #size-cells = <1>;
716724ba675SRob Herring ranges = <0x0 0x6b000 0x1000>;
717724ba675SRob Herring };
718724ba675SRob Herring
719724ba675SRob Herring target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
720724ba675SRob Herring compatible = "ti,sysc";
721724ba675SRob Herring status = "disabled";
722724ba675SRob Herring #address-cells = <1>;
723724ba675SRob Herring #size-cells = <1>;
724724ba675SRob Herring ranges = <0x0 0x6d000 0x1000>;
725724ba675SRob Herring };
726724ba675SRob Herring
727724ba675SRob Herring target-module@71000 { /* 0x4a171000, ap 61 48.0 */
728724ba675SRob Herring compatible = "ti,sysc";
729724ba675SRob Herring status = "disabled";
730724ba675SRob Herring #address-cells = <1>;
731724ba675SRob Herring #size-cells = <1>;
732724ba675SRob Herring ranges = <0x0 0x71000 0x1000>;
733724ba675SRob Herring };
734724ba675SRob Herring
735724ba675SRob Herring target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
736724ba675SRob Herring compatible = "ti,sysc";
737724ba675SRob Herring status = "disabled";
738724ba675SRob Herring #address-cells = <1>;
739724ba675SRob Herring #size-cells = <1>;
740724ba675SRob Herring ranges = <0x0 0x73000 0x1000>;
741724ba675SRob Herring };
742724ba675SRob Herring
743724ba675SRob Herring target-module@75000 { /* 0x4a175000, ap 65 64.0 */
744724ba675SRob Herring compatible = "ti,sysc";
745724ba675SRob Herring status = "disabled";
746724ba675SRob Herring #address-cells = <1>;
747724ba675SRob Herring #size-cells = <1>;
748724ba675SRob Herring ranges = <0x0 0x75000 0x1000>;
749724ba675SRob Herring };
750724ba675SRob Herring
751724ba675SRob Herring target-module@77000 { /* 0x4a177000, ap 67 66.0 */
752724ba675SRob Herring compatible = "ti,sysc";
753724ba675SRob Herring status = "disabled";
754724ba675SRob Herring #address-cells = <1>;
755724ba675SRob Herring #size-cells = <1>;
756724ba675SRob Herring ranges = <0x0 0x77000 0x1000>;
757724ba675SRob Herring };
758724ba675SRob Herring
759724ba675SRob Herring target-module@79000 { /* 0x4a179000, ap 105 34.0 */
760724ba675SRob Herring compatible = "ti,sysc";
761724ba675SRob Herring status = "disabled";
762724ba675SRob Herring #address-cells = <1>;
763724ba675SRob Herring #size-cells = <1>;
764724ba675SRob Herring ranges = <0x0 0x79000 0x1000>;
765724ba675SRob Herring };
766724ba675SRob Herring
767724ba675SRob Herring target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
768724ba675SRob Herring compatible = "ti,sysc";
769724ba675SRob Herring status = "disabled";
770724ba675SRob Herring #address-cells = <1>;
771724ba675SRob Herring #size-cells = <1>;
772724ba675SRob Herring ranges = <0x0 0x7b000 0x1000>;
773724ba675SRob Herring };
774724ba675SRob Herring
775724ba675SRob Herring target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
776724ba675SRob Herring compatible = "ti,sysc";
777724ba675SRob Herring status = "disabled";
778724ba675SRob Herring #address-cells = <1>;
779724ba675SRob Herring #size-cells = <1>;
780724ba675SRob Herring ranges = <0x0 0x7d000 0x1000>;
781724ba675SRob Herring };
782724ba675SRob Herring
783724ba675SRob Herring target-module@81000 { /* 0x4a181000, ap 69 26.0 */
784724ba675SRob Herring compatible = "ti,sysc";
785724ba675SRob Herring status = "disabled";
786724ba675SRob Herring #address-cells = <1>;
787724ba675SRob Herring #size-cells = <1>;
788724ba675SRob Herring ranges = <0x0 0x81000 0x1000>;
789724ba675SRob Herring };
790724ba675SRob Herring
791724ba675SRob Herring target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
792724ba675SRob Herring compatible = "ti,sysc";
793724ba675SRob Herring status = "disabled";
794724ba675SRob Herring #address-cells = <1>;
795724ba675SRob Herring #size-cells = <1>;
796724ba675SRob Herring ranges = <0x0 0x83000 0x1000>;
797724ba675SRob Herring };
798724ba675SRob Herring
799724ba675SRob Herring target-module@85000 { /* 0x4a185000, ap 73 36.0 */
800724ba675SRob Herring compatible = "ti,sysc";
801724ba675SRob Herring status = "disabled";
802724ba675SRob Herring #address-cells = <1>;
803724ba675SRob Herring #size-cells = <1>;
804724ba675SRob Herring ranges = <0x0 0x85000 0x1000>;
805724ba675SRob Herring };
806724ba675SRob Herring
807724ba675SRob Herring target-module@87000 { /* 0x4a187000, ap 75 74.0 */
808724ba675SRob Herring compatible = "ti,sysc";
809724ba675SRob Herring status = "disabled";
810724ba675SRob Herring #address-cells = <1>;
811724ba675SRob Herring #size-cells = <1>;
812724ba675SRob Herring ranges = <0x0 0x87000 0x1000>;
813724ba675SRob Herring };
814724ba675SRob Herring };
815724ba675SRob Herring
816724ba675SRob Herring segment@200000 { /* 0x4a200000 */
817724ba675SRob Herring compatible = "simple-pm-bus";
818724ba675SRob Herring #address-cells = <1>;
819724ba675SRob Herring #size-cells = <1>;
820724ba675SRob Herring ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
821724ba675SRob Herring <0x00019000 0x00219000 0x001000>, /* ap 44 */
822724ba675SRob Herring <0x00000000 0x00200000 0x001000>, /* ap 77 */
823724ba675SRob Herring <0x00001000 0x00201000 0x001000>, /* ap 78 */
824724ba675SRob Herring <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
825724ba675SRob Herring <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
826724ba675SRob Herring <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
827724ba675SRob Herring <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
828724ba675SRob Herring <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
829724ba675SRob Herring <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
830724ba675SRob Herring <0x00010000 0x00210000 0x001000>, /* ap 85 */
831724ba675SRob Herring <0x00011000 0x00211000 0x001000>, /* ap 86 */
832724ba675SRob Herring <0x00012000 0x00212000 0x001000>, /* ap 87 */
833724ba675SRob Herring <0x00013000 0x00213000 0x001000>, /* ap 88 */
834724ba675SRob Herring <0x00014000 0x00214000 0x001000>, /* ap 89 */
835724ba675SRob Herring <0x00015000 0x00215000 0x001000>, /* ap 90 */
836724ba675SRob Herring <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
837724ba675SRob Herring <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
838724ba675SRob Herring <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
839724ba675SRob Herring <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
840724ba675SRob Herring <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
841724ba675SRob Herring <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
842724ba675SRob Herring <0x00020000 0x00220000 0x001000>, /* ap 97 */
843724ba675SRob Herring <0x00021000 0x00221000 0x001000>, /* ap 98 */
844724ba675SRob Herring <0x00024000 0x00224000 0x001000>, /* ap 99 */
845724ba675SRob Herring <0x00025000 0x00225000 0x001000>, /* ap 100 */
846724ba675SRob Herring <0x00026000 0x00226000 0x001000>, /* ap 101 */
847724ba675SRob Herring <0x00027000 0x00227000 0x001000>, /* ap 102 */
848724ba675SRob Herring <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
849724ba675SRob Herring <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
850724ba675SRob Herring <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
851724ba675SRob Herring <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
852724ba675SRob Herring <0x00030000 0x00230000 0x001000>, /* ap 113 */
853724ba675SRob Herring <0x00031000 0x00231000 0x001000>, /* ap 114 */
854724ba675SRob Herring <0x00032000 0x00232000 0x001000>, /* ap 115 */
855724ba675SRob Herring <0x00033000 0x00233000 0x001000>, /* ap 116 */
856724ba675SRob Herring <0x00034000 0x00234000 0x001000>, /* ap 117 */
857724ba675SRob Herring <0x00035000 0x00235000 0x001000>, /* ap 118 */
858724ba675SRob Herring <0x00036000 0x00236000 0x001000>, /* ap 119 */
859724ba675SRob Herring <0x00037000 0x00237000 0x001000>, /* ap 120 */
860724ba675SRob Herring <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
861724ba675SRob Herring <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
862724ba675SRob Herring
863724ba675SRob Herring target-module@0 { /* 0x4a200000, ap 77 3e.0 */
864724ba675SRob Herring compatible = "ti,sysc";
865724ba675SRob Herring status = "disabled";
866724ba675SRob Herring #address-cells = <1>;
867724ba675SRob Herring #size-cells = <1>;
868724ba675SRob Herring ranges = <0x0 0x0 0x1000>;
869724ba675SRob Herring };
870724ba675SRob Herring
871724ba675SRob Herring target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
872724ba675SRob Herring compatible = "ti,sysc";
873724ba675SRob Herring status = "disabled";
874724ba675SRob Herring #address-cells = <1>;
875724ba675SRob Herring #size-cells = <1>;
876724ba675SRob Herring ranges = <0x0 0xa000 0x1000>;
877724ba675SRob Herring };
878724ba675SRob Herring
879724ba675SRob Herring target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
880724ba675SRob Herring compatible = "ti,sysc";
881724ba675SRob Herring status = "disabled";
882724ba675SRob Herring #address-cells = <1>;
883724ba675SRob Herring #size-cells = <1>;
884724ba675SRob Herring ranges = <0x0 0xc000 0x1000>;
885724ba675SRob Herring };
886724ba675SRob Herring
887724ba675SRob Herring target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
888724ba675SRob Herring compatible = "ti,sysc";
889724ba675SRob Herring status = "disabled";
890724ba675SRob Herring #address-cells = <1>;
891724ba675SRob Herring #size-cells = <1>;
892724ba675SRob Herring ranges = <0x0 0xe000 0x1000>;
893724ba675SRob Herring };
894724ba675SRob Herring
895724ba675SRob Herring target-module@10000 { /* 0x4a210000, ap 85 14.0 */
896724ba675SRob Herring compatible = "ti,sysc";
897724ba675SRob Herring status = "disabled";
898724ba675SRob Herring #address-cells = <1>;
899724ba675SRob Herring #size-cells = <1>;
900724ba675SRob Herring ranges = <0x0 0x10000 0x1000>;
901724ba675SRob Herring };
902724ba675SRob Herring
903724ba675SRob Herring target-module@12000 { /* 0x4a212000, ap 87 16.0 */
904724ba675SRob Herring compatible = "ti,sysc";
905724ba675SRob Herring status = "disabled";
906724ba675SRob Herring #address-cells = <1>;
907724ba675SRob Herring #size-cells = <1>;
908724ba675SRob Herring ranges = <0x0 0x12000 0x1000>;
909724ba675SRob Herring };
910724ba675SRob Herring
911724ba675SRob Herring target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
912724ba675SRob Herring compatible = "ti,sysc";
913724ba675SRob Herring status = "disabled";
914724ba675SRob Herring #address-cells = <1>;
915724ba675SRob Herring #size-cells = <1>;
916724ba675SRob Herring ranges = <0x0 0x14000 0x1000>;
917724ba675SRob Herring };
918724ba675SRob Herring
919724ba675SRob Herring target-module@18000 { /* 0x4a218000, ap 43 12.0 */
920724ba675SRob Herring compatible = "ti,sysc";
921724ba675SRob Herring status = "disabled";
922724ba675SRob Herring #address-cells = <1>;
923724ba675SRob Herring #size-cells = <1>;
924724ba675SRob Herring ranges = <0x0 0x18000 0x1000>;
925724ba675SRob Herring };
926724ba675SRob Herring
927724ba675SRob Herring target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
928724ba675SRob Herring compatible = "ti,sysc";
929724ba675SRob Herring status = "disabled";
930724ba675SRob Herring #address-cells = <1>;
931724ba675SRob Herring #size-cells = <1>;
932724ba675SRob Herring ranges = <0x0 0x1a000 0x1000>;
933724ba675SRob Herring };
934724ba675SRob Herring
935724ba675SRob Herring target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
936724ba675SRob Herring compatible = "ti,sysc";
937724ba675SRob Herring status = "disabled";
938724ba675SRob Herring #address-cells = <1>;
939724ba675SRob Herring #size-cells = <1>;
940724ba675SRob Herring ranges = <0x0 0x1c000 0x1000>;
941724ba675SRob Herring };
942724ba675SRob Herring
943724ba675SRob Herring target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
944724ba675SRob Herring compatible = "ti,sysc";
945724ba675SRob Herring status = "disabled";
946724ba675SRob Herring #address-cells = <1>;
947724ba675SRob Herring #size-cells = <1>;
948724ba675SRob Herring ranges = <0x0 0x1e000 0x1000>;
949724ba675SRob Herring };
950724ba675SRob Herring
951724ba675SRob Herring target-module@20000 { /* 0x4a220000, ap 97 24.0 */
952724ba675SRob Herring compatible = "ti,sysc";
953724ba675SRob Herring status = "disabled";
954724ba675SRob Herring #address-cells = <1>;
955724ba675SRob Herring #size-cells = <1>;
956724ba675SRob Herring ranges = <0x0 0x20000 0x1000>;
957724ba675SRob Herring };
958724ba675SRob Herring
959724ba675SRob Herring target-module@24000 { /* 0x4a224000, ap 99 44.0 */
960724ba675SRob Herring compatible = "ti,sysc";
961724ba675SRob Herring status = "disabled";
962724ba675SRob Herring #address-cells = <1>;
963724ba675SRob Herring #size-cells = <1>;
964724ba675SRob Herring ranges = <0x0 0x24000 0x1000>;
965724ba675SRob Herring };
966724ba675SRob Herring
967724ba675SRob Herring target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
968724ba675SRob Herring compatible = "ti,sysc";
969724ba675SRob Herring status = "disabled";
970724ba675SRob Herring #address-cells = <1>;
971724ba675SRob Herring #size-cells = <1>;
972724ba675SRob Herring ranges = <0x0 0x26000 0x1000>;
973724ba675SRob Herring };
974724ba675SRob Herring
975724ba675SRob Herring target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
976724ba675SRob Herring compatible = "ti,sysc";
977724ba675SRob Herring status = "disabled";
978724ba675SRob Herring #address-cells = <1>;
979724ba675SRob Herring #size-cells = <1>;
980724ba675SRob Herring ranges = <0x0 0x2a000 0x1000>;
981724ba675SRob Herring };
982724ba675SRob Herring
983724ba675SRob Herring target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
984724ba675SRob Herring compatible = "ti,sysc";
985724ba675SRob Herring status = "disabled";
986724ba675SRob Herring #address-cells = <1>;
987724ba675SRob Herring #size-cells = <1>;
988724ba675SRob Herring ranges = <0x0 0x2c000 0x1000>;
989724ba675SRob Herring };
990724ba675SRob Herring
991724ba675SRob Herring target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
992724ba675SRob Herring compatible = "ti,sysc";
993724ba675SRob Herring status = "disabled";
994724ba675SRob Herring #address-cells = <1>;
995724ba675SRob Herring #size-cells = <1>;
996724ba675SRob Herring ranges = <0x0 0x2e000 0x1000>;
997724ba675SRob Herring };
998724ba675SRob Herring
999724ba675SRob Herring target-module@30000 { /* 0x4a230000, ap 113 70.0 */
1000724ba675SRob Herring compatible = "ti,sysc";
1001724ba675SRob Herring status = "disabled";
1002724ba675SRob Herring #address-cells = <1>;
1003724ba675SRob Herring #size-cells = <1>;
1004724ba675SRob Herring ranges = <0x0 0x30000 0x1000>;
1005724ba675SRob Herring };
1006724ba675SRob Herring
1007724ba675SRob Herring target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
1008724ba675SRob Herring compatible = "ti,sysc";
1009724ba675SRob Herring status = "disabled";
1010724ba675SRob Herring #address-cells = <1>;
1011724ba675SRob Herring #size-cells = <1>;
1012724ba675SRob Herring ranges = <0x0 0x32000 0x1000>;
1013724ba675SRob Herring };
1014724ba675SRob Herring
1015724ba675SRob Herring target-module@34000 { /* 0x4a234000, ap 117 76.1 */
1016724ba675SRob Herring compatible = "ti,sysc";
1017724ba675SRob Herring status = "disabled";
1018724ba675SRob Herring #address-cells = <1>;
1019724ba675SRob Herring #size-cells = <1>;
1020724ba675SRob Herring ranges = <0x0 0x34000 0x1000>;
1021724ba675SRob Herring };
1022724ba675SRob Herring
1023724ba675SRob Herring target-module@36000 { /* 0x4a236000, ap 119 62.0 */
1024724ba675SRob Herring compatible = "ti,sysc";
1025724ba675SRob Herring status = "disabled";
1026724ba675SRob Herring #address-cells = <1>;
1027724ba675SRob Herring #size-cells = <1>;
1028724ba675SRob Herring ranges = <0x0 0x36000 0x1000>;
1029724ba675SRob Herring };
1030724ba675SRob Herring };
1031724ba675SRob Herring};
1032724ba675SRob Herring
1033724ba675SRob Herring&l4_per1 { /* 0x48000000 */
1034724ba675SRob Herring compatible = "ti,dra7-l4-per1", "simple-pm-bus";
1035724ba675SRob Herring power-domains = <&prm_l4per>;
1036724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>;
1037724ba675SRob Herring clock-names = "fck";
1038724ba675SRob Herring reg = <0x48000000 0x800>,
1039724ba675SRob Herring <0x48000800 0x800>,
1040724ba675SRob Herring <0x48001000 0x400>,
1041724ba675SRob Herring <0x48001400 0x400>,
1042724ba675SRob Herring <0x48001800 0x400>,
1043724ba675SRob Herring <0x48001c00 0x400>;
1044724ba675SRob Herring reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1045724ba675SRob Herring #address-cells = <1>;
1046724ba675SRob Herring #size-cells = <1>;
1047724ba675SRob Herring ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1048724ba675SRob Herring <0x00200000 0x48200000 0x200000>; /* segment 1 */
1049724ba675SRob Herring
1050724ba675SRob Herring segment@0 { /* 0x48000000 */
1051724ba675SRob Herring compatible = "simple-pm-bus";
1052724ba675SRob Herring #address-cells = <1>;
1053724ba675SRob Herring #size-cells = <1>;
1054724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1055724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 1 */
1056724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 2 */
1057724ba675SRob Herring <0x00020000 0x00020000 0x001000>, /* ap 3 */
1058724ba675SRob Herring <0x00021000 0x00021000 0x001000>, /* ap 4 */
1059724ba675SRob Herring <0x00032000 0x00032000 0x001000>, /* ap 5 */
1060724ba675SRob Herring <0x00033000 0x00033000 0x001000>, /* ap 6 */
1061724ba675SRob Herring <0x00034000 0x00034000 0x001000>, /* ap 7 */
1062724ba675SRob Herring <0x00035000 0x00035000 0x001000>, /* ap 8 */
1063724ba675SRob Herring <0x00036000 0x00036000 0x001000>, /* ap 9 */
1064724ba675SRob Herring <0x00037000 0x00037000 0x001000>, /* ap 10 */
1065724ba675SRob Herring <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1066724ba675SRob Herring <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1067724ba675SRob Herring <0x00055000 0x00055000 0x001000>, /* ap 13 */
1068724ba675SRob Herring <0x00056000 0x00056000 0x001000>, /* ap 14 */
1069724ba675SRob Herring <0x00057000 0x00057000 0x001000>, /* ap 15 */
1070724ba675SRob Herring <0x00058000 0x00058000 0x001000>, /* ap 16 */
1071724ba675SRob Herring <0x00059000 0x00059000 0x001000>, /* ap 17 */
1072724ba675SRob Herring <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1073724ba675SRob Herring <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1074724ba675SRob Herring <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1075724ba675SRob Herring <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1076724ba675SRob Herring <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1077724ba675SRob Herring <0x00060000 0x00060000 0x001000>, /* ap 23 */
1078724ba675SRob Herring <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1079724ba675SRob Herring <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1080724ba675SRob Herring <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1081724ba675SRob Herring <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1082724ba675SRob Herring <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1083724ba675SRob Herring <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1084724ba675SRob Herring <0x00070000 0x00070000 0x001000>, /* ap 30 */
1085724ba675SRob Herring <0x00071000 0x00071000 0x001000>, /* ap 31 */
1086724ba675SRob Herring <0x00072000 0x00072000 0x001000>, /* ap 32 */
1087724ba675SRob Herring <0x00073000 0x00073000 0x001000>, /* ap 33 */
1088724ba675SRob Herring <0x00061000 0x00061000 0x001000>, /* ap 34 */
1089724ba675SRob Herring <0x00053000 0x00053000 0x001000>, /* ap 35 */
1090724ba675SRob Herring <0x00054000 0x00054000 0x001000>, /* ap 36 */
1091724ba675SRob Herring <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1092724ba675SRob Herring <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1093724ba675SRob Herring <0x00078000 0x00078000 0x001000>, /* ap 39 */
1094724ba675SRob Herring <0x00079000 0x00079000 0x001000>, /* ap 40 */
1095724ba675SRob Herring <0x00086000 0x00086000 0x001000>, /* ap 41 */
1096724ba675SRob Herring <0x00087000 0x00087000 0x001000>, /* ap 42 */
1097724ba675SRob Herring <0x00088000 0x00088000 0x001000>, /* ap 43 */
1098724ba675SRob Herring <0x00089000 0x00089000 0x001000>, /* ap 44 */
1099724ba675SRob Herring <0x00051000 0x00051000 0x001000>, /* ap 45 */
1100724ba675SRob Herring <0x00052000 0x00052000 0x001000>, /* ap 46 */
1101724ba675SRob Herring <0x00098000 0x00098000 0x001000>, /* ap 47 */
1102724ba675SRob Herring <0x00099000 0x00099000 0x001000>, /* ap 48 */
1103724ba675SRob Herring <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1104724ba675SRob Herring <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1105724ba675SRob Herring <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1106724ba675SRob Herring <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1107724ba675SRob Herring <0x00068000 0x00068000 0x001000>, /* ap 53 */
1108724ba675SRob Herring <0x00069000 0x00069000 0x001000>, /* ap 54 */
1109724ba675SRob Herring <0x00090000 0x00090000 0x002000>, /* ap 55 */
1110724ba675SRob Herring <0x00092000 0x00092000 0x001000>, /* ap 56 */
1111724ba675SRob Herring <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1112724ba675SRob Herring <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1113724ba675SRob Herring <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1114724ba675SRob Herring <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1115724ba675SRob Herring <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1116724ba675SRob Herring <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1117724ba675SRob Herring <0x00066000 0x00066000 0x001000>, /* ap 63 */
1118724ba675SRob Herring <0x00067000 0x00067000 0x001000>, /* ap 64 */
1119724ba675SRob Herring <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1120724ba675SRob Herring <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1121724ba675SRob Herring <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1122724ba675SRob Herring <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1123724ba675SRob Herring <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1124724ba675SRob Herring <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1125724ba675SRob Herring <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1126724ba675SRob Herring <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1127724ba675SRob Herring <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1128724ba675SRob Herring <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1129724ba675SRob Herring <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1130724ba675SRob Herring <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1131724ba675SRob Herring <0x00001400 0x00001400 0x000400>, /* ap 77 */
1132724ba675SRob Herring <0x00001800 0x00001800 0x000400>, /* ap 78 */
1133724ba675SRob Herring <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1134724ba675SRob Herring <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1135724ba675SRob Herring <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1136724ba675SRob Herring <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1137724ba675SRob Herring <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1138724ba675SRob Herring <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1139724ba675SRob Herring
1140724ba675SRob Herring target-module@20000 { /* 0x48020000, ap 3 04.0 */
1141724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1142724ba675SRob Herring reg = <0x20050 0x4>,
1143724ba675SRob Herring <0x20054 0x4>,
1144724ba675SRob Herring <0x20058 0x4>;
1145724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1146724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1147724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1148724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1149724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1150724ba675SRob Herring <SYSC_IDLE_NO>,
1151724ba675SRob Herring <SYSC_IDLE_SMART>,
1152724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1153724ba675SRob Herring ti,syss-mask = <1>;
1154724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1155724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1156724ba675SRob Herring clock-names = "fck";
1157724ba675SRob Herring #address-cells = <1>;
1158724ba675SRob Herring #size-cells = <1>;
1159724ba675SRob Herring ranges = <0x0 0x20000 0x1000>;
1160724ba675SRob Herring
1161724ba675SRob Herring uart3: serial@0 {
1162724ba675SRob Herring compatible = "ti,dra742-uart";
1163724ba675SRob Herring reg = <0x0 0x100>;
1164724ba675SRob Herring interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1165724ba675SRob Herring clock-frequency = <48000000>;
1166724ba675SRob Herring status = "disabled";
1167724ba675SRob Herring dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1168724ba675SRob Herring dma-names = "tx", "rx";
1169724ba675SRob Herring };
1170724ba675SRob Herring };
1171724ba675SRob Herring
1172724ba675SRob Herring target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1173724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc";
1174724ba675SRob Herring reg = <0x32000 0x4>,
1175724ba675SRob Herring <0x32010 0x4>;
1176724ba675SRob Herring reg-names = "rev", "sysc";
1177724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1178724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
1179724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1180724ba675SRob Herring <SYSC_IDLE_NO>,
1181724ba675SRob Herring <SYSC_IDLE_SMART>,
1182724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1183724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1184724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1185724ba675SRob Herring clock-names = "fck";
1186724ba675SRob Herring #address-cells = <1>;
1187724ba675SRob Herring #size-cells = <1>;
1188724ba675SRob Herring ranges = <0x0 0x32000 0x1000>;
1189724ba675SRob Herring
1190724ba675SRob Herring timer2: timer@0 {
1191724ba675SRob Herring compatible = "ti,omap5430-timer";
1192724ba675SRob Herring reg = <0x0 0x80>;
1193724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;
1194724ba675SRob Herring clock-names = "fck", "timer_sys_ck";
1195724ba675SRob Herring interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1196724ba675SRob Herring };
1197724ba675SRob Herring };
1198724ba675SRob Herring
1199724ba675SRob Herring timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */
1200724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc";
1201724ba675SRob Herring reg = <0x34000 0x4>,
1202724ba675SRob Herring <0x34010 0x4>;
1203724ba675SRob Herring reg-names = "rev", "sysc";
1204724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1205724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
1206724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1207724ba675SRob Herring <SYSC_IDLE_NO>,
1208724ba675SRob Herring <SYSC_IDLE_SMART>,
1209724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1210724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1211724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1212724ba675SRob Herring clock-names = "fck";
1213724ba675SRob Herring #address-cells = <1>;
1214724ba675SRob Herring #size-cells = <1>;
1215724ba675SRob Herring ranges = <0x0 0x34000 0x1000>;
1216724ba675SRob Herring
1217724ba675SRob Herring timer3: timer@0 {
1218724ba675SRob Herring compatible = "ti,omap5430-timer";
1219724ba675SRob Herring reg = <0x0 0x80>;
1220724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;
1221724ba675SRob Herring clock-names = "fck", "timer_sys_ck";
1222724ba675SRob Herring interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1223724ba675SRob Herring };
1224724ba675SRob Herring };
1225724ba675SRob Herring
1226724ba675SRob Herring timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1227724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc";
1228724ba675SRob Herring reg = <0x36000 0x4>,
1229724ba675SRob Herring <0x36010 0x4>;
1230724ba675SRob Herring reg-names = "rev", "sysc";
1231724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1232724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
1233724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1234724ba675SRob Herring <SYSC_IDLE_NO>,
1235724ba675SRob Herring <SYSC_IDLE_SMART>,
1236724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1237724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1238724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1239724ba675SRob Herring clock-names = "fck";
1240724ba675SRob Herring #address-cells = <1>;
1241724ba675SRob Herring #size-cells = <1>;
1242724ba675SRob Herring ranges = <0x0 0x36000 0x1000>;
1243724ba675SRob Herring
1244724ba675SRob Herring timer4: timer@0 {
1245724ba675SRob Herring compatible = "ti,omap5430-timer";
1246724ba675SRob Herring reg = <0x0 0x80>;
1247724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;
1248724ba675SRob Herring clock-names = "fck", "timer_sys_ck";
1249724ba675SRob Herring interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1250724ba675SRob Herring };
1251724ba675SRob Herring };
1252724ba675SRob Herring
1253724ba675SRob Herring target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1254724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc";
1255724ba675SRob Herring reg = <0x3e000 0x4>,
1256724ba675SRob Herring <0x3e010 0x4>;
1257724ba675SRob Herring reg-names = "rev", "sysc";
1258724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1259724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
1260724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1261724ba675SRob Herring <SYSC_IDLE_NO>,
1262724ba675SRob Herring <SYSC_IDLE_SMART>,
1263724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1264724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1265724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1266724ba675SRob Herring clock-names = "fck";
1267724ba675SRob Herring #address-cells = <1>;
1268724ba675SRob Herring #size-cells = <1>;
1269724ba675SRob Herring ranges = <0x0 0x3e000 0x1000>;
1270724ba675SRob Herring
1271724ba675SRob Herring timer9: timer@0 {
1272724ba675SRob Herring compatible = "ti,omap5430-timer";
1273724ba675SRob Herring reg = <0x0 0x80>;
1274724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;
1275724ba675SRob Herring clock-names = "fck", "timer_sys_ck";
1276724ba675SRob Herring interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1277724ba675SRob Herring };
1278724ba675SRob Herring };
1279724ba675SRob Herring
1280724ba675SRob Herring gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1281724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1282724ba675SRob Herring reg = <0x51000 0x4>,
1283724ba675SRob Herring <0x51010 0x4>,
1284724ba675SRob Herring <0x51114 0x4>;
1285724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1286724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1287724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1288724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1289724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1290724ba675SRob Herring <SYSC_IDLE_NO>,
1291724ba675SRob Herring <SYSC_IDLE_SMART>,
1292724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1293724ba675SRob Herring ti,syss-mask = <1>;
1294724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1295724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1296724ba675SRob Herring <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1297724ba675SRob Herring clock-names = "fck", "dbclk";
1298724ba675SRob Herring #address-cells = <1>;
1299724ba675SRob Herring #size-cells = <1>;
1300724ba675SRob Herring ranges = <0x0 0x51000 0x1000>;
1301724ba675SRob Herring
1302724ba675SRob Herring gpio7: gpio@0 {
1303724ba675SRob Herring compatible = "ti,omap4-gpio";
1304724ba675SRob Herring reg = <0x0 0x200>;
1305724ba675SRob Herring interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1306724ba675SRob Herring gpio-controller;
1307724ba675SRob Herring #gpio-cells = <2>;
1308724ba675SRob Herring interrupt-controller;
1309724ba675SRob Herring #interrupt-cells = <2>;
1310724ba675SRob Herring };
1311724ba675SRob Herring };
1312724ba675SRob Herring
1313724ba675SRob Herring target-module@53000 { /* 0x48053000, ap 35 36.0 */
1314724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1315724ba675SRob Herring reg = <0x53000 0x4>,
1316724ba675SRob Herring <0x53010 0x4>,
1317724ba675SRob Herring <0x53114 0x4>;
1318724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1319724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1320724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1321724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1322724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1323724ba675SRob Herring <SYSC_IDLE_NO>,
1324724ba675SRob Herring <SYSC_IDLE_SMART>,
1325724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1326724ba675SRob Herring ti,syss-mask = <1>;
1327724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1328724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1329724ba675SRob Herring <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1330724ba675SRob Herring clock-names = "fck", "dbclk";
1331724ba675SRob Herring #address-cells = <1>;
1332724ba675SRob Herring #size-cells = <1>;
1333724ba675SRob Herring ranges = <0x0 0x53000 0x1000>;
1334724ba675SRob Herring
1335724ba675SRob Herring gpio8: gpio@0 {
1336724ba675SRob Herring compatible = "ti,omap4-gpio";
1337724ba675SRob Herring reg = <0x0 0x200>;
1338724ba675SRob Herring interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1339724ba675SRob Herring gpio-controller;
1340724ba675SRob Herring #gpio-cells = <2>;
1341724ba675SRob Herring interrupt-controller;
1342724ba675SRob Herring #interrupt-cells = <2>;
1343724ba675SRob Herring };
1344724ba675SRob Herring };
1345724ba675SRob Herring
1346724ba675SRob Herring gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1347724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1348724ba675SRob Herring reg = <0x55000 0x4>,
1349724ba675SRob Herring <0x55010 0x4>,
1350724ba675SRob Herring <0x55114 0x4>;
1351724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1352724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1353724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1354724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1355724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1356724ba675SRob Herring <SYSC_IDLE_NO>,
1357724ba675SRob Herring <SYSC_IDLE_SMART>,
1358724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1359724ba675SRob Herring ti,syss-mask = <1>;
1360724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1361724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1362724ba675SRob Herring <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1363724ba675SRob Herring clock-names = "fck", "dbclk";
1364724ba675SRob Herring #address-cells = <1>;
1365724ba675SRob Herring #size-cells = <1>;
1366724ba675SRob Herring ranges = <0x0 0x55000 0x1000>;
1367724ba675SRob Herring
1368724ba675SRob Herring gpio2: gpio@0 {
1369724ba675SRob Herring compatible = "ti,omap4-gpio";
1370724ba675SRob Herring reg = <0x0 0x200>;
1371724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1372724ba675SRob Herring gpio-controller;
1373724ba675SRob Herring #gpio-cells = <2>;
1374724ba675SRob Herring interrupt-controller;
1375724ba675SRob Herring #interrupt-cells = <2>;
1376724ba675SRob Herring };
1377724ba675SRob Herring };
1378724ba675SRob Herring
1379724ba675SRob Herring gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */
1380724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1381724ba675SRob Herring reg = <0x57000 0x4>,
1382724ba675SRob Herring <0x57010 0x4>,
1383724ba675SRob Herring <0x57114 0x4>;
1384724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1385724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1386724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1387724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1388724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1389724ba675SRob Herring <SYSC_IDLE_NO>,
1390724ba675SRob Herring <SYSC_IDLE_SMART>,
1391724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1392724ba675SRob Herring ti,syss-mask = <1>;
1393724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1394724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1395724ba675SRob Herring <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1396724ba675SRob Herring clock-names = "fck", "dbclk";
1397724ba675SRob Herring #address-cells = <1>;
1398724ba675SRob Herring #size-cells = <1>;
1399724ba675SRob Herring ranges = <0x0 0x57000 0x1000>;
1400724ba675SRob Herring
1401724ba675SRob Herring gpio3: gpio@0 {
1402724ba675SRob Herring compatible = "ti,omap4-gpio";
1403724ba675SRob Herring reg = <0x0 0x200>;
1404724ba675SRob Herring interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1405724ba675SRob Herring gpio-controller;
1406724ba675SRob Herring #gpio-cells = <2>;
1407724ba675SRob Herring interrupt-controller;
1408724ba675SRob Herring #interrupt-cells = <2>;
1409724ba675SRob Herring };
1410724ba675SRob Herring };
1411724ba675SRob Herring
1412724ba675SRob Herring target-module@59000 { /* 0x48059000, ap 17 16.0 */
1413724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1414724ba675SRob Herring reg = <0x59000 0x4>,
1415724ba675SRob Herring <0x59010 0x4>,
1416724ba675SRob Herring <0x59114 0x4>;
1417724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1418724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1419724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1420724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1421724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1422724ba675SRob Herring <SYSC_IDLE_NO>,
1423724ba675SRob Herring <SYSC_IDLE_SMART>,
1424724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1425724ba675SRob Herring ti,syss-mask = <1>;
1426724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1427724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1428724ba675SRob Herring <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1429724ba675SRob Herring clock-names = "fck", "dbclk";
1430724ba675SRob Herring #address-cells = <1>;
1431724ba675SRob Herring #size-cells = <1>;
1432724ba675SRob Herring ranges = <0x0 0x59000 0x1000>;
1433724ba675SRob Herring
1434724ba675SRob Herring gpio4: gpio@0 {
1435724ba675SRob Herring compatible = "ti,omap4-gpio";
1436724ba675SRob Herring reg = <0x0 0x200>;
1437724ba675SRob Herring interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1438724ba675SRob Herring gpio-controller;
1439724ba675SRob Herring #gpio-cells = <2>;
1440724ba675SRob Herring interrupt-controller;
1441724ba675SRob Herring #interrupt-cells = <2>;
1442724ba675SRob Herring };
1443724ba675SRob Herring };
1444724ba675SRob Herring
1445724ba675SRob Herring target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1446724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1447724ba675SRob Herring reg = <0x5b000 0x4>,
1448724ba675SRob Herring <0x5b010 0x4>,
1449724ba675SRob Herring <0x5b114 0x4>;
1450724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1451724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1452724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1453724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1454724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1455724ba675SRob Herring <SYSC_IDLE_NO>,
1456724ba675SRob Herring <SYSC_IDLE_SMART>,
1457724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1458724ba675SRob Herring ti,syss-mask = <1>;
1459724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1460724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1461724ba675SRob Herring <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1462724ba675SRob Herring clock-names = "fck", "dbclk";
1463724ba675SRob Herring #address-cells = <1>;
1464724ba675SRob Herring #size-cells = <1>;
1465724ba675SRob Herring ranges = <0x0 0x5b000 0x1000>;
1466724ba675SRob Herring
1467724ba675SRob Herring gpio5: gpio@0 {
1468724ba675SRob Herring compatible = "ti,omap4-gpio";
1469724ba675SRob Herring reg = <0x0 0x200>;
1470724ba675SRob Herring interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1471724ba675SRob Herring gpio-controller;
1472724ba675SRob Herring #gpio-cells = <2>;
1473724ba675SRob Herring interrupt-controller;
1474724ba675SRob Herring #interrupt-cells = <2>;
1475724ba675SRob Herring };
1476724ba675SRob Herring };
1477724ba675SRob Herring
1478724ba675SRob Herring target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1479724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1480724ba675SRob Herring reg = <0x5d000 0x4>,
1481724ba675SRob Herring <0x5d010 0x4>,
1482724ba675SRob Herring <0x5d114 0x4>;
1483724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1484724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1485724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1486724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1487724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1488724ba675SRob Herring <SYSC_IDLE_NO>,
1489724ba675SRob Herring <SYSC_IDLE_SMART>,
1490724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1491724ba675SRob Herring ti,syss-mask = <1>;
1492724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1493724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1494724ba675SRob Herring <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1495724ba675SRob Herring clock-names = "fck", "dbclk";
1496724ba675SRob Herring #address-cells = <1>;
1497724ba675SRob Herring #size-cells = <1>;
1498724ba675SRob Herring ranges = <0x0 0x5d000 0x1000>;
1499724ba675SRob Herring
1500724ba675SRob Herring gpio6: gpio@0 {
1501724ba675SRob Herring compatible = "ti,omap4-gpio";
1502724ba675SRob Herring reg = <0x0 0x200>;
1503724ba675SRob Herring interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1504724ba675SRob Herring gpio-controller;
1505724ba675SRob Herring #gpio-cells = <2>;
1506724ba675SRob Herring interrupt-controller;
1507724ba675SRob Herring #interrupt-cells = <2>;
1508724ba675SRob Herring };
1509724ba675SRob Herring };
1510724ba675SRob Herring
1511724ba675SRob Herring target-module@60000 { /* 0x48060000, ap 23 32.0 */
1512724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1513724ba675SRob Herring reg = <0x60000 0x8>,
1514724ba675SRob Herring <0x60010 0x8>,
1515724ba675SRob Herring <0x60090 0x8>;
1516724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1517724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1518724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP |
1519724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1520724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1521724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1522724ba675SRob Herring <SYSC_IDLE_NO>,
1523724ba675SRob Herring <SYSC_IDLE_SMART>,
1524724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1525724ba675SRob Herring ti,syss-mask = <1>;
1526724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1527724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1528724ba675SRob Herring clock-names = "fck";
1529724ba675SRob Herring #address-cells = <1>;
1530724ba675SRob Herring #size-cells = <1>;
1531724ba675SRob Herring ranges = <0x0 0x60000 0x1000>;
1532724ba675SRob Herring
1533724ba675SRob Herring i2c3: i2c@0 {
1534724ba675SRob Herring compatible = "ti,omap4-i2c";
1535724ba675SRob Herring reg = <0x0 0x100>;
1536724ba675SRob Herring interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1537724ba675SRob Herring #address-cells = <1>;
1538724ba675SRob Herring #size-cells = <0>;
1539724ba675SRob Herring status = "disabled";
1540724ba675SRob Herring };
1541724ba675SRob Herring };
1542724ba675SRob Herring
1543724ba675SRob Herring target-module@66000 { /* 0x48066000, ap 63 14.0 */
1544724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1545724ba675SRob Herring reg = <0x66050 0x4>,
1546724ba675SRob Herring <0x66054 0x4>,
1547724ba675SRob Herring <0x66058 0x4>;
1548724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1549724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1550724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1551724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1552724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1553724ba675SRob Herring <SYSC_IDLE_NO>,
1554724ba675SRob Herring <SYSC_IDLE_SMART>,
1555724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1556724ba675SRob Herring ti,syss-mask = <1>;
1557724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1558724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1559724ba675SRob Herring clock-names = "fck";
1560724ba675SRob Herring #address-cells = <1>;
1561724ba675SRob Herring #size-cells = <1>;
1562724ba675SRob Herring ranges = <0x0 0x66000 0x1000>;
1563724ba675SRob Herring
1564724ba675SRob Herring uart5: serial@0 {
1565724ba675SRob Herring compatible = "ti,dra742-uart";
1566724ba675SRob Herring reg = <0x0 0x100>;
1567724ba675SRob Herring interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1568724ba675SRob Herring clock-frequency = <48000000>;
1569724ba675SRob Herring status = "disabled";
1570724ba675SRob Herring dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1571724ba675SRob Herring dma-names = "tx", "rx";
1572724ba675SRob Herring };
1573724ba675SRob Herring };
1574724ba675SRob Herring
1575724ba675SRob Herring target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1576724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1577724ba675SRob Herring reg = <0x68050 0x4>,
1578724ba675SRob Herring <0x68054 0x4>,
1579724ba675SRob Herring <0x68058 0x4>;
1580724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1581724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1582724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1583724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1584724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1585724ba675SRob Herring <SYSC_IDLE_NO>,
1586724ba675SRob Herring <SYSC_IDLE_SMART>,
1587724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1588724ba675SRob Herring ti,syss-mask = <1>;
1589724ba675SRob Herring /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1590724ba675SRob Herring clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1591724ba675SRob Herring clock-names = "fck";
1592724ba675SRob Herring #address-cells = <1>;
1593724ba675SRob Herring #size-cells = <1>;
1594724ba675SRob Herring ranges = <0x0 0x68000 0x1000>;
1595724ba675SRob Herring
1596724ba675SRob Herring uart6: serial@0 {
1597724ba675SRob Herring compatible = "ti,dra742-uart";
1598724ba675SRob Herring reg = <0x0 0x100>;
1599724ba675SRob Herring interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1600724ba675SRob Herring clock-frequency = <48000000>;
1601724ba675SRob Herring status = "disabled";
1602724ba675SRob Herring dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1603724ba675SRob Herring dma-names = "tx", "rx";
1604724ba675SRob Herring };
1605724ba675SRob Herring };
1606724ba675SRob Herring
1607724ba675SRob Herring target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1608724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1609724ba675SRob Herring reg = <0x6a050 0x4>,
1610724ba675SRob Herring <0x6a054 0x4>,
1611724ba675SRob Herring <0x6a058 0x4>;
1612724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1613724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1614724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1615724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1616724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1617724ba675SRob Herring <SYSC_IDLE_NO>,
1618724ba675SRob Herring <SYSC_IDLE_SMART>,
1619724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1620724ba675SRob Herring ti,syss-mask = <1>;
1621724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1622724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1623724ba675SRob Herring clock-names = "fck";
1624724ba675SRob Herring #address-cells = <1>;
1625724ba675SRob Herring #size-cells = <1>;
1626724ba675SRob Herring ranges = <0x0 0x6a000 0x1000>;
1627724ba675SRob Herring
1628724ba675SRob Herring uart1: serial@0 {
1629724ba675SRob Herring compatible = "ti,dra742-uart";
1630724ba675SRob Herring reg = <0x0 0x100>;
1631724ba675SRob Herring interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1632724ba675SRob Herring clock-frequency = <48000000>;
1633724ba675SRob Herring status = "disabled";
1634724ba675SRob Herring dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1635724ba675SRob Herring dma-names = "tx", "rx";
1636724ba675SRob Herring };
1637724ba675SRob Herring };
1638724ba675SRob Herring
1639724ba675SRob Herring target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1640724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1641724ba675SRob Herring reg = <0x6c050 0x4>,
1642724ba675SRob Herring <0x6c054 0x4>,
1643724ba675SRob Herring <0x6c058 0x4>;
1644724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1645724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1646724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1647724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1648724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1649724ba675SRob Herring <SYSC_IDLE_NO>,
1650724ba675SRob Herring <SYSC_IDLE_SMART>,
1651724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1652724ba675SRob Herring ti,syss-mask = <1>;
1653724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1654724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1655724ba675SRob Herring clock-names = "fck";
1656724ba675SRob Herring #address-cells = <1>;
1657724ba675SRob Herring #size-cells = <1>;
1658724ba675SRob Herring ranges = <0x0 0x6c000 0x1000>;
1659724ba675SRob Herring
1660724ba675SRob Herring uart2: serial@0 {
1661724ba675SRob Herring compatible = "ti,dra742-uart";
1662724ba675SRob Herring reg = <0x0 0x100>;
1663724ba675SRob Herring interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1664724ba675SRob Herring clock-frequency = <48000000>;
1665724ba675SRob Herring status = "disabled";
1666724ba675SRob Herring dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1667724ba675SRob Herring dma-names = "tx", "rx";
1668724ba675SRob Herring };
1669724ba675SRob Herring };
1670724ba675SRob Herring
1671724ba675SRob Herring target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1672724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1673724ba675SRob Herring reg = <0x6e050 0x4>,
1674724ba675SRob Herring <0x6e054 0x4>,
1675724ba675SRob Herring <0x6e058 0x4>;
1676724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1677724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1678724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1679724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1680724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1681724ba675SRob Herring <SYSC_IDLE_NO>,
1682724ba675SRob Herring <SYSC_IDLE_SMART>,
1683724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1684724ba675SRob Herring ti,syss-mask = <1>;
1685724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1686724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1687724ba675SRob Herring clock-names = "fck";
1688724ba675SRob Herring #address-cells = <1>;
1689724ba675SRob Herring #size-cells = <1>;
1690724ba675SRob Herring ranges = <0x0 0x6e000 0x1000>;
1691724ba675SRob Herring
1692724ba675SRob Herring uart4: serial@0 {
1693724ba675SRob Herring compatible = "ti,dra742-uart";
1694724ba675SRob Herring reg = <0x0 0x100>;
1695724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1696724ba675SRob Herring clock-frequency = <48000000>;
1697724ba675SRob Herring status = "disabled";
1698724ba675SRob Herring dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1699724ba675SRob Herring dma-names = "tx", "rx";
1700724ba675SRob Herring };
1701724ba675SRob Herring };
1702724ba675SRob Herring
1703724ba675SRob Herring target-module@70000 { /* 0x48070000, ap 30 22.0 */
1704724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1705724ba675SRob Herring reg = <0x70000 0x8>,
1706724ba675SRob Herring <0x70010 0x8>,
1707724ba675SRob Herring <0x70090 0x8>;
1708724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1709724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1710724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP |
1711724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1712724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1713724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1714724ba675SRob Herring <SYSC_IDLE_NO>,
1715724ba675SRob Herring <SYSC_IDLE_SMART>,
1716724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1717724ba675SRob Herring ti,syss-mask = <1>;
1718724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1719724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1720724ba675SRob Herring clock-names = "fck";
1721724ba675SRob Herring #address-cells = <1>;
1722724ba675SRob Herring #size-cells = <1>;
1723724ba675SRob Herring ranges = <0x0 0x70000 0x1000>;
1724724ba675SRob Herring
1725724ba675SRob Herring i2c1: i2c@0 {
1726724ba675SRob Herring compatible = "ti,omap4-i2c";
1727724ba675SRob Herring reg = <0x0 0x100>;
1728724ba675SRob Herring interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1729724ba675SRob Herring #address-cells = <1>;
1730724ba675SRob Herring #size-cells = <0>;
1731724ba675SRob Herring status = "disabled";
1732724ba675SRob Herring };
1733724ba675SRob Herring };
1734724ba675SRob Herring
1735724ba675SRob Herring target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1736724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1737724ba675SRob Herring reg = <0x72000 0x8>,
1738724ba675SRob Herring <0x72010 0x8>,
1739724ba675SRob Herring <0x72090 0x8>;
1740724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1741724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1742724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP |
1743724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1744724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1745724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1746724ba675SRob Herring <SYSC_IDLE_NO>,
1747724ba675SRob Herring <SYSC_IDLE_SMART>,
1748724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1749724ba675SRob Herring ti,syss-mask = <1>;
1750724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1751724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1752724ba675SRob Herring clock-names = "fck";
1753724ba675SRob Herring #address-cells = <1>;
1754724ba675SRob Herring #size-cells = <1>;
1755724ba675SRob Herring ranges = <0x0 0x72000 0x1000>;
1756724ba675SRob Herring
1757724ba675SRob Herring i2c2: i2c@0 {
1758724ba675SRob Herring compatible = "ti,omap4-i2c";
1759724ba675SRob Herring reg = <0x0 0x100>;
1760724ba675SRob Herring interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1761724ba675SRob Herring #address-cells = <1>;
1762724ba675SRob Herring #size-cells = <0>;
1763724ba675SRob Herring status = "disabled";
1764724ba675SRob Herring };
1765724ba675SRob Herring };
1766724ba675SRob Herring
1767724ba675SRob Herring target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1768724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1769724ba675SRob Herring reg = <0x78000 0x4>,
1770724ba675SRob Herring <0x78010 0x4>,
1771724ba675SRob Herring <0x78014 0x4>;
1772724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1773724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1774724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1775724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1776724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1777724ba675SRob Herring <SYSC_IDLE_NO>,
1778724ba675SRob Herring <SYSC_IDLE_SMART>,
1779724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1780724ba675SRob Herring ti,syss-mask = <1>;
1781724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1782724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1783724ba675SRob Herring clock-names = "fck";
1784724ba675SRob Herring #address-cells = <1>;
1785724ba675SRob Herring #size-cells = <1>;
1786724ba675SRob Herring ranges = <0x0 0x78000 0x1000>;
1787724ba675SRob Herring
1788724ba675SRob Herring elm: elm@0 {
1789724ba675SRob Herring compatible = "ti,am3352-elm";
1790724ba675SRob Herring reg = <0x0 0xfc0>; /* device IO registers */
1791724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1792724ba675SRob Herring status = "disabled";
1793724ba675SRob Herring };
1794724ba675SRob Herring };
1795724ba675SRob Herring
1796724ba675SRob Herring target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1797724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1798724ba675SRob Herring reg = <0x7a000 0x8>,
1799724ba675SRob Herring <0x7a010 0x8>,
1800724ba675SRob Herring <0x7a090 0x8>;
1801724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1802724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1803724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP |
1804724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1805724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1806724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1807724ba675SRob Herring <SYSC_IDLE_NO>,
1808724ba675SRob Herring <SYSC_IDLE_SMART>,
1809724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1810724ba675SRob Herring ti,syss-mask = <1>;
1811724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1812724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1813724ba675SRob Herring clock-names = "fck";
1814724ba675SRob Herring #address-cells = <1>;
1815724ba675SRob Herring #size-cells = <1>;
1816724ba675SRob Herring ranges = <0x0 0x7a000 0x1000>;
1817724ba675SRob Herring
1818724ba675SRob Herring i2c4: i2c@0 {
1819724ba675SRob Herring compatible = "ti,omap4-i2c";
1820724ba675SRob Herring reg = <0x0 0x100>;
1821724ba675SRob Herring interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1822724ba675SRob Herring #address-cells = <1>;
1823724ba675SRob Herring #size-cells = <0>;
1824724ba675SRob Herring status = "disabled";
1825724ba675SRob Herring };
1826724ba675SRob Herring };
1827724ba675SRob Herring
1828724ba675SRob Herring target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1829724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1830724ba675SRob Herring reg = <0x7c000 0x8>,
1831724ba675SRob Herring <0x7c010 0x8>,
1832724ba675SRob Herring <0x7c090 0x8>;
1833724ba675SRob Herring reg-names = "rev", "sysc", "syss";
1834724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1835724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP |
1836724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
1837724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
1838724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1839724ba675SRob Herring <SYSC_IDLE_NO>,
1840724ba675SRob Herring <SYSC_IDLE_SMART>,
1841724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1842724ba675SRob Herring ti,syss-mask = <1>;
1843724ba675SRob Herring /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1844724ba675SRob Herring clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1845724ba675SRob Herring clock-names = "fck";
1846724ba675SRob Herring #address-cells = <1>;
1847724ba675SRob Herring #size-cells = <1>;
1848724ba675SRob Herring ranges = <0x0 0x7c000 0x1000>;
1849724ba675SRob Herring
1850724ba675SRob Herring i2c5: i2c@0 {
1851724ba675SRob Herring compatible = "ti,omap4-i2c";
1852724ba675SRob Herring reg = <0x0 0x100>;
1853724ba675SRob Herring interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1854724ba675SRob Herring #address-cells = <1>;
1855724ba675SRob Herring #size-cells = <0>;
1856724ba675SRob Herring status = "disabled";
1857724ba675SRob Herring };
1858724ba675SRob Herring };
1859724ba675SRob Herring
1860724ba675SRob Herring target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1861724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc";
1862724ba675SRob Herring reg = <0x86000 0x4>,
1863724ba675SRob Herring <0x86010 0x4>;
1864724ba675SRob Herring reg-names = "rev", "sysc";
1865724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1866724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
1867724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1868724ba675SRob Herring <SYSC_IDLE_NO>,
1869724ba675SRob Herring <SYSC_IDLE_SMART>,
1870724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1871724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1872724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1873724ba675SRob Herring clock-names = "fck";
1874724ba675SRob Herring #address-cells = <1>;
1875724ba675SRob Herring #size-cells = <1>;
1876724ba675SRob Herring ranges = <0x0 0x86000 0x1000>;
1877724ba675SRob Herring
1878724ba675SRob Herring timer10: timer@0 {
1879724ba675SRob Herring compatible = "ti,omap5430-timer";
1880724ba675SRob Herring reg = <0x0 0x80>;
1881724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;
1882724ba675SRob Herring clock-names = "fck", "timer_sys_ck";
1883724ba675SRob Herring interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1884724ba675SRob Herring };
1885724ba675SRob Herring };
1886724ba675SRob Herring
1887724ba675SRob Herring target-module@88000 { /* 0x48088000, ap 43 66.0 */
1888724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc";
1889724ba675SRob Herring reg = <0x88000 0x4>,
1890724ba675SRob Herring <0x88010 0x4>;
1891724ba675SRob Herring reg-names = "rev", "sysc";
1892724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1893724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
1894724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1895724ba675SRob Herring <SYSC_IDLE_NO>,
1896724ba675SRob Herring <SYSC_IDLE_SMART>,
1897724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1898724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1899724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1900724ba675SRob Herring clock-names = "fck";
1901724ba675SRob Herring #address-cells = <1>;
1902724ba675SRob Herring #size-cells = <1>;
1903724ba675SRob Herring ranges = <0x0 0x88000 0x1000>;
1904724ba675SRob Herring
1905724ba675SRob Herring timer11: timer@0 {
1906724ba675SRob Herring compatible = "ti,omap5430-timer";
1907724ba675SRob Herring reg = <0x0 0x80>;
1908724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;
1909724ba675SRob Herring clock-names = "fck", "timer_sys_ck";
1910724ba675SRob Herring interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1911724ba675SRob Herring };
1912724ba675SRob Herring };
1913724ba675SRob Herring
1914724ba675SRob Herring target-module@90000 { /* 0x48090000, ap 55 12.0 */
1915724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
1916724ba675SRob Herring reg = <0x91fe0 0x4>,
1917724ba675SRob Herring <0x91fe4 0x4>;
1918724ba675SRob Herring reg-names = "rev", "sysc";
1919724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1920724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1921724ba675SRob Herring <SYSC_IDLE_NO>;
1922724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1923724ba675SRob Herring clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1924724ba675SRob Herring clock-names = "fck";
1925724ba675SRob Herring #address-cells = <1>;
1926724ba675SRob Herring #size-cells = <1>;
1927724ba675SRob Herring ranges = <0x0 0x90000 0x2000>;
1928724ba675SRob Herring
1929724ba675SRob Herring rng: rng@0 {
1930724ba675SRob Herring compatible = "ti,omap4-rng";
1931724ba675SRob Herring reg = <0x0 0x2000>;
1932724ba675SRob Herring interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1933724ba675SRob Herring clocks = <&l3_iclk_div>;
1934724ba675SRob Herring clock-names = "fck";
1935724ba675SRob Herring };
1936724ba675SRob Herring };
1937724ba675SRob Herring
1938724ba675SRob Herring target-module@98000 { /* 0x48098000, ap 47 08.0 */
1939724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
1940724ba675SRob Herring reg = <0x98000 0x4>,
1941724ba675SRob Herring <0x98010 0x4>;
1942724ba675SRob Herring reg-names = "rev", "sysc";
1943724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1944724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
1945724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1946724ba675SRob Herring <SYSC_IDLE_NO>,
1947724ba675SRob Herring <SYSC_IDLE_SMART>,
1948724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1949724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1950724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1951724ba675SRob Herring clock-names = "fck";
1952724ba675SRob Herring #address-cells = <1>;
1953724ba675SRob Herring #size-cells = <1>;
1954724ba675SRob Herring ranges = <0x0 0x98000 0x1000>;
1955724ba675SRob Herring
1956724ba675SRob Herring mcspi1: spi@0 {
1957724ba675SRob Herring compatible = "ti,omap4-mcspi";
1958724ba675SRob Herring reg = <0x0 0x200>;
1959724ba675SRob Herring interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1960724ba675SRob Herring #address-cells = <1>;
1961724ba675SRob Herring #size-cells = <0>;
1962724ba675SRob Herring ti,spi-num-cs = <4>;
1963724ba675SRob Herring dmas = <&sdma_xbar 35>,
1964724ba675SRob Herring <&sdma_xbar 36>,
1965724ba675SRob Herring <&sdma_xbar 37>,
1966724ba675SRob Herring <&sdma_xbar 38>,
1967724ba675SRob Herring <&sdma_xbar 39>,
1968724ba675SRob Herring <&sdma_xbar 40>,
1969724ba675SRob Herring <&sdma_xbar 41>,
1970724ba675SRob Herring <&sdma_xbar 42>;
1971724ba675SRob Herring dma-names = "tx0", "rx0", "tx1", "rx1",
1972724ba675SRob Herring "tx2", "rx2", "tx3", "rx3";
1973724ba675SRob Herring status = "disabled";
1974724ba675SRob Herring };
1975724ba675SRob Herring };
1976724ba675SRob Herring
1977724ba675SRob Herring target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1978724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
1979724ba675SRob Herring reg = <0x9a000 0x4>,
1980724ba675SRob Herring <0x9a010 0x4>;
1981724ba675SRob Herring reg-names = "rev", "sysc";
1982724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1983724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
1984724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1985724ba675SRob Herring <SYSC_IDLE_NO>,
1986724ba675SRob Herring <SYSC_IDLE_SMART>,
1987724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
1988724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1989724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1990724ba675SRob Herring clock-names = "fck";
1991724ba675SRob Herring #address-cells = <1>;
1992724ba675SRob Herring #size-cells = <1>;
1993724ba675SRob Herring ranges = <0x0 0x9a000 0x1000>;
1994724ba675SRob Herring
1995724ba675SRob Herring mcspi2: spi@0 {
1996724ba675SRob Herring compatible = "ti,omap4-mcspi";
1997724ba675SRob Herring reg = <0x0 0x200>;
1998724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1999724ba675SRob Herring #address-cells = <1>;
2000724ba675SRob Herring #size-cells = <0>;
2001724ba675SRob Herring ti,spi-num-cs = <2>;
2002724ba675SRob Herring dmas = <&sdma_xbar 43>,
2003724ba675SRob Herring <&sdma_xbar 44>,
2004724ba675SRob Herring <&sdma_xbar 45>,
2005724ba675SRob Herring <&sdma_xbar 46>;
2006724ba675SRob Herring dma-names = "tx0", "rx0", "tx1", "rx1";
2007724ba675SRob Herring status = "disabled";
2008724ba675SRob Herring };
2009724ba675SRob Herring };
2010724ba675SRob Herring
2011724ba675SRob Herring target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
2012724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2013724ba675SRob Herring reg = <0x9c000 0x4>,
2014724ba675SRob Herring <0x9c010 0x4>;
2015724ba675SRob Herring reg-names = "rev", "sysc";
2016724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2017724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
2018724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>,
2019724ba675SRob Herring <SYSC_IDLE_NO>,
2020724ba675SRob Herring <SYSC_IDLE_SMART>,
2021724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2022724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2023724ba675SRob Herring <SYSC_IDLE_NO>,
2024724ba675SRob Herring <SYSC_IDLE_SMART>,
2025724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2026724ba675SRob Herring /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2027724ba675SRob Herring clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2028724ba675SRob Herring clock-names = "fck";
2029724ba675SRob Herring #address-cells = <1>;
2030724ba675SRob Herring #size-cells = <1>;
2031724ba675SRob Herring ranges = <0x0 0x9c000 0x1000>;
2032724ba675SRob Herring
2033724ba675SRob Herring mmc1: mmc@0 {
2034724ba675SRob Herring compatible = "ti,dra7-sdhci";
2035724ba675SRob Herring reg = <0x0 0x400>;
2036724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2037724ba675SRob Herring status = "disabled";
2038724ba675SRob Herring pbias-supply = <&pbias_mmc_reg>;
2039724ba675SRob Herring max-frequency = <192000000>;
2040724ba675SRob Herring mmc-ddr-1_8v;
2041724ba675SRob Herring mmc-ddr-3_3v;
2042724ba675SRob Herring };
2043724ba675SRob Herring };
2044724ba675SRob Herring
2045724ba675SRob Herring target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2046724ba675SRob Herring compatible = "ti,sysc";
2047724ba675SRob Herring status = "disabled";
2048724ba675SRob Herring #address-cells = <1>;
2049724ba675SRob Herring #size-cells = <1>;
2050724ba675SRob Herring ranges = <0x0 0xa2000 0x1000>;
2051724ba675SRob Herring };
2052724ba675SRob Herring
2053724ba675SRob Herring target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2054724ba675SRob Herring compatible = "ti,sysc";
2055724ba675SRob Herring status = "disabled";
2056724ba675SRob Herring #address-cells = <1>;
2057724ba675SRob Herring #size-cells = <1>;
2058724ba675SRob Herring ranges = <0x00000000 0x000a4000 0x00001000>,
2059724ba675SRob Herring <0x00001000 0x000a5000 0x00001000>;
2060724ba675SRob Herring };
2061724ba675SRob Herring
2062724ba675SRob Herring des_target: target-module@a5000 { /* 0x480a5000 */
2063724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
2064724ba675SRob Herring reg = <0xa5030 0x4>,
2065724ba675SRob Herring <0xa5034 0x4>,
2066724ba675SRob Herring <0xa5038 0x4>;
2067724ba675SRob Herring reg-names = "rev", "sysc", "syss";
2068724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2069724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
2070724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2071724ba675SRob Herring <SYSC_IDLE_NO>,
2072724ba675SRob Herring <SYSC_IDLE_SMART>,
2073724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2074724ba675SRob Herring ti,syss-mask = <1>;
2075724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
2076724ba675SRob Herring clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2077724ba675SRob Herring clock-names = "fck";
2078724ba675SRob Herring #address-cells = <1>;
2079724ba675SRob Herring #size-cells = <1>;
2080724ba675SRob Herring ranges = <0 0xa5000 0x00001000>;
2081724ba675SRob Herring
2082724ba675SRob Herring des: des@0 {
2083724ba675SRob Herring compatible = "ti,omap4-des";
2084724ba675SRob Herring reg = <0 0xa0>;
2085724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2086724ba675SRob Herring dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2087724ba675SRob Herring dma-names = "tx", "rx";
2088724ba675SRob Herring clocks = <&l3_iclk_div>;
2089724ba675SRob Herring clock-names = "fck";
2090724ba675SRob Herring };
2091724ba675SRob Herring };
2092724ba675SRob Herring
2093724ba675SRob Herring target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2094724ba675SRob Herring compatible = "ti,sysc";
2095724ba675SRob Herring status = "disabled";
2096724ba675SRob Herring #address-cells = <1>;
2097724ba675SRob Herring #size-cells = <1>;
2098724ba675SRob Herring ranges = <0x0 0xa8000 0x4000>;
2099724ba675SRob Herring };
2100724ba675SRob Herring
2101724ba675SRob Herring target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2102724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2103724ba675SRob Herring reg = <0xad000 0x4>,
2104724ba675SRob Herring <0xad010 0x4>;
2105724ba675SRob Herring reg-names = "rev", "sysc";
2106724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2107724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
2108724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>,
2109724ba675SRob Herring <SYSC_IDLE_NO>,
2110724ba675SRob Herring <SYSC_IDLE_SMART>,
2111724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2112724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2113724ba675SRob Herring <SYSC_IDLE_NO>,
2114724ba675SRob Herring <SYSC_IDLE_SMART>,
2115724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2116724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2117724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2118724ba675SRob Herring clock-names = "fck";
2119724ba675SRob Herring #address-cells = <1>;
2120724ba675SRob Herring #size-cells = <1>;
2121724ba675SRob Herring ranges = <0x0 0xad000 0x1000>;
2122724ba675SRob Herring
2123724ba675SRob Herring mmc3: mmc@0 {
2124724ba675SRob Herring compatible = "ti,dra7-sdhci";
2125724ba675SRob Herring reg = <0x0 0x400>;
2126724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2127724ba675SRob Herring status = "disabled";
2128724ba675SRob Herring /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2129724ba675SRob Herring max-frequency = <64000000>;
2130724ba675SRob Herring /* SDMA is not supported */
2131724ba675SRob Herring sdhci-caps-mask = <0x0 0x400000>;
2132724ba675SRob Herring };
2133724ba675SRob Herring };
2134724ba675SRob Herring
2135724ba675SRob Herring target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2136724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
2137724ba675SRob Herring reg = <0xb2000 0x4>,
2138724ba675SRob Herring <0xb2014 0x4>,
2139724ba675SRob Herring <0xb2018 0x4>;
2140724ba675SRob Herring reg-names = "rev", "sysc", "syss";
2141724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2142724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
2143724ba675SRob Herring ti,syss-mask = <1>;
2144724ba675SRob Herring ti,no-reset-on-init;
2145724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2146724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2147724ba675SRob Herring clock-names = "fck";
2148724ba675SRob Herring #address-cells = <1>;
2149724ba675SRob Herring #size-cells = <1>;
2150724ba675SRob Herring ranges = <0x0 0xb2000 0x1000>;
2151724ba675SRob Herring
2152724ba675SRob Herring hdqw1w: 1w@0 {
2153724ba675SRob Herring compatible = "ti,omap3-1w";
2154724ba675SRob Herring reg = <0x0 0x1000>;
2155724ba675SRob Herring interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2156724ba675SRob Herring };
2157724ba675SRob Herring };
2158724ba675SRob Herring
2159724ba675SRob Herring target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2160724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2161724ba675SRob Herring reg = <0xb4000 0x4>,
2162724ba675SRob Herring <0xb4010 0x4>;
2163724ba675SRob Herring reg-names = "rev", "sysc";
2164724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2165724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
2166724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>,
2167724ba675SRob Herring <SYSC_IDLE_NO>,
2168724ba675SRob Herring <SYSC_IDLE_SMART>,
2169724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2170724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2171724ba675SRob Herring <SYSC_IDLE_NO>,
2172724ba675SRob Herring <SYSC_IDLE_SMART>,
2173724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2174724ba675SRob Herring /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2175724ba675SRob Herring clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2176724ba675SRob Herring clock-names = "fck";
2177724ba675SRob Herring #address-cells = <1>;
2178724ba675SRob Herring #size-cells = <1>;
2179724ba675SRob Herring ranges = <0x0 0xb4000 0x1000>;
2180724ba675SRob Herring
2181724ba675SRob Herring mmc2: mmc@0 {
2182724ba675SRob Herring compatible = "ti,dra7-sdhci";
2183724ba675SRob Herring reg = <0x0 0x400>;
2184724ba675SRob Herring interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2185724ba675SRob Herring status = "disabled";
2186724ba675SRob Herring max-frequency = <192000000>;
2187724ba675SRob Herring /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2188724ba675SRob Herring sdhci-caps-mask = <0x7 0x0>;
2189724ba675SRob Herring mmc-hs200-1_8v;
2190724ba675SRob Herring mmc-ddr-1_8v;
2191724ba675SRob Herring mmc-ddr-3_3v;
2192724ba675SRob Herring };
2193724ba675SRob Herring };
2194724ba675SRob Herring
2195724ba675SRob Herring target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2196724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2197724ba675SRob Herring reg = <0xb8000 0x4>,
2198724ba675SRob Herring <0xb8010 0x4>;
2199724ba675SRob Herring reg-names = "rev", "sysc";
2200724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2201724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
2202724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2203724ba675SRob Herring <SYSC_IDLE_NO>,
2204724ba675SRob Herring <SYSC_IDLE_SMART>,
2205724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2206724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2207724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2208724ba675SRob Herring clock-names = "fck";
2209724ba675SRob Herring #address-cells = <1>;
2210724ba675SRob Herring #size-cells = <1>;
2211724ba675SRob Herring ranges = <0x0 0xb8000 0x1000>;
2212724ba675SRob Herring
2213724ba675SRob Herring mcspi3: spi@0 {
2214724ba675SRob Herring compatible = "ti,omap4-mcspi";
2215724ba675SRob Herring reg = <0x0 0x200>;
2216724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2217724ba675SRob Herring #address-cells = <1>;
2218724ba675SRob Herring #size-cells = <0>;
2219724ba675SRob Herring ti,spi-num-cs = <2>;
2220724ba675SRob Herring dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2221724ba675SRob Herring dma-names = "tx0", "rx0";
2222724ba675SRob Herring status = "disabled";
2223724ba675SRob Herring };
2224724ba675SRob Herring };
2225724ba675SRob Herring
2226724ba675SRob Herring target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2227724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2228724ba675SRob Herring reg = <0xba000 0x4>,
2229724ba675SRob Herring <0xba010 0x4>;
2230724ba675SRob Herring reg-names = "rev", "sysc";
2231724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2232724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
2233724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2234724ba675SRob Herring <SYSC_IDLE_NO>,
2235724ba675SRob Herring <SYSC_IDLE_SMART>,
2236724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2237724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2238724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2239724ba675SRob Herring clock-names = "fck";
2240724ba675SRob Herring #address-cells = <1>;
2241724ba675SRob Herring #size-cells = <1>;
2242724ba675SRob Herring ranges = <0x0 0xba000 0x1000>;
2243724ba675SRob Herring
2244724ba675SRob Herring mcspi4: spi@0 {
2245724ba675SRob Herring compatible = "ti,omap4-mcspi";
2246724ba675SRob Herring reg = <0x0 0x200>;
2247724ba675SRob Herring interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2248724ba675SRob Herring #address-cells = <1>;
2249724ba675SRob Herring #size-cells = <0>;
2250724ba675SRob Herring ti,spi-num-cs = <1>;
2251724ba675SRob Herring dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2252724ba675SRob Herring dma-names = "tx0", "rx0";
2253724ba675SRob Herring status = "disabled";
2254724ba675SRob Herring };
2255724ba675SRob Herring };
2256724ba675SRob Herring
2257724ba675SRob Herring target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2258724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2259724ba675SRob Herring reg = <0xd1000 0x4>,
2260724ba675SRob Herring <0xd1010 0x4>;
2261724ba675SRob Herring reg-names = "rev", "sysc";
2262724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2263724ba675SRob Herring SYSC_OMAP4_SOFTRESET)>;
2264724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>,
2265724ba675SRob Herring <SYSC_IDLE_NO>,
2266724ba675SRob Herring <SYSC_IDLE_SMART>,
2267724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2268724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2269724ba675SRob Herring <SYSC_IDLE_NO>,
2270724ba675SRob Herring <SYSC_IDLE_SMART>,
2271724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2272724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2273724ba675SRob Herring clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2274724ba675SRob Herring clock-names = "fck";
2275724ba675SRob Herring #address-cells = <1>;
2276724ba675SRob Herring #size-cells = <1>;
2277724ba675SRob Herring ranges = <0x0 0xd1000 0x1000>;
2278724ba675SRob Herring
2279724ba675SRob Herring mmc4: mmc@0 {
2280724ba675SRob Herring compatible = "ti,dra7-sdhci";
2281724ba675SRob Herring reg = <0x0 0x400>;
2282724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2283724ba675SRob Herring status = "disabled";
2284724ba675SRob Herring max-frequency = <192000000>;
2285724ba675SRob Herring /* SDMA is not supported */
2286724ba675SRob Herring sdhci-caps-mask = <0x0 0x400000>;
2287724ba675SRob Herring };
2288724ba675SRob Herring };
2289724ba675SRob Herring
2290724ba675SRob Herring target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2291724ba675SRob Herring compatible = "ti,sysc";
2292724ba675SRob Herring status = "disabled";
2293724ba675SRob Herring #address-cells = <1>;
2294724ba675SRob Herring #size-cells = <1>;
2295724ba675SRob Herring ranges = <0x0 0xd5000 0x1000>;
2296724ba675SRob Herring };
2297724ba675SRob Herring };
2298724ba675SRob Herring
2299724ba675SRob Herring segment@200000 { /* 0x48200000 */
2300724ba675SRob Herring compatible = "simple-pm-bus";
2301724ba675SRob Herring #address-cells = <1>;
2302724ba675SRob Herring #size-cells = <1>;
2303724ba675SRob Herring };
2304724ba675SRob Herring};
2305724ba675SRob Herring
2306724ba675SRob Herring&l4_per2 { /* 0x48400000 */
2307724ba675SRob Herring compatible = "ti,dra7-l4-per2", "simple-pm-bus";
2308724ba675SRob Herring power-domains = <&prm_l4per>;
2309724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;
2310724ba675SRob Herring clock-names = "fck";
2311724ba675SRob Herring reg = <0x48400000 0x800>,
2312724ba675SRob Herring <0x48400800 0x800>,
2313724ba675SRob Herring <0x48401000 0x400>,
2314724ba675SRob Herring <0x48401400 0x400>,
2315724ba675SRob Herring <0x48401800 0x400>;
2316724ba675SRob Herring reg-names = "ap", "la", "ia0", "ia1", "ia2";
2317724ba675SRob Herring #address-cells = <1>;
2318724ba675SRob Herring #size-cells = <1>;
2319724ba675SRob Herring ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2320724ba675SRob Herring <0x45800000 0x45800000 0x400000>, /* L3 data port */
2321724ba675SRob Herring <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2322724ba675SRob Herring <0x46000000 0x46000000 0x400000>, /* L3 data port */
2323724ba675SRob Herring <0x48436000 0x48436000 0x400000>, /* L3 data port */
2324724ba675SRob Herring <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2325724ba675SRob Herring <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2326724ba675SRob Herring <0x48450000 0x48450000 0x400000>, /* L3 data port */
2327724ba675SRob Herring <0x48454000 0x48454000 0x400000>; /* L3 data port */
2328724ba675SRob Herring
2329724ba675SRob Herring segment@0 { /* 0x48400000 */
2330724ba675SRob Herring compatible = "simple-pm-bus";
2331724ba675SRob Herring #address-cells = <1>;
2332724ba675SRob Herring #size-cells = <1>;
2333724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2334724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 1 */
2335724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 2 */
2336724ba675SRob Herring <0x00084000 0x00084000 0x004000>, /* ap 3 */
2337724ba675SRob Herring <0x00001400 0x00001400 0x000400>, /* ap 4 */
2338724ba675SRob Herring <0x00001800 0x00001800 0x000400>, /* ap 5 */
2339724ba675SRob Herring <0x00088000 0x00088000 0x001000>, /* ap 6 */
2340724ba675SRob Herring <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2341724ba675SRob Herring <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2342724ba675SRob Herring <0x00060000 0x00060000 0x002000>, /* ap 9 */
2343724ba675SRob Herring <0x00062000 0x00062000 0x001000>, /* ap 10 */
2344724ba675SRob Herring <0x00064000 0x00064000 0x002000>, /* ap 11 */
2345724ba675SRob Herring <0x00066000 0x00066000 0x001000>, /* ap 12 */
2346724ba675SRob Herring <0x00068000 0x00068000 0x002000>, /* ap 13 */
2347724ba675SRob Herring <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2348724ba675SRob Herring <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2349724ba675SRob Herring <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2350724ba675SRob Herring <0x00036000 0x00036000 0x001000>, /* ap 17 */
2351724ba675SRob Herring <0x00037000 0x00037000 0x001000>, /* ap 18 */
2352724ba675SRob Herring <0x00070000 0x00070000 0x002000>, /* ap 19 */
2353724ba675SRob Herring <0x00072000 0x00072000 0x001000>, /* ap 20 */
2354724ba675SRob Herring <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2355724ba675SRob Herring <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2356724ba675SRob Herring <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2357724ba675SRob Herring <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2358724ba675SRob Herring <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2359724ba675SRob Herring <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2360724ba675SRob Herring <0x00040000 0x00040000 0x001000>, /* ap 27 */
2361724ba675SRob Herring <0x00041000 0x00041000 0x001000>, /* ap 28 */
2362724ba675SRob Herring <0x00042000 0x00042000 0x001000>, /* ap 29 */
2363724ba675SRob Herring <0x00043000 0x00043000 0x001000>, /* ap 30 */
2364724ba675SRob Herring <0x00080000 0x00080000 0x002000>, /* ap 31 */
2365724ba675SRob Herring <0x00082000 0x00082000 0x001000>, /* ap 32 */
2366724ba675SRob Herring <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2367724ba675SRob Herring <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2368724ba675SRob Herring <0x00074000 0x00074000 0x002000>, /* ap 35 */
2369724ba675SRob Herring <0x00076000 0x00076000 0x001000>, /* ap 36 */
2370724ba675SRob Herring <0x00050000 0x00050000 0x001000>, /* ap 37 */
2371724ba675SRob Herring <0x00051000 0x00051000 0x001000>, /* ap 38 */
2372724ba675SRob Herring <0x00078000 0x00078000 0x002000>, /* ap 39 */
2373724ba675SRob Herring <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2374724ba675SRob Herring <0x00054000 0x00054000 0x001000>, /* ap 41 */
2375724ba675SRob Herring <0x00055000 0x00055000 0x001000>, /* ap 42 */
2376724ba675SRob Herring <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2377724ba675SRob Herring <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2378724ba675SRob Herring <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2379724ba675SRob Herring <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2380724ba675SRob Herring <0x00020000 0x00020000 0x001000>, /* ap 47 */
2381724ba675SRob Herring <0x00021000 0x00021000 0x001000>, /* ap 48 */
2382724ba675SRob Herring <0x00022000 0x00022000 0x001000>, /* ap 49 */
2383724ba675SRob Herring <0x00023000 0x00023000 0x001000>, /* ap 50 */
2384724ba675SRob Herring <0x00024000 0x00024000 0x001000>, /* ap 51 */
2385724ba675SRob Herring <0x00025000 0x00025000 0x001000>, /* ap 52 */
2386724ba675SRob Herring <0x00046000 0x00046000 0x001000>, /* ap 53 */
2387724ba675SRob Herring <0x00047000 0x00047000 0x001000>, /* ap 54 */
2388724ba675SRob Herring <0x00048000 0x00048000 0x001000>, /* ap 55 */
2389724ba675SRob Herring <0x00049000 0x00049000 0x001000>, /* ap 56 */
2390724ba675SRob Herring <0x00058000 0x00058000 0x002000>, /* ap 57 */
2391724ba675SRob Herring <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2392724ba675SRob Herring <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2393724ba675SRob Herring <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2394724ba675SRob Herring <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2395724ba675SRob Herring <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2396724ba675SRob Herring <0x45800000 0x45800000 0x400000>, /* L3 data port */
2397724ba675SRob Herring <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2398724ba675SRob Herring <0x46000000 0x46000000 0x400000>, /* L3 data port */
2399724ba675SRob Herring <0x48436000 0x48436000 0x400000>, /* L3 data port */
2400724ba675SRob Herring <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2401724ba675SRob Herring <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2402724ba675SRob Herring <0x48450000 0x48450000 0x400000>, /* L3 data port */
2403724ba675SRob Herring <0x48454000 0x48454000 0x400000>; /* L3 data port */
2404724ba675SRob Herring
2405724ba675SRob Herring target-module@20000 { /* 0x48420000, ap 47 02.0 */
2406724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
2407724ba675SRob Herring reg = <0x20050 0x4>,
2408724ba675SRob Herring <0x20054 0x4>,
2409724ba675SRob Herring <0x20058 0x4>;
2410724ba675SRob Herring reg-names = "rev", "sysc", "syss";
2411724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2412724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
2413724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
2414724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2415724ba675SRob Herring <SYSC_IDLE_NO>,
2416724ba675SRob Herring <SYSC_IDLE_SMART>,
2417724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2418724ba675SRob Herring ti,syss-mask = <1>;
2419724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2420724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2421724ba675SRob Herring clock-names = "fck";
2422724ba675SRob Herring #address-cells = <1>;
2423724ba675SRob Herring #size-cells = <1>;
2424724ba675SRob Herring ranges = <0x0 0x20000 0x1000>;
2425724ba675SRob Herring
2426724ba675SRob Herring uart7: serial@0 {
2427724ba675SRob Herring compatible = "ti,dra742-uart";
2428724ba675SRob Herring reg = <0x0 0x100>;
2429724ba675SRob Herring interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2430724ba675SRob Herring clock-frequency = <48000000>;
2431724ba675SRob Herring status = "disabled";
2432724ba675SRob Herring };
2433724ba675SRob Herring };
2434724ba675SRob Herring
2435724ba675SRob Herring target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2436724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
2437724ba675SRob Herring reg = <0x22050 0x4>,
2438724ba675SRob Herring <0x22054 0x4>,
2439724ba675SRob Herring <0x22058 0x4>;
2440724ba675SRob Herring reg-names = "rev", "sysc", "syss";
2441724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2442724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
2443724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
2444724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2445724ba675SRob Herring <SYSC_IDLE_NO>,
2446724ba675SRob Herring <SYSC_IDLE_SMART>,
2447724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2448724ba675SRob Herring ti,syss-mask = <1>;
2449724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2450724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2451724ba675SRob Herring clock-names = "fck";
2452724ba675SRob Herring #address-cells = <1>;
2453724ba675SRob Herring #size-cells = <1>;
2454724ba675SRob Herring ranges = <0x0 0x22000 0x1000>;
2455724ba675SRob Herring
2456724ba675SRob Herring uart8: serial@0 {
2457724ba675SRob Herring compatible = "ti,dra742-uart";
2458724ba675SRob Herring reg = <0x0 0x100>;
2459724ba675SRob Herring interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2460724ba675SRob Herring clock-frequency = <48000000>;
2461724ba675SRob Herring status = "disabled";
2462724ba675SRob Herring };
2463724ba675SRob Herring };
2464724ba675SRob Herring
2465724ba675SRob Herring target-module@24000 { /* 0x48424000, ap 51 12.0 */
2466724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc";
2467724ba675SRob Herring reg = <0x24050 0x4>,
2468724ba675SRob Herring <0x24054 0x4>,
2469724ba675SRob Herring <0x24058 0x4>;
2470724ba675SRob Herring reg-names = "rev", "sysc", "syss";
2471724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2472724ba675SRob Herring SYSC_OMAP2_SOFTRESET |
2473724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>;
2474724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2475724ba675SRob Herring <SYSC_IDLE_NO>,
2476724ba675SRob Herring <SYSC_IDLE_SMART>,
2477724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>;
2478724ba675SRob Herring ti,syss-mask = <1>;
2479724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2480724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2481724ba675SRob Herring clock-names = "fck";
2482724ba675SRob Herring #address-cells = <1>;
2483724ba675SRob Herring #size-cells = <1>;
2484724ba675SRob Herring ranges = <0x0 0x24000 0x1000>;
2485724ba675SRob Herring
2486724ba675SRob Herring uart9: serial@0 {
2487724ba675SRob Herring compatible = "ti,dra742-uart";
2488724ba675SRob Herring reg = <0x0 0x100>;
2489724ba675SRob Herring interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2490724ba675SRob Herring clock-frequency = <48000000>;
2491724ba675SRob Herring status = "disabled";
2492724ba675SRob Herring };
2493724ba675SRob Herring };
2494724ba675SRob Herring
2495724ba675SRob Herring target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2496724ba675SRob Herring compatible = "ti,sysc";
2497724ba675SRob Herring status = "disabled";
2498724ba675SRob Herring #address-cells = <1>;
2499724ba675SRob Herring #size-cells = <1>;
2500724ba675SRob Herring ranges = <0x0 0x2c000 0x1000>;
2501724ba675SRob Herring };
2502724ba675SRob Herring
2503724ba675SRob Herring target-module@36000 { /* 0x48436000, ap 17 06.0 */
2504724ba675SRob Herring compatible = "ti,sysc";
2505724ba675SRob Herring status = "disabled";
2506724ba675SRob Herring #address-cells = <1>;
2507724ba675SRob Herring #size-cells = <1>;
2508724ba675SRob Herring ranges = <0x0 0x36000 0x1000>;
2509724ba675SRob Herring };
2510724ba675SRob Herring
2511724ba675SRob Herring target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2512724ba675SRob Herring compatible = "ti,sysc";
2513724ba675SRob Herring status = "disabled";
2514724ba675SRob Herring #address-cells = <1>;
2515724ba675SRob Herring #size-cells = <1>;
2516724ba675SRob Herring ranges = <0x0 0x3a000 0x1000>;
2517724ba675SRob Herring };
2518724ba675SRob Herring
2519724ba675SRob Herring atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2520724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2521724ba675SRob Herring reg = <0x3c000 0x4>;
2522724ba675SRob Herring reg-names = "rev";
2523724ba675SRob Herring clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2524724ba675SRob Herring clock-names = "fck";
2525724ba675SRob Herring #address-cells = <1>;
2526724ba675SRob Herring #size-cells = <1>;
2527724ba675SRob Herring ranges = <0x0 0x3c000 0x1000>;
2528724ba675SRob Herring
2529724ba675SRob Herring atl: atl@0 {
2530724ba675SRob Herring compatible = "ti,dra7-atl";
2531724ba675SRob Herring reg = <0x0 0x3ff>;
2532724ba675SRob Herring ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2533724ba675SRob Herring <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2534724ba675SRob Herring clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2535724ba675SRob Herring clock-names = "fck";
2536724ba675SRob Herring status = "disabled";
2537724ba675SRob Herring };
2538724ba675SRob Herring };
2539724ba675SRob Herring
2540724ba675SRob Herring target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2541724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2542724ba675SRob Herring reg = <0x3e000 0x4>,
2543724ba675SRob Herring <0x3e004 0x4>;
2544724ba675SRob Herring reg-names = "rev", "sysc";
2545724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2546724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2547724ba675SRob Herring <SYSC_IDLE_NO>,
2548724ba675SRob Herring <SYSC_IDLE_SMART>;
2549724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2550724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2551724ba675SRob Herring clock-names = "fck";
2552724ba675SRob Herring #address-cells = <1>;
2553724ba675SRob Herring #size-cells = <1>;
2554724ba675SRob Herring ranges = <0x0 0x3e000 0x1000>;
2555724ba675SRob Herring
2556724ba675SRob Herring epwmss0: epwmss@0 {
2557724ba675SRob Herring compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2558724ba675SRob Herring reg = <0x0 0x30>;
2559724ba675SRob Herring #address-cells = <1>;
2560724ba675SRob Herring #size-cells = <1>;
2561724ba675SRob Herring status = "disabled";
2562724ba675SRob Herring ranges = <0 0 0x1000>;
2563724ba675SRob Herring
2564724ba675SRob Herring ecap0: pwm@100 {
2565724ba675SRob Herring compatible = "ti,dra746-ecap",
2566724ba675SRob Herring "ti,am3352-ecap";
2567724ba675SRob Herring #pwm-cells = <3>;
2568724ba675SRob Herring reg = <0x100 0x80>;
2569724ba675SRob Herring clocks = <&l4_root_clk_div>;
2570724ba675SRob Herring clock-names = "fck";
2571724ba675SRob Herring status = "disabled";
2572724ba675SRob Herring };
2573724ba675SRob Herring
2574724ba675SRob Herring ehrpwm0: pwm@200 {
2575724ba675SRob Herring compatible = "ti,dra746-ehrpwm",
2576724ba675SRob Herring "ti,am3352-ehrpwm";
2577724ba675SRob Herring #pwm-cells = <3>;
2578724ba675SRob Herring reg = <0x200 0x80>;
2579724ba675SRob Herring clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2580724ba675SRob Herring clock-names = "tbclk", "fck";
2581724ba675SRob Herring status = "disabled";
2582724ba675SRob Herring };
2583724ba675SRob Herring };
2584724ba675SRob Herring };
2585724ba675SRob Herring
2586724ba675SRob Herring target-module@40000 { /* 0x48440000, ap 27 38.0 */
2587724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2588724ba675SRob Herring reg = <0x40000 0x4>,
2589724ba675SRob Herring <0x40004 0x4>;
2590724ba675SRob Herring reg-names = "rev", "sysc";
2591724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2592724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2593724ba675SRob Herring <SYSC_IDLE_NO>,
2594724ba675SRob Herring <SYSC_IDLE_SMART>;
2595724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2596724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2597724ba675SRob Herring clock-names = "fck";
2598724ba675SRob Herring #address-cells = <1>;
2599724ba675SRob Herring #size-cells = <1>;
2600724ba675SRob Herring ranges = <0x0 0x40000 0x1000>;
2601724ba675SRob Herring
2602724ba675SRob Herring epwmss1: epwmss@0 {
2603724ba675SRob Herring compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2604724ba675SRob Herring reg = <0x0 0x30>;
2605724ba675SRob Herring #address-cells = <1>;
2606724ba675SRob Herring #size-cells = <1>;
2607724ba675SRob Herring status = "disabled";
2608724ba675SRob Herring ranges = <0 0 0x1000>;
2609724ba675SRob Herring
2610724ba675SRob Herring ecap1: pwm@100 {
2611724ba675SRob Herring compatible = "ti,dra746-ecap",
2612724ba675SRob Herring "ti,am3352-ecap";
2613724ba675SRob Herring #pwm-cells = <3>;
2614724ba675SRob Herring reg = <0x100 0x80>;
2615724ba675SRob Herring clocks = <&l4_root_clk_div>;
2616724ba675SRob Herring clock-names = "fck";
2617724ba675SRob Herring status = "disabled";
2618724ba675SRob Herring };
2619724ba675SRob Herring
2620724ba675SRob Herring ehrpwm1: pwm@200 {
2621724ba675SRob Herring compatible = "ti,dra746-ehrpwm",
2622724ba675SRob Herring "ti,am3352-ehrpwm";
2623724ba675SRob Herring #pwm-cells = <3>;
2624724ba675SRob Herring reg = <0x200 0x80>;
2625724ba675SRob Herring clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2626724ba675SRob Herring clock-names = "tbclk", "fck";
2627724ba675SRob Herring status = "disabled";
2628724ba675SRob Herring };
2629724ba675SRob Herring };
2630724ba675SRob Herring };
2631724ba675SRob Herring
2632724ba675SRob Herring target-module@42000 { /* 0x48442000, ap 29 20.0 */
2633724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
2634724ba675SRob Herring reg = <0x42000 0x4>,
2635724ba675SRob Herring <0x42004 0x4>;
2636724ba675SRob Herring reg-names = "rev", "sysc";
2637724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2638724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2639724ba675SRob Herring <SYSC_IDLE_NO>,
2640724ba675SRob Herring <SYSC_IDLE_SMART>;
2641724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2642724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2643724ba675SRob Herring clock-names = "fck";
2644724ba675SRob Herring #address-cells = <1>;
2645724ba675SRob Herring #size-cells = <1>;
2646724ba675SRob Herring ranges = <0x0 0x42000 0x1000>;
2647724ba675SRob Herring
2648724ba675SRob Herring epwmss2: epwmss@0 {
2649724ba675SRob Herring compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2650724ba675SRob Herring reg = <0x0 0x30>;
2651724ba675SRob Herring #address-cells = <1>;
2652724ba675SRob Herring #size-cells = <1>;
2653724ba675SRob Herring status = "disabled";
2654724ba675SRob Herring ranges = <0 0 0x1000>;
2655724ba675SRob Herring
2656724ba675SRob Herring ecap2: pwm@100 {
2657724ba675SRob Herring compatible = "ti,dra746-ecap",
2658724ba675SRob Herring "ti,am3352-ecap";
2659724ba675SRob Herring #pwm-cells = <3>;
2660724ba675SRob Herring reg = <0x100 0x80>;
2661724ba675SRob Herring clocks = <&l4_root_clk_div>;
2662724ba675SRob Herring clock-names = "fck";
2663724ba675SRob Herring status = "disabled";
2664724ba675SRob Herring };
2665724ba675SRob Herring
2666724ba675SRob Herring ehrpwm2: pwm@200 {
2667724ba675SRob Herring compatible = "ti,dra746-ehrpwm",
2668724ba675SRob Herring "ti,am3352-ehrpwm";
2669724ba675SRob Herring #pwm-cells = <3>;
2670724ba675SRob Herring reg = <0x200 0x80>;
2671724ba675SRob Herring clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2672724ba675SRob Herring clock-names = "tbclk", "fck";
2673724ba675SRob Herring status = "disabled";
2674724ba675SRob Herring };
2675724ba675SRob Herring };
2676724ba675SRob Herring };
2677724ba675SRob Herring
2678724ba675SRob Herring target-module@46000 { /* 0x48446000, ap 53 40.0 */
2679724ba675SRob Herring compatible = "ti,sysc";
2680724ba675SRob Herring status = "disabled";
2681724ba675SRob Herring #address-cells = <1>;
2682724ba675SRob Herring #size-cells = <1>;
2683724ba675SRob Herring ranges = <0x0 0x46000 0x1000>;
2684724ba675SRob Herring };
2685724ba675SRob Herring
2686724ba675SRob Herring target-module@48000 { /* 0x48448000, ap 55 48.0 */
2687724ba675SRob Herring compatible = "ti,sysc";
2688724ba675SRob Herring status = "disabled";
2689724ba675SRob Herring #address-cells = <1>;
2690724ba675SRob Herring #size-cells = <1>;
2691724ba675SRob Herring ranges = <0x0 0x48000 0x1000>;
2692724ba675SRob Herring };
2693724ba675SRob Herring
2694724ba675SRob Herring target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2695724ba675SRob Herring compatible = "ti,sysc";
2696724ba675SRob Herring status = "disabled";
2697724ba675SRob Herring #address-cells = <1>;
2698724ba675SRob Herring #size-cells = <1>;
2699724ba675SRob Herring ranges = <0x0 0x4a000 0x1000>;
2700724ba675SRob Herring };
2701724ba675SRob Herring
2702724ba675SRob Herring target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2703724ba675SRob Herring compatible = "ti,sysc";
2704724ba675SRob Herring status = "disabled";
2705724ba675SRob Herring #address-cells = <1>;
2706724ba675SRob Herring #size-cells = <1>;
2707724ba675SRob Herring ranges = <0x0 0x4c000 0x1000>;
2708724ba675SRob Herring };
2709724ba675SRob Herring
2710724ba675SRob Herring target-module@50000 { /* 0x48450000, ap 37 24.0 */
2711724ba675SRob Herring compatible = "ti,sysc";
2712724ba675SRob Herring status = "disabled";
2713724ba675SRob Herring #address-cells = <1>;
2714724ba675SRob Herring #size-cells = <1>;
2715724ba675SRob Herring ranges = <0x0 0x50000 0x1000>;
2716724ba675SRob Herring };
2717724ba675SRob Herring
2718724ba675SRob Herring target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2719724ba675SRob Herring compatible = "ti,sysc";
2720724ba675SRob Herring status = "disabled";
2721724ba675SRob Herring #address-cells = <1>;
2722724ba675SRob Herring #size-cells = <1>;
2723724ba675SRob Herring ranges = <0x0 0x54000 0x1000>;
2724724ba675SRob Herring };
2725724ba675SRob Herring
2726724ba675SRob Herring target-module@58000 { /* 0x48458000, ap 57 28.0 */
2727724ba675SRob Herring compatible = "ti,sysc";
2728724ba675SRob Herring status = "disabled";
2729724ba675SRob Herring #address-cells = <1>;
2730724ba675SRob Herring #size-cells = <1>;
2731724ba675SRob Herring ranges = <0x0 0x58000 0x2000>;
2732724ba675SRob Herring };
2733724ba675SRob Herring
2734724ba675SRob Herring target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2735724ba675SRob Herring compatible = "ti,sysc";
2736724ba675SRob Herring status = "disabled";
2737724ba675SRob Herring #address-cells = <1>;
2738724ba675SRob Herring #size-cells = <1>;
2739724ba675SRob Herring ranges = <0x0 0x5b000 0x1000>;
2740724ba675SRob Herring };
2741724ba675SRob Herring
2742724ba675SRob Herring target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2743724ba675SRob Herring compatible = "ti,sysc";
2744724ba675SRob Herring status = "disabled";
2745724ba675SRob Herring #address-cells = <1>;
2746724ba675SRob Herring #size-cells = <1>;
2747724ba675SRob Herring ranges = <0x0 0x5d000 0x1000>;
2748724ba675SRob Herring };
2749724ba675SRob Herring
2750724ba675SRob Herring target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2751724ba675SRob Herring compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2752724ba675SRob Herring reg = <0x60000 0x4>,
2753724ba675SRob Herring <0x60004 0x4>;
2754724ba675SRob Herring reg-names = "rev", "sysc";
2755724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2756724ba675SRob Herring <SYSC_IDLE_NO>,
2757724ba675SRob Herring <SYSC_IDLE_SMART>;
2758724ba675SRob Herring /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2759724ba675SRob Herring clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2760724ba675SRob Herring <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2761724ba675SRob Herring <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2762724ba675SRob Herring clock-names = "fck", "ahclkx", "ahclkr";
2763724ba675SRob Herring #address-cells = <1>;
2764724ba675SRob Herring #size-cells = <1>;
2765724ba675SRob Herring ranges = <0x0 0x60000 0x2000>,
2766724ba675SRob Herring <0x45800000 0x45800000 0x400000>;
2767724ba675SRob Herring
2768724ba675SRob Herring mcasp1: mcasp@0 {
2769724ba675SRob Herring compatible = "ti,dra7-mcasp-audio";
2770724ba675SRob Herring reg = <0x0 0x2000>,
2771724ba675SRob Herring <0x45800000 0x1000>; /* L3 data port */
2772724ba675SRob Herring reg-names = "mpu","dat";
2773724ba675SRob Herring interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2774724ba675SRob Herring <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2775724ba675SRob Herring interrupt-names = "tx", "rx";
2776724ba675SRob Herring dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2777724ba675SRob Herring dma-names = "tx", "rx";
2778724ba675SRob Herring clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2779724ba675SRob Herring <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2780724ba675SRob Herring <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2781724ba675SRob Herring clock-names = "fck", "ahclkx", "ahclkr";
2782724ba675SRob Herring status = "disabled";
2783724ba675SRob Herring };
2784724ba675SRob Herring };
2785724ba675SRob Herring
2786724ba675SRob Herring target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2787724ba675SRob Herring compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2788724ba675SRob Herring reg = <0x64000 0x4>,
2789724ba675SRob Herring <0x64004 0x4>;
2790724ba675SRob Herring reg-names = "rev", "sysc";
2791724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2792724ba675SRob Herring <SYSC_IDLE_NO>,
2793724ba675SRob Herring <SYSC_IDLE_SMART>;
2794724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2795724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2796724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2797724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2798724ba675SRob Herring clock-names = "fck", "ahclkx", "ahclkr";
2799724ba675SRob Herring #address-cells = <1>;
2800724ba675SRob Herring #size-cells = <1>;
2801724ba675SRob Herring ranges = <0x0 0x64000 0x2000>,
2802724ba675SRob Herring <0x45c00000 0x45c00000 0x400000>;
2803724ba675SRob Herring
2804724ba675SRob Herring mcasp2: mcasp@0 {
2805724ba675SRob Herring compatible = "ti,dra7-mcasp-audio";
2806724ba675SRob Herring reg = <0x0 0x2000>,
2807724ba675SRob Herring <0x45c00000 0x1000>; /* L3 data port */
2808724ba675SRob Herring reg-names = "mpu","dat";
2809724ba675SRob Herring interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2810724ba675SRob Herring <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2811724ba675SRob Herring interrupt-names = "tx", "rx";
2812724ba675SRob Herring dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2813724ba675SRob Herring dma-names = "tx", "rx";
2814724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2815724ba675SRob Herring <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2816724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2817724ba675SRob Herring clock-names = "fck", "ahclkx", "ahclkr";
2818724ba675SRob Herring status = "disabled";
2819724ba675SRob Herring };
2820724ba675SRob Herring };
2821724ba675SRob Herring
2822724ba675SRob Herring target-module@68000 { /* 0x48468000, ap 13 26.0 */
2823724ba675SRob Herring compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2824724ba675SRob Herring reg = <0x68000 0x4>,
2825724ba675SRob Herring <0x68004 0x4>;
2826724ba675SRob Herring reg-names = "rev", "sysc";
2827724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2828724ba675SRob Herring <SYSC_IDLE_NO>,
2829724ba675SRob Herring <SYSC_IDLE_SMART>;
2830724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2831724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2832724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2833724ba675SRob Herring clock-names = "fck", "ahclkx";
2834724ba675SRob Herring #address-cells = <1>;
2835724ba675SRob Herring #size-cells = <1>;
2836724ba675SRob Herring ranges = <0x0 0x68000 0x2000>,
2837724ba675SRob Herring <0x46000000 0x46000000 0x400000>;
2838724ba675SRob Herring
2839724ba675SRob Herring mcasp3: mcasp@0 {
2840724ba675SRob Herring compatible = "ti,dra7-mcasp-audio";
2841724ba675SRob Herring reg = <0x0 0x2000>,
2842724ba675SRob Herring <0x46000000 0x1000>; /* L3 data port */
2843724ba675SRob Herring reg-names = "mpu","dat";
2844724ba675SRob Herring interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2845724ba675SRob Herring <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2846724ba675SRob Herring interrupt-names = "tx", "rx";
2847724ba675SRob Herring dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2848724ba675SRob Herring dma-names = "tx", "rx";
2849724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2850724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2851724ba675SRob Herring clock-names = "fck", "ahclkx";
2852724ba675SRob Herring status = "disabled";
2853724ba675SRob Herring };
2854724ba675SRob Herring };
2855724ba675SRob Herring
2856724ba675SRob Herring target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2857724ba675SRob Herring compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2858724ba675SRob Herring reg = <0x6c000 0x4>,
2859724ba675SRob Herring <0x6c004 0x4>;
2860724ba675SRob Herring reg-names = "rev", "sysc";
2861724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2862724ba675SRob Herring <SYSC_IDLE_NO>,
2863724ba675SRob Herring <SYSC_IDLE_SMART>;
2864724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2865724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2866724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2867724ba675SRob Herring clock-names = "fck", "ahclkx";
2868724ba675SRob Herring #address-cells = <1>;
2869724ba675SRob Herring #size-cells = <1>;
2870724ba675SRob Herring ranges = <0x0 0x6c000 0x2000>,
2871724ba675SRob Herring <0x48436000 0x48436000 0x400000>;
2872724ba675SRob Herring
2873724ba675SRob Herring mcasp4: mcasp@0 {
2874724ba675SRob Herring compatible = "ti,dra7-mcasp-audio";
2875724ba675SRob Herring reg = <0x0 0x2000>,
2876724ba675SRob Herring <0x48436000 0x1000>; /* L3 data port */
2877724ba675SRob Herring reg-names = "mpu","dat";
2878724ba675SRob Herring interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2879724ba675SRob Herring <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2880724ba675SRob Herring interrupt-names = "tx", "rx";
2881724ba675SRob Herring dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2882724ba675SRob Herring dma-names = "tx", "rx";
2883724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2884724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2885724ba675SRob Herring clock-names = "fck", "ahclkx";
2886724ba675SRob Herring status = "disabled";
2887724ba675SRob Herring };
2888724ba675SRob Herring };
2889724ba675SRob Herring
2890724ba675SRob Herring target-module@70000 { /* 0x48470000, ap 19 36.0 */
2891724ba675SRob Herring compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2892724ba675SRob Herring reg = <0x70000 0x4>,
2893724ba675SRob Herring <0x70004 0x4>;
2894724ba675SRob Herring reg-names = "rev", "sysc";
2895724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2896724ba675SRob Herring <SYSC_IDLE_NO>,
2897724ba675SRob Herring <SYSC_IDLE_SMART>;
2898724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2899724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2900724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2901724ba675SRob Herring clock-names = "fck", "ahclkx";
2902724ba675SRob Herring #address-cells = <1>;
2903724ba675SRob Herring #size-cells = <1>;
2904724ba675SRob Herring ranges = <0x0 0x70000 0x2000>,
2905724ba675SRob Herring <0x4843a000 0x4843a000 0x400000>;
2906724ba675SRob Herring
2907724ba675SRob Herring mcasp5: mcasp@0 {
2908724ba675SRob Herring compatible = "ti,dra7-mcasp-audio";
2909724ba675SRob Herring reg = <0x0 0x2000>,
2910724ba675SRob Herring <0x4843a000 0x1000>; /* L3 data port */
2911724ba675SRob Herring reg-names = "mpu","dat";
2912724ba675SRob Herring interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2913724ba675SRob Herring <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2914724ba675SRob Herring interrupt-names = "tx", "rx";
2915724ba675SRob Herring dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2916724ba675SRob Herring dma-names = "tx", "rx";
2917724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2918724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2919724ba675SRob Herring clock-names = "fck", "ahclkx";
2920724ba675SRob Herring status = "disabled";
2921724ba675SRob Herring };
2922724ba675SRob Herring };
2923724ba675SRob Herring
2924724ba675SRob Herring target-module@74000 { /* 0x48474000, ap 35 14.0 */
2925724ba675SRob Herring compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2926724ba675SRob Herring reg = <0x74000 0x4>,
2927724ba675SRob Herring <0x74004 0x4>;
2928724ba675SRob Herring reg-names = "rev", "sysc";
2929724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2930724ba675SRob Herring <SYSC_IDLE_NO>,
2931724ba675SRob Herring <SYSC_IDLE_SMART>;
2932724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2933724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2934724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2935724ba675SRob Herring clock-names = "fck", "ahclkx";
2936724ba675SRob Herring #address-cells = <1>;
2937724ba675SRob Herring #size-cells = <1>;
2938724ba675SRob Herring ranges = <0x0 0x74000 0x2000>,
2939724ba675SRob Herring <0x4844c000 0x4844c000 0x400000>;
2940724ba675SRob Herring
2941724ba675SRob Herring mcasp6: mcasp@0 {
2942724ba675SRob Herring compatible = "ti,dra7-mcasp-audio";
2943724ba675SRob Herring reg = <0x0 0x2000>,
2944724ba675SRob Herring <0x4844c000 0x1000>; /* L3 data port */
2945724ba675SRob Herring reg-names = "mpu","dat";
2946724ba675SRob Herring interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2947724ba675SRob Herring <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2948724ba675SRob Herring interrupt-names = "tx", "rx";
2949724ba675SRob Herring dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2950724ba675SRob Herring dma-names = "tx", "rx";
2951724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2952724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2953724ba675SRob Herring clock-names = "fck", "ahclkx";
2954724ba675SRob Herring status = "disabled";
2955724ba675SRob Herring };
2956724ba675SRob Herring };
2957724ba675SRob Herring
2958724ba675SRob Herring target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2959724ba675SRob Herring compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2960724ba675SRob Herring reg = <0x78000 0x4>,
2961724ba675SRob Herring <0x78004 0x4>;
2962724ba675SRob Herring reg-names = "rev", "sysc";
2963724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2964724ba675SRob Herring <SYSC_IDLE_NO>,
2965724ba675SRob Herring <SYSC_IDLE_SMART>;
2966724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2967724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2968724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2969724ba675SRob Herring clock-names = "fck", "ahclkx";
2970724ba675SRob Herring #address-cells = <1>;
2971724ba675SRob Herring #size-cells = <1>;
2972724ba675SRob Herring ranges = <0x0 0x78000 0x2000>,
2973724ba675SRob Herring <0x48450000 0x48450000 0x400000>;
2974724ba675SRob Herring
2975724ba675SRob Herring mcasp7: mcasp@0 {
2976724ba675SRob Herring compatible = "ti,dra7-mcasp-audio";
2977724ba675SRob Herring reg = <0x0 0x2000>,
2978724ba675SRob Herring <0x48450000 0x1000>; /* L3 data port */
2979724ba675SRob Herring reg-names = "mpu","dat";
2980724ba675SRob Herring interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2981724ba675SRob Herring <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2982724ba675SRob Herring interrupt-names = "tx", "rx";
2983724ba675SRob Herring dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2984724ba675SRob Herring dma-names = "tx", "rx";
2985724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2986724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2987724ba675SRob Herring clock-names = "fck", "ahclkx";
2988724ba675SRob Herring status = "disabled";
2989724ba675SRob Herring };
2990724ba675SRob Herring };
2991724ba675SRob Herring
2992724ba675SRob Herring target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2993724ba675SRob Herring compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2994724ba675SRob Herring reg = <0x7c000 0x4>,
2995724ba675SRob Herring <0x7c004 0x4>;
2996724ba675SRob Herring reg-names = "rev", "sysc";
2997724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2998724ba675SRob Herring <SYSC_IDLE_NO>,
2999724ba675SRob Herring <SYSC_IDLE_SMART>;
3000724ba675SRob Herring /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
3001724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3002724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
3003724ba675SRob Herring clock-names = "fck", "ahclkx";
3004724ba675SRob Herring #address-cells = <1>;
3005724ba675SRob Herring #size-cells = <1>;
3006724ba675SRob Herring ranges = <0x0 0x7c000 0x2000>,
3007724ba675SRob Herring <0x48454000 0x48454000 0x400000>;
3008724ba675SRob Herring
3009724ba675SRob Herring mcasp8: mcasp@0 {
3010724ba675SRob Herring compatible = "ti,dra7-mcasp-audio";
3011724ba675SRob Herring reg = <0x0 0x2000>,
3012724ba675SRob Herring <0x48454000 0x1000>; /* L3 data port */
3013724ba675SRob Herring reg-names = "mpu","dat";
3014724ba675SRob Herring interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
3015724ba675SRob Herring <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
3016724ba675SRob Herring interrupt-names = "tx", "rx";
3017724ba675SRob Herring dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
3018724ba675SRob Herring dma-names = "tx", "rx";
3019724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3020724ba675SRob Herring <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
3021724ba675SRob Herring clock-names = "fck", "ahclkx";
3022724ba675SRob Herring status = "disabled";
3023724ba675SRob Herring };
3024724ba675SRob Herring };
3025724ba675SRob Herring
3026724ba675SRob Herring target-module@80000 { /* 0x48480000, ap 31 16.0 */
3027724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc";
3028724ba675SRob Herring reg = <0x80020 0x4>;
3029724ba675SRob Herring reg-names = "rev";
3030724ba675SRob Herring clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3031724ba675SRob Herring clock-names = "fck";
3032724ba675SRob Herring #address-cells = <1>;
3033724ba675SRob Herring #size-cells = <1>;
3034724ba675SRob Herring ranges = <0x0 0x80000 0x2000>;
3035724ba675SRob Herring
3036724ba675SRob Herring dcan2: can@0 {
3037724ba675SRob Herring compatible = "ti,dra7-d_can";
3038724ba675SRob Herring reg = <0x0 0x2000>;
3039724ba675SRob Herring syscon-raminit = <&scm_conf 0x558 1>;
3040724ba675SRob Herring interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
3041724ba675SRob Herring clocks = <&sys_clkin1>;
3042724ba675SRob Herring status = "disabled";
3043724ba675SRob Herring };
3044724ba675SRob Herring };
3045724ba675SRob Herring
3046724ba675SRob Herring target-module@84000 { /* 0x48484000, ap 3 10.0 */
3047724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc";
3048724ba675SRob Herring reg = <0x85200 0x4>,
3049724ba675SRob Herring <0x85208 0x4>,
3050724ba675SRob Herring <0x85204 0x4>;
3051724ba675SRob Herring reg-names = "rev", "sysc", "syss";
3052724ba675SRob Herring ti,sysc-mask = <0>;
3053724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>,
3054724ba675SRob Herring <SYSC_IDLE_NO>;
3055724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3056724ba675SRob Herring <SYSC_IDLE_NO>;
3057724ba675SRob Herring ti,syss-mask = <1>;
3058724ba675SRob Herring clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3059724ba675SRob Herring clock-names = "fck";
3060724ba675SRob Herring #address-cells = <1>;
3061724ba675SRob Herring #size-cells = <1>;
3062724ba675SRob Herring ranges = <0x0 0x84000 0x4000>;
3063724ba675SRob Herring /*
3064724ba675SRob Herring * Do not allow gating of cpsw clock as workaround
3065724ba675SRob Herring * for errata i877. Keeping internal clock disabled
3066724ba675SRob Herring * causes the device switching characteristics
3067724ba675SRob Herring * to degrade over time and eventually fail to meet
3068724ba675SRob Herring * the data manual delay time/skew specs.
3069724ba675SRob Herring */
3070724ba675SRob Herring ti,no-idle;
3071724ba675SRob Herring
3072724ba675SRob Herring mac_sw: switch@0 {
3073724ba675SRob Herring compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
3074724ba675SRob Herring reg = <0x0 0x4000>;
3075724ba675SRob Herring ranges = <0 0 0x4000>;
3076724ba675SRob Herring clocks = <&gmac_main_clk>;
3077724ba675SRob Herring clock-names = "fck";
3078724ba675SRob Herring #address-cells = <1>;
3079724ba675SRob Herring #size-cells = <1>;
3080724ba675SRob Herring syscon = <&scm_conf>;
3081724ba675SRob Herring status = "disabled";
3082724ba675SRob Herring
3083724ba675SRob Herring interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3084724ba675SRob Herring <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3085724ba675SRob Herring <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3086724ba675SRob Herring <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3087724ba675SRob Herring interrupt-names = "rx_thresh", "rx", "tx", "misc";
3088724ba675SRob Herring
3089724ba675SRob Herring ethernet-ports {
3090724ba675SRob Herring #address-cells = <1>;
3091724ba675SRob Herring #size-cells = <0>;
3092724ba675SRob Herring
3093724ba675SRob Herring cpsw_port1: port@1 {
3094724ba675SRob Herring reg = <1>;
3095724ba675SRob Herring label = "port1";
3096724ba675SRob Herring mac-address = [ 00 00 00 00 00 00 ];
3097724ba675SRob Herring phys = <&phy_gmii_sel 1>;
3098724ba675SRob Herring };
3099724ba675SRob Herring
3100724ba675SRob Herring cpsw_port2: port@2 {
3101724ba675SRob Herring reg = <2>;
3102724ba675SRob Herring label = "port2";
3103724ba675SRob Herring mac-address = [ 00 00 00 00 00 00 ];
3104724ba675SRob Herring phys = <&phy_gmii_sel 2>;
3105724ba675SRob Herring };
3106724ba675SRob Herring };
3107724ba675SRob Herring
3108724ba675SRob Herring davinci_mdio_sw: mdio@1000 {
3109724ba675SRob Herring compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3110724ba675SRob Herring clocks = <&gmac_main_clk>;
3111724ba675SRob Herring clock-names = "fck";
3112724ba675SRob Herring #address-cells = <1>;
3113724ba675SRob Herring #size-cells = <0>;
3114724ba675SRob Herring bus_freq = <1000000>;
3115724ba675SRob Herring reg = <0x1000 0x100>;
3116724ba675SRob Herring };
3117724ba675SRob Herring
3118724ba675SRob Herring cpts {
3119724ba675SRob Herring clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3120724ba675SRob Herring clock-names = "cpts";
3121724ba675SRob Herring };
3122724ba675SRob Herring };
3123724ba675SRob Herring };
3124724ba675SRob Herring };
3125724ba675SRob Herring};
3126724ba675SRob Herring
3127724ba675SRob Herring&l4_per3 { /* 0x48800000 */
3128724ba675SRob Herring compatible = "ti,dra7-l4-per3", "simple-pm-bus";
3129724ba675SRob Herring power-domains = <&prm_l4per>;
3130724ba675SRob Herring clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>;
3131724ba675SRob Herring clock-names = "fck";
3132724ba675SRob Herring reg = <0x48800000 0x800>,
3133724ba675SRob Herring <0x48800800 0x800>,
3134724ba675SRob Herring <0x48801000 0x400>,
3135724ba675SRob Herring <0x48801400 0x400>,
3136724ba675SRob Herring <0x48801800 0x400>;
3137724ba675SRob Herring reg-names = "ap", "la", "ia0", "ia1", "ia2";
3138724ba675SRob Herring #address-cells = <1>;
3139724ba675SRob Herring #size-cells = <1>;
3140724ba675SRob Herring ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3141724ba675SRob Herring
3142724ba675SRob Herring segment@0 { /* 0x48800000 */
3143724ba675SRob Herring compatible = "simple-pm-bus";
3144724ba675SRob Herring #address-cells = <1>;
3145724ba675SRob Herring #size-cells = <1>;
3146724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3147724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */
3148724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 2 */
3149