/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | omap4460.dtsi | 12 cpu0: cpu@0 { 32 reg = <0x4a002260 0x4 33 0x4a00232C 0x4 34 0x4a002378 0x18>; 36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ 39 #thermal-sensor-cells = <0>; 45 reg = <0x4a307bd [all...] |
H A D | omap5-l4-abe.dtsi | 1 &l4_abe { /* 0x40100000 */ 3 reg = <0x40100000 0x400>, 4 <0x40100400 0x400>; 10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ 11 <0x4900000 [all...] |
H A D | omap4-l4-abe.dtsi | 1 &l4_abe { /* 0x40100000 */ 3 reg = <0x40100000 0x400>, 4 <0x40100400 0x400>; 10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ 11 <0x4900000 [all...] |
H A D | am33xx-l4.dtsi | 1 &l4_wkup { /* 0x44c00000 */ 4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x40 [all...] |
H A D | omap4-l4.dtsi | 2 &l4_cfg { /* 0x4a000000 */ 5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>; 7 reg = <0x4a000000 0x800>, 8 <0x4a000800 0x800>, 9 <0x4a001000 0x1000>; 13 ranges = <0x00000000 0x4a00000 [all...] |
H A D | omap5-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */ 4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ 13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */ 14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */ 15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */ 16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */ [all …]
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H A D | dra7-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */ 4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ 13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */ 14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */ 16 segment@0 { /* 0x4a000000 */ 20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ [all …]
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H A D | am437x-l4.dtsi | 1 &l4_wkup { /* 0x44c00000 */ 4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x40 [all...] |
/freebsd/sys/contrib/device-tree/Bindings/bus/ |
H A D | brcm,bus-axi.txt | 26 reg = <0x18000000 0x1000>; 27 ranges = <0x00000000 0x18000000 0x00100000>; 31 interrupt-map-mask = <0x000fffff 0xffff>; 33 /* Ethernet Controller 0 */ 34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 39 /* PCIe Controller 0 */ 40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/ |
H A D | nvidia,tegra20-host1x.yaml | 175 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to 202 - description: host1x syncpoint interrupt 0 226 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to 240 reg = <0x50000000 0x00024000>; 241 interrupts = <0 65 0x04>, /* mpcore syncpt */ 242 <0 67 0x04>; /* mpcore general */ 252 ranges = <0x54000000 0x54000000 0x04000000>; 256 reg = <0x54040000 0x00040000>; 257 interrupts = <0 68 0x04>; 265 reg = <0x54080000 0x00040000>; [all …]
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H A D | nvidia,tegra20-host1x.txt | 106 - reg: csi port number. Valid port numbers are 0 through 5. 120 port@0 with single child 'endpoint' node always a sink. 123 port@0 (required node) 125 - reg: 0 440 reg = <0x50000000 0x00024000>; 441 interrupts = <0 65 0x04 /* mpcore syncpt */ 442 0 67 0x04>; /* mpcore general */ 452 ranges = <0x54000000 0x54000000 0x04000000>; 456 reg = <0x54040000 0x00040000>; 457 interrupts = <0 68 0x04>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/ |
H A D | bcm-ns.dtsi | 26 ranges = <0x00000000 0x18000000 0x00001000>; 32 reg = <0x0300 0x100>; 40 reg = <0x0400 0x100>; 44 pinctrl-0 = <&pinmux_uart1>; 51 ranges = <0x00000000 0x1900000 [all...] |
/freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra20.dtsi | 17 memory@0 { 19 reg = <0 0>; 24 reg = <0x40000000 0x40000>; 27 ranges = <0 0x40000000 0x40000>; 30 reg = <0x400 0x3fc0 [all...] |
H A D | tegra30.dtsi | 20 reg = <0x80000000 0x0>; 26 reg = <0x00003000 0x00000800>, /* PADS registers */ 27 <0x00003800 0x00000200>, /* AFI registers */ 28 <0x10000000 0x10000000>; /* configuration space */ 35 interrupt-map-mask = <0 0 [all...] |
/freebsd/sys/contrib/dev/rtw89/ |
H A D | rtw8852c_table.c | 10 {0xF0FF0000, 0x00000000}, 11 {0xF03300FF, 0x00000001}, 12 {0xF03400FF, 0x00000002}, 13 {0xF03500FF, 0x00000003}, 14 {0xF03600FF, 0x0000000 [all...] |
/freebsd/sys/dev/qlnx/qlnxe/ |
H A D | ecore_init_values.h | 35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */ 36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */ 37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */ 38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */ 40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */ 41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */ 42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */ 43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */ 44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */ 45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */ [all …]
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/freebsd/sys/dev/bxe/ |
H A D | 57711_init_values.c | 55 {OP_WR, 0x600dc, 0x1}, 56 {OP_SW, 0x61000, 0x2000000}, 57 {OP_RD, 0x600d8, 0x0}, 58 {OP_SW, 0x60200, 0x30200}, 59 {OP_WR, 0x600dc, 0x0}, 62 {OP_RD, 0x600b8, 0x0}, 63 {OP_RD, 0x600c8, 0x0}, 64 {OP_WR, 0x6016c, 0x0}, 67 {OP_RD, 0x600bc, 0x0}, 68 {OP_RD, 0x600cc, 0x0}, [all …]
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H A D | 57710_init_values.c | 55 {OP_WR, 0x600dc, 0x1}, 56 {OP_SW, 0x61000, 0x2000000}, 57 {OP_RD, 0x600d8, 0x0}, 58 {OP_SW, 0x60200, 0x30200}, 59 {OP_WR, 0x600dc, 0x0}, 62 {OP_WR, 0x60068, 0xb8}, 63 {OP_WR, 0x60078, 0x114}, 64 {OP_RD, 0x600b8, 0x0}, 65 {OP_RD, 0x600c8, 0x0}, 68 {OP_WR, 0x6006c, 0xb8}, [all …]
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H A D | 57712_init_values.c | 54 /* #define ATC_COMMON_START 0 */ 55 {OP_WR, 0x1100b8, 0x1}, 58 {OP_WR, 0x600dc, 0x1}, 59 {OP_WR, 0x60050, 0x180}, 60 {OP_SW, 0x61000, 0x1ff0000}, 61 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */ 62 {OP_WR, 0x617fc, 0x3fe001}, 63 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */ 64 {OP_SW, 0x617fc, 0x20101ff}, 65 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */ [all …]
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