Lines Matching +full:0 +full:x00024000
17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
51 ranges = <0x54000000 0x54000000 0x04000000>;
55 reg = <0x54040000 0x00040000>;
67 reg = <0x54080000 0x00040000>;
79 reg = <0x540c0000 0x00040000>;
91 reg = <0x54100000 0x00040000>;
102 reg = <0x54140000 0x00040000>;
113 reg = <0x54180000 0x00040000>;
123 reg = <0x54200000 0x00040000>;
133 nvidia,head = <0>;
153 reg = <0x54240000 0x00040000>;
183 reg = <0x54280000 0x00040000>;
192 #sound-dai-cells = <0>;
198 reg = <0x542c0000 0x00040000>;
208 reg = <0x54300000 0x00040000>;
223 reg = <0x50040600 0x20>;
231 reg = <0x50041000 0x1000>,
232 <0x50040100 0x0100>;
240 reg = <0x50043000 0x1000>;
249 reg = <0x60004000 0x100>,
250 <0x60004100 0x50>,
251 <0x60004200 0x50>,
252 <0x60004300 0x50>;
260 reg = <0x60005000 0x60>;
261 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
270 reg = <0x60006000 0x1000>;
284 reg = <0x60007000 0x1000>;
289 reg = <0x6000a000 0x1200>;
314 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
319 reg = <0x6000d000 0x1000>;
331 gpio-ranges = <&pinmux 0 0 224>;
336 reg = <0x6001a000 0x1000>, /* Syntax Engine */
337 <0x6001b000 0x1000>, /* Video Bitstream Engine */
338 <0x6001c000 0x100>, /* Macroblock Engine */
339 <0x6001c200 0x100>, /* Post-processing Engine */
340 <0x6001c400 0x100>, /* Motion Compensation Engine */
341 <0x6001c600 0x100>, /* Transform Engine */
342 <0x6001c800 0x100>, /* Pixel prediction block */
343 <0x6001ca00 0x100>, /* Video DMA */
344 <0x6001d800 0x300>; /* Video frame controls */
361 reg = <0x70000014 0x10>, /* Tri-state registers */
362 <0x70000080 0x20>, /* Mux registers */
363 <0x700000a0 0x14>, /* Pull-up/down registers */
364 <0x70000868 0xa8>; /* Pad control registers */
369 reg = <0x70000800 0x64>, /* Chip revision */
370 <0x70000008 0x04>; /* Strapping options */
375 reg = <0x70000c00 0x80>;
380 reg = <0x70002000 0x200>;
392 reg = <0x70002400 0x200>;
400 #sound-dai-cells = <0>;
409 reg = <0x70002800 0x200>;
421 reg = <0x70002a00 0x200>;
440 reg = <0x70006000 0x40>;
452 reg = <0x70006040 0x40>;
464 reg = <0x70006200 0x100>;
476 reg = <0x70006300 0x100>;
488 reg = <0x70006400 0x100>;
500 reg = <0x70008000 0x100>;
502 #size-cells = <0>;
517 reg = <0x70009000 0x1000>;
520 ranges = <0 0 0xd0000000 0xfffffff>;
532 reg = <0x7000a000 0x100>;
542 reg = <0x7000c000 0x100>;
545 #size-cells = <0>;
558 reg = <0x7000c380 0x80>;
561 #size-cells = <0>;
572 reg = <0x7000c400 0x100>;
575 #size-cells = <0>;
588 reg = <0x7000c500 0x100>;
591 #size-cells = <0>;
604 reg = <0x7000d000 0x200>;
607 #size-cells = <0>;
620 reg = <0x7000d400 0x200>;
623 #size-cells = <0>;
634 reg = <0x7000d600 0x200>;
637 #size-cells = <0>;
648 reg = <0x7000d800 0x200>;
651 #size-cells = <0>;
662 reg = <0x7000da00 0x200>;
665 #size-cells = <0>;
676 reg = <0x7000e000 0x100>;
683 reg = <0x7000e200 0x100>;
693 reg = <0x7000e400 0x400>;
699 #power-domain-cells = <0>;
711 #power-domain-cells = <0>;
719 #power-domain-cells = <0>;
727 #power-domain-cells = <0>;
740 #power-domain-cells = <0>;
747 reg = <0x7000f000 0x00000400>, /* controller registers */
748 <0x58000000 0x02000000>; /* GART aperture */
753 #iommu-cells = <0>;
759 reg = <0x7000f400 0x400>;
764 #size-cells = <0>;
765 #interconnect-cells = <0>;
773 reg = <0x7000f800 0x400>;
783 reg = <0x80003000 0x00000800>, /* PADS registers */
784 <0x80003800 0x00000200>, /* AFI registers */
785 <0x90000000 0x10000000>; /* configuration space */
792 interrupt-map-mask = <0 0 0 0>;
793 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
795 bus-range = <0x00 0xff>;
799 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
800 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
801 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
802 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
803 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
818 pci@1,0 {
820 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
821 reg = <0x000800 0 0 0 0>;
822 bus-range = <0x00 0xff>;
832 pci@2,0 {
834 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
835 reg = <0x001000 0 0 0 0>;
836 bus-range = <0x00 0xff>;
849 reg = <0xc5000000 0x4000>;
864 reg = <0xc5000000 0x4000>,
865 <0xc5000000 0x4000>;
875 #phy-cells = <0>;
885 nvidia,pmc = <&tegra_pmc 0>;
891 reg = <0xc5004000 0x4000>;
905 reg = <0xc5004000 0x4000>;
914 #phy-cells = <0>;
921 reg = <0xc5008000 0x4000>;
935 reg = <0xc5008000 0x4000>,
936 <0xc5000000 0x4000>;
946 #phy-cells = <0>;
960 reg = <0xc8000000 0x200>;
973 reg = <0xc8000200 0x200>;
986 reg = <0xc8000400 0x200>;
999 reg = <0xc8000600 0x200>;
1012 #size-cells = <0>;
1014 cpu@0 {
1017 reg = <0>;
1033 interrupt-affinity = <&{/cpus/cpu@0}>,
1042 #size-cells = <0>;
1044 simple-audio-card,dai-link@0 {
1045 reg = <0>;