Lines Matching +full:0 +full:x00024000
26 ranges = <0x00000000 0x18000000 0x00001000>;
32 reg = <0x0300 0x100>;
40 reg = <0x0400 0x100>;
44 pinctrl-0 = <&pinmux_uart1>;
51 ranges = <0x00000000 0x19000000 0x00023000>;
57 reg = <0x20000 0x100>;
62 reg = <0x20200 0x100>;
69 reg = <0x20600 0x20>;
78 #address-cells = <0>;
80 reg = <0x21000 0x1000>,
81 <0x20100 0x100>;
86 reg = <0x22000 0x1000>;
97 reg = <0x18000000 0x1000>;
98 ranges = <0x00000000 0x18000000 0x00100000>;
103 interrupt-map-mask = <0x000fffff 0xffff>;
106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
114 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
115 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
116 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
117 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
118 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
119 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
120 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
121 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
123 /* PCIe Controller 0 */
124 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
125 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
126 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
127 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
128 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
129 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
132 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
133 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
134 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
135 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
136 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
137 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
140 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
141 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
142 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
143 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
144 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
145 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
148 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
151 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
153 /* Ethernet Controller 0 */
154 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
157 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
160 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
163 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
166 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
175 chipcommon: chipcommon@0 {
176 reg = <0x00000000 0x1000>;
185 reg = <0x00012000 0x1000>;
192 reg = <0x00013000 0x1000>;
199 reg = <0x00014000 0x1000>;
206 reg = <0x00021000 0x1000>;
216 reg = <0x00021000 0x1000>;
221 #size-cells = <0>;
225 #trigger-source-cells = <0>;
230 #trigger-source-cells = <0>;
236 reg = <0x00022000 0x1000>;
240 #size-cells = <0>;
244 #trigger-source-cells = <0>;
249 #trigger-source-cells = <0>;
255 reg = <0x00023000 0x1000>;
265 reg = <0x00023000 0x1000>;
271 #size-cells = <0>;
275 #trigger-source-cells = <0>;
281 reg = <0x24000 0x800>;
291 reg = <0x25000 0x800>;
301 reg = <0x26000 0x800>;
311 reg = <0x27000 0x800>;
317 reg = <0x18002000 0x28>;
325 reg = <0x18003000 0x8>;
326 #size-cells = <0>;
334 #size-cells = <0>;
335 reg = <0x18003000 0x4>;
336 mux-mask = <0x200>;
338 mdio@0 {
339 reg = <0x0>;
341 #size-cells = <0>;
345 reg = <0x10>;
347 #phy-cells = <0>;
355 reg = <0x18004000 0x14>;
360 reg = <0x18007000 0x1000>;
366 #size-cells = <0>;
368 port@0 {
369 reg = <0>;
412 reg = <0x18008000 0x20>;
421 ranges = <0 0x1800c000 0x1000>;
427 reg = <0x100 0x1a4>;
434 reg = <0x164 0x4>;
438 #phy-cells = <0>;
443 reg = <0x180 0x4>;
448 reg = <0x1c0 0x24>;
475 reg = <0x2c0 0x10>;
476 #thermal-sensor-cells = <0>;
483 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
488 #size-cells = <0>;
494 reg = <0x18105000 0x1000>;
499 polling-delay-passive = <0>;
507 hysteresis = <0>;