Lines Matching +full:0 +full:x00024000
1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
21 <0x00000800 0x00000800 0x000800>, /* ap 1 */
22 <0x00001000 0x00001000 0x001000>, /* ap 2 */
23 <0x00002000 0x00002000 0x002000>, /* ap 3 */
24 <0x00004000 0x00004000 0x001000>, /* ap 4 */
25 <0x00005000 0x00005000 0x001000>, /* ap 5 */
26 <0x00006000 0x00006000 0x001000>, /* ap 6 */
27 <0x00008000 0x00008000 0x002000>, /* ap 7 */
28 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
29 <0x00056000 0x00056000 0x001000>, /* ap 9 */
30 <0x00057000 0x00057000 0x001000>, /* ap 10 */
31 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
32 <0x00060000 0x00060000 0x001000>, /* ap 12 */
33 <0x00080000 0x00080000 0x008000>, /* ap 13 */
34 <0x00088000 0x00088000 0x001000>, /* ap 14 */
35 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
36 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
37 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
38 <0x000da000 0x000da000 0x001000>, /* ap 18 */
39 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
40 <0x000de000 0x000de000 0x001000>, /* ap 20 */
41 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
42 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
43 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
44 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
45 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
46 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
47 <0x00090000 0x00090000 0x008000>, /* ap 59 */
48 <0x00098000 0x00098000 0x001000>; /* ap 60 */
50 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
52 reg = <0x2000 0x4>;
56 ranges = <0x0 0x2000 0x2000>;
58 scm: scm@0 {
60 reg = <0 0x2000>;
63 ranges = <0 0 0x2000>;
65 scm_conf: scm_conf@0 {
67 reg = <0x0 0x1400>;
70 ranges = <0 0x0 0x1400>;
74 reg = <0xe00 0x4>;
85 reg = <0x554 0x4>;
91 #size-cells = <0>;
98 reg = <0x1400 0x0468>;
100 #size-cells = <0>;
105 pinctrl-single,function-mask = <0x3fffffff>;
110 reg = <0x1c04 0x0020>;
116 reg = <0x1c24 0x0024>;
121 reg = <0xb78 0xfc>;
124 ti,dma-safe-map = <0>;
130 reg = <0xc78 0x7c>;
133 ti,dma-safe-map = <0>;
139 target-module@5000 { /* 0x4a005000, ap 5 10.0 */
141 reg = <0x5000 0x4>;
145 ranges = <0x0 0x5000 0x1000>;
147 cm_core_aon: cm_core_aon@0 {
152 reg = <0 0x2000>;
153 ranges = <0 0 0x2000>;
157 #size-cells = <0>;
165 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
167 reg = <0x8000 0x4>;
171 ranges = <0x0 0x8000 0x2000>;
173 cm_core: cm_core@0 {
177 reg = <0 0x3000>;
178 ranges = <0 0 0x3000>;
182 #size-cells = <0>;
190 target-module@56000 { /* 0x4a056000, ap 9 02.0 */
192 reg = <0x56000 0x4>,
193 <0x5602c 0x4>,
194 <0x56028 0x4>;
210 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
214 ranges = <0x0 0x56000 0x1000>;
216 sdma: dma-controller@0 {
218 reg = <0x0 0x1000>;
229 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
234 ranges = <0x0 0x5e000 0x2000>;
237 target-module@80000 { /* 0x4a080000, ap 13 20.0 */
239 reg = <0x80000 0x4>,
240 <0x80010 0x4>,
241 <0x80014 0x4>;
250 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
254 ranges = <0x0 0x80000 0x8000>;
256 ocp2scp@0 {
260 ranges = <0 0 0x8000>;
261 reg = <0x0 0x20>;
265 reg = <0x4000 0x400>;
266 syscon-phy-power = <&scm_conf 0x300>;
271 #phy-cells = <0>;
277 reg = <0x5000 0x400>;
278 syscon-phy-power = <&scm_conf 0xe74>;
283 #phy-cells = <0>;
288 reg = <0x4400 0x80>,
289 <0x4800 0x64>,
290 <0x4c00 0x40>;
292 syscon-phy-power = <&scm_conf 0x370>;
299 #phy-cells = <0>;
304 target-module@90000 { /* 0x4a090000, ap 59 42.0 */
306 reg = <0x90000 0x4>,
307 <0x90010 0x4>,
308 <0x90014 0x4>;
317 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
321 ranges = <0x0 0x90000 0x8000>;
323 ocp2scp@0 {
327 ranges = <0 0 0x8000>;
328 reg = <0x0 0x20>;
332 reg = <0x4000 0x80>, /* phy_rx */
333 <0x4400 0x64>; /* phy_tx */
335 syscon-phy-power = <&scm_conf_pcie 0x1c>;
336 syscon-pcs = <&scm_conf_pcie 0x10>;
347 #phy-cells = <0>;
352 reg = <0x5000 0x80>, /* phy_rx */
353 <0x5400 0x64>; /* phy_tx */
355 syscon-phy-power = <&scm_conf_pcie 0x20>;
356 syscon-pcs = <&scm_conf_pcie 0x10>;
367 #phy-cells = <0>;
373 reg = <0x6000 0x80>, /* phy_rx */
374 <0x6400 0x64>, /* phy_tx */
375 <0x6800 0x40>; /* pll_ctrl */
377 syscon-phy-power = <&scm_conf 0x374>;
381 syscon-pllreset = <&scm_conf 0x3fc>;
382 #phy-cells = <0>;
387 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
392 ranges = <0x0 0xa0000 0x8000>;
395 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
397 reg = <0xd9038 0x4>;
405 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
409 ranges = <0x0 0xd9000 0x1000>;
414 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
416 reg = <0xdd038 0x4>;
424 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
428 ranges = <0x0 0xdd000 0x1000>;
433 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
438 ranges = <0x0 0xe0000 0x1000>;
441 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
443 reg = <0xf4000 0x4>,
444 <0xf4010 0x4>;
451 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
455 ranges = <0x0 0xf4000 0x1000>;
457 mailbox1: mailbox@0 {
459 reg = <0x0 0x200>;
470 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
472 reg = <0xf6000 0x4>,
473 <0xf6010 0x4>,
474 <0xf6014 0x4>;
484 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
488 ranges = <0x0 0xf6000 0x1000>;
490 hwspinlock: spinlock@0 {
492 reg = <0x0 0x1000>;
498 segment@100000 { /* 0x4a100000 */
502 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
503 <0x00003000 0x00103000 0x001000>, /* ap 28 */
504 <0x00008000 0x00108000 0x001000>, /* ap 29 */
505 <0x00009000 0x00109000 0x001000>, /* ap 30 */
506 <0x00040000 0x00140000 0x010000>, /* ap 31 */
507 <0x00050000 0x00150000 0x001000>, /* ap 32 */
508 <0x00051000 0x00151000 0x001000>, /* ap 33 */
509 <0x00052000 0x00152000 0x001000>, /* ap 34 */
510 <0x00053000 0x00153000 0x001000>, /* ap 35 */
511 <0x00054000 0x00154000 0x001000>, /* ap 36 */
512 <0x00055000 0x00155000 0x001000>, /* ap 37 */
513 <0x00056000 0x00156000 0x001000>, /* ap 38 */
514 <0x00057000 0x00157000 0x001000>, /* ap 39 */
515 <0x00058000 0x00158000 0x001000>, /* ap 40 */
516 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
517 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
518 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
519 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
520 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
521 <0x00060000 0x00160000 0x001000>, /* ap 48 */
522 <0x00061000 0x00161000 0x001000>, /* ap 49 */
523 <0x00062000 0x00162000 0x001000>, /* ap 50 */
524 <0x00063000 0x00163000 0x001000>, /* ap 51 */
525 <0x00064000 0x00164000 0x001000>, /* ap 52 */
526 <0x00065000 0x00165000 0x001000>, /* ap 53 */
527 <0x00066000 0x00166000 0x001000>, /* ap 54 */
528 <0x00067000 0x00167000 0x001000>, /* ap 55 */
529 <0x00068000 0x00168000 0x001000>, /* ap 56 */
530 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
531 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
532 <0x00071000 0x00171000 0x001000>, /* ap 61 */
533 <0x00072000 0x00172000 0x001000>, /* ap 62 */
534 <0x00073000 0x00173000 0x001000>, /* ap 63 */
535 <0x00074000 0x00174000 0x001000>, /* ap 64 */
536 <0x00075000 0x00175000 0x001000>, /* ap 65 */
537 <0x00076000 0x00176000 0x001000>, /* ap 66 */
538 <0x00077000 0x00177000 0x001000>, /* ap 67 */
539 <0x00078000 0x00178000 0x001000>, /* ap 68 */
540 <0x00081000 0x00181000 0x001000>, /* ap 69 */
541 <0x00082000 0x00182000 0x001000>, /* ap 70 */
542 <0x00083000 0x00183000 0x001000>, /* ap 71 */
543 <0x00084000 0x00184000 0x001000>, /* ap 72 */
544 <0x00085000 0x00185000 0x001000>, /* ap 73 */
545 <0x00086000 0x00186000 0x001000>, /* ap 74 */
546 <0x00087000 0x00187000 0x001000>, /* ap 75 */
547 <0x00088000 0x00188000 0x001000>, /* ap 76 */
548 <0x00069000 0x00169000 0x001000>, /* ap 103 */
549 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
550 <0x00079000 0x00179000 0x001000>, /* ap 105 */
551 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
552 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
553 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
554 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
555 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
556 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
557 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
558 <0x00059000 0x00159000 0x001000>, /* ap 125 */
559 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
561 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
566 ranges = <0x0 0x2000 0x1000>;
569 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
574 ranges = <0x0 0x8000 0x1000>;
577 target-module@40000 { /* 0x4a140000, ap 31 06.0 */
579 reg = <0x400fc 4>,
580 <0x41100 4>;
590 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;
594 ranges = <0x0 0x40000 0x10000>;
596 sata: sata@0 {
598 reg = <0 0x1100>, <0x1100 0x8>;
603 ports-implemented = <0x1>;
607 target-module@51000 { /* 0x4a151000, ap 33 50.0 */
612 ranges = <0x0 0x51000 0x1000>;
615 target-module@53000 { /* 0x4a153000, ap 35 54.0 */
620 ranges = <0x0 0x53000 0x1000>;
623 target-module@55000 { /* 0x4a155000, ap 37 46.0 */
628 ranges = <0x0 0x55000 0x1000>;
631 target-module@57000 { /* 0x4a157000, ap 39 58.0 */
636 ranges = <0x0 0x57000 0x1000>;
639 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
644 ranges = <0x0 0x59000 0x1000>;
647 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
652 ranges = <0x0 0x5b000 0x1000>;
655 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
660 ranges = <0x0 0x5d000 0x1000>;
663 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
668 ranges = <0x0 0x5f000 0x1000>;
671 target-module@61000 { /* 0x4a161000, ap 49 32.0 */
676 ranges = <0x0 0x61000 0x1000>;
679 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
684 ranges = <0x0 0x63000 0x1000>;
687 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
692 ranges = <0x0 0x65000 0x1000>;
695 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
700 ranges = <0x0 0x67000 0x1000>;
703 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
708 ranges = <0x0 0x69000 0x1000>;
711 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
716 ranges = <0x0 0x6b000 0x1000>;
719 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
724 ranges = <0x0 0x6d000 0x1000>;
727 target-module@71000 { /* 0x4a171000, ap 61 48.0 */
732 ranges = <0x0 0x71000 0x1000>;
735 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
740 ranges = <0x0 0x73000 0x1000>;
743 target-module@75000 { /* 0x4a175000, ap 65 64.0 */
748 ranges = <0x0 0x75000 0x1000>;
751 target-module@77000 { /* 0x4a177000, ap 67 66.0 */
756 ranges = <0x0 0x77000 0x1000>;
759 target-module@79000 { /* 0x4a179000, ap 105 34.0 */
764 ranges = <0x0 0x79000 0x1000>;
767 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
772 ranges = <0x0 0x7b000 0x1000>;
775 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
780 ranges = <0x0 0x7d000 0x1000>;
783 target-module@81000 { /* 0x4a181000, ap 69 26.0 */
788 ranges = <0x0 0x81000 0x1000>;
791 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
796 ranges = <0x0 0x83000 0x1000>;
799 target-module@85000 { /* 0x4a185000, ap 73 36.0 */
804 ranges = <0x0 0x85000 0x1000>;
807 target-module@87000 { /* 0x4a187000, ap 75 74.0 */
812 ranges = <0x0 0x87000 0x1000>;
816 segment@200000 { /* 0x4a200000 */
820 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
821 <0x00019000 0x00219000 0x001000>, /* ap 44 */
822 <0x00000000 0x00200000 0x001000>, /* ap 77 */
823 <0x00001000 0x00201000 0x001000>, /* ap 78 */
824 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
825 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
826 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
827 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
828 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
829 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
830 <0x00010000 0x00210000 0x001000>, /* ap 85 */
831 <0x00011000 0x00211000 0x001000>, /* ap 86 */
832 <0x00012000 0x00212000 0x001000>, /* ap 87 */
833 <0x00013000 0x00213000 0x001000>, /* ap 88 */
834 <0x00014000 0x00214000 0x001000>, /* ap 89 */
835 <0x00015000 0x00215000 0x001000>, /* ap 90 */
836 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
837 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
838 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
839 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
840 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
841 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
842 <0x00020000 0x00220000 0x001000>, /* ap 97 */
843 <0x00021000 0x00221000 0x001000>, /* ap 98 */
844 <0x00024000 0x00224000 0x001000>, /* ap 99 */
845 <0x00025000 0x00225000 0x001000>, /* ap 100 */
846 <0x00026000 0x00226000 0x001000>, /* ap 101 */
847 <0x00027000 0x00227000 0x001000>, /* ap 102 */
848 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
849 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
850 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
851 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
852 <0x00030000 0x00230000 0x001000>, /* ap 113 */
853 <0x00031000 0x00231000 0x001000>, /* ap 114 */
854 <0x00032000 0x00232000 0x001000>, /* ap 115 */
855 <0x00033000 0x00233000 0x001000>, /* ap 116 */
856 <0x00034000 0x00234000 0x001000>, /* ap 117 */
857 <0x00035000 0x00235000 0x001000>, /* ap 118 */
858 <0x00036000 0x00236000 0x001000>, /* ap 119 */
859 <0x00037000 0x00237000 0x001000>, /* ap 120 */
860 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
861 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
863 target-module@0 { /* 0x4a200000, ap 77 3e.0 */
868 ranges = <0x0 0x0 0x1000>;
871 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
876 ranges = <0x0 0xa000 0x1000>;
879 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
884 ranges = <0x0 0xc000 0x1000>;
887 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
892 ranges = <0x0 0xe000 0x1000>;
895 target-module@10000 { /* 0x4a210000, ap 85 14.0 */
900 ranges = <0x0 0x10000 0x1000>;
903 target-module@12000 { /* 0x4a212000, ap 87 16.0 */
908 ranges = <0x0 0x12000 0x1000>;
911 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
916 ranges = <0x0 0x14000 0x1000>;
919 target-module@18000 { /* 0x4a218000, ap 43 12.0 */
924 ranges = <0x0 0x18000 0x1000>;
927 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
932 ranges = <0x0 0x1a000 0x1000>;
935 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
940 ranges = <0x0 0x1c000 0x1000>;
943 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
948 ranges = <0x0 0x1e000 0x1000>;
951 target-module@20000 { /* 0x4a220000, ap 97 24.0 */
956 ranges = <0x0 0x20000 0x1000>;
959 target-module@24000 { /* 0x4a224000, ap 99 44.0 */
964 ranges = <0x0 0x24000 0x1000>;
967 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
972 ranges = <0x0 0x26000 0x1000>;
975 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
980 ranges = <0x0 0x2a000 0x1000>;
983 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
988 ranges = <0x0 0x2c000 0x1000>;
991 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
996 ranges = <0x0 0x2e000 0x1000>;
999 target-module@30000 { /* 0x4a230000, ap 113 70.0 */
1004 ranges = <0x0 0x30000 0x1000>;
1007 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
1012 ranges = <0x0 0x32000 0x1000>;
1015 target-module@34000 { /* 0x4a234000, ap 117 76.1 */
1020 ranges = <0x0 0x34000 0x1000>;
1023 target-module@36000 { /* 0x4a236000, ap 119 62.0 */
1028 ranges = <0x0 0x36000 0x1000>;
1033 &l4_per1 { /* 0x48000000 */
1036 clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>;
1038 reg = <0x48000000 0x800>,
1039 <0x48000800 0x800>,
1040 <0x48001000 0x400>,
1041 <0x48001400 0x400>,
1042 <0x48001800 0x400>,
1043 <0x48001c00 0x400>;
1047 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1048 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1050 segment@0 { /* 0x48000000 */
1054 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1055 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1056 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1057 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1058 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1059 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1060 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1061 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1062 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1063 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1064 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1065 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1066 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1067 <0x00055000 0x00055000 0x001000>, /* ap 13 */
1068 <0x00056000 0x00056000 0x001000>, /* ap 14 */
1069 <0x00057000 0x00057000 0x001000>, /* ap 15 */
1070 <0x00058000 0x00058000 0x001000>, /* ap 16 */
1071 <0x00059000 0x00059000 0x001000>, /* ap 17 */
1072 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1073 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1074 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1075 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1076 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1077 <0x00060000 0x00060000 0x001000>, /* ap 23 */
1078 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1079 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1080 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1081 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1082 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1083 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1084 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1085 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1086 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1087 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1088 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1089 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1090 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1091 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1092 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1093 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1094 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1095 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1096 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1097 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1098 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1099 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1100 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1101 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1102 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1103 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1104 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1105 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1106 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1107 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1108 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1109 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1110 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1111 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1112 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1113 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1114 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1115 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1116 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1117 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1118 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1119 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1120 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1121 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1122 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1123 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1124 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1125 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1126 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1127 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1128 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1129 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1130 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1131 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1132 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1133 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1134 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1135 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1136 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1137 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1138 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1140 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1142 reg = <0x20050 0x4>,
1143 <0x20054 0x4>,
1144 <0x20058 0x4>;
1155 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1159 ranges = <0x0 0x20000 0x1000>;
1161 uart3: serial@0 {
1163 reg = <0x0 0x100>;
1172 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1174 reg = <0x32000 0x4>,
1175 <0x32010 0x4>;
1184 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1188 ranges = <0x0 0x32000 0x1000>;
1190 timer2: timer@0 {
1192 reg = <0x0 0x80>;
1199 timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */
1201 reg = <0x34000 0x4>,
1202 <0x34010 0x4>;
1211 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1215 ranges = <0x0 0x34000 0x1000>;
1217 timer3: timer@0 {
1219 reg = <0x0 0x80>;
1226 timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1228 reg = <0x36000 0x4>,
1229 <0x36010 0x4>;
1238 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1242 ranges = <0x0 0x36000 0x1000>;
1244 timer4: timer@0 {
1246 reg = <0x0 0x80>;
1253 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1255 reg = <0x3e000 0x4>,
1256 <0x3e010 0x4>;
1265 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1269 ranges = <0x0 0x3e000 0x1000>;
1271 timer9: timer@0 {
1273 reg = <0x0 0x80>;
1280 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1282 reg = <0x51000 0x4>,
1283 <0x51010 0x4>,
1284 <0x51114 0x4>;
1295 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1300 ranges = <0x0 0x51000 0x1000>;
1302 gpio7: gpio@0 {
1304 reg = <0x0 0x200>;
1313 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1315 reg = <0x53000 0x4>,
1316 <0x53010 0x4>,
1317 <0x53114 0x4>;
1328 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1333 ranges = <0x0 0x53000 0x1000>;
1335 gpio8: gpio@0 {
1337 reg = <0x0 0x200>;
1346 gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1348 reg = <0x55000 0x4>,
1349 <0x55010 0x4>,
1350 <0x55114 0x4>;
1361 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1366 ranges = <0x0 0x55000 0x1000>;
1368 gpio2: gpio@0 {
1370 reg = <0x0 0x200>;
1379 gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */
1381 reg = <0x57000 0x4>,
1382 <0x57010 0x4>,
1383 <0x57114 0x4>;
1394 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1399 ranges = <0x0 0x57000 0x1000>;
1401 gpio3: gpio@0 {
1403 reg = <0x0 0x200>;
1412 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1414 reg = <0x59000 0x4>,
1415 <0x59010 0x4>,
1416 <0x59114 0x4>;
1427 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1432 ranges = <0x0 0x59000 0x1000>;
1434 gpio4: gpio@0 {
1436 reg = <0x0 0x200>;
1445 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1447 reg = <0x5b000 0x4>,
1448 <0x5b010 0x4>,
1449 <0x5b114 0x4>;
1460 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1465 ranges = <0x0 0x5b000 0x1000>;
1467 gpio5: gpio@0 {
1469 reg = <0x0 0x200>;
1478 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1480 reg = <0x5d000 0x4>,
1481 <0x5d010 0x4>,
1482 <0x5d114 0x4>;
1493 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1498 ranges = <0x0 0x5d000 0x1000>;
1500 gpio6: gpio@0 {
1502 reg = <0x0 0x200>;
1511 target-module@60000 { /* 0x48060000, ap 23 32.0 */
1513 reg = <0x60000 0x8>,
1514 <0x60010 0x8>,
1515 <0x60090 0x8>;
1527 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1531 ranges = <0x0 0x60000 0x1000>;
1533 i2c3: i2c@0 {
1535 reg = <0x0 0x100>;
1538 #size-cells = <0>;
1543 target-module@66000 { /* 0x48066000, ap 63 14.0 */
1545 reg = <0x66050 0x4>,
1546 <0x66054 0x4>,
1547 <0x66058 0x4>;
1558 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1562 ranges = <0x0 0x66000 0x1000>;
1564 uart5: serial@0 {
1566 reg = <0x0 0x100>;
1575 target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1577 reg = <0x68050 0x4>,
1578 <0x68054 0x4>,
1579 <0x68058 0x4>;
1590 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1594 ranges = <0x0 0x68000 0x1000>;
1596 uart6: serial@0 {
1598 reg = <0x0 0x100>;
1607 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1609 reg = <0x6a050 0x4>,
1610 <0x6a054 0x4>,
1611 <0x6a058 0x4>;
1622 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1626 ranges = <0x0 0x6a000 0x1000>;
1628 uart1: serial@0 {
1630 reg = <0x0 0x100>;
1639 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1641 reg = <0x6c050 0x4>,
1642 <0x6c054 0x4>,
1643 <0x6c058 0x4>;
1654 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1658 ranges = <0x0 0x6c000 0x1000>;
1660 uart2: serial@0 {
1662 reg = <0x0 0x100>;
1671 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1673 reg = <0x6e050 0x4>,
1674 <0x6e054 0x4>,
1675 <0x6e058 0x4>;
1686 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1690 ranges = <0x0 0x6e000 0x1000>;
1692 uart4: serial@0 {
1694 reg = <0x0 0x100>;
1703 target-module@70000 { /* 0x48070000, ap 30 22.0 */
1705 reg = <0x70000 0x8>,
1706 <0x70010 0x8>,
1707 <0x70090 0x8>;
1719 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1723 ranges = <0x0 0x70000 0x1000>;
1725 i2c1: i2c@0 {
1727 reg = <0x0 0x100>;
1730 #size-cells = <0>;
1735 target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1737 reg = <0x72000 0x8>,
1738 <0x72010 0x8>,
1739 <0x72090 0x8>;
1751 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1755 ranges = <0x0 0x72000 0x1000>;
1757 i2c2: i2c@0 {
1759 reg = <0x0 0x100>;
1762 #size-cells = <0>;
1767 target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1769 reg = <0x78000 0x4>,
1770 <0x78010 0x4>,
1771 <0x78014 0x4>;
1782 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1786 ranges = <0x0 0x78000 0x1000>;
1788 elm: elm@0 {
1790 reg = <0x0 0xfc0>; /* device IO registers */
1796 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1798 reg = <0x7a000 0x8>,
1799 <0x7a010 0x8>,
1800 <0x7a090 0x8>;
1812 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1816 ranges = <0x0 0x7a000 0x1000>;
1818 i2c4: i2c@0 {
1820 reg = <0x0 0x100>;
1823 #size-cells = <0>;
1828 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1830 reg = <0x7c000 0x8>,
1831 <0x7c010 0x8>,
1832 <0x7c090 0x8>;
1844 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1848 ranges = <0x0 0x7c000 0x1000>;
1850 i2c5: i2c@0 {
1852 reg = <0x0 0x100>;
1855 #size-cells = <0>;
1860 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1862 reg = <0x86000 0x4>,
1863 <0x86010 0x4>;
1872 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1876 ranges = <0x0 0x86000 0x1000>;
1878 timer10: timer@0 {
1880 reg = <0x0 0x80>;
1887 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1889 reg = <0x88000 0x4>,
1890 <0x88010 0x4>;
1899 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1903 ranges = <0x0 0x88000 0x1000>;
1905 timer11: timer@0 {
1907 reg = <0x0 0x80>;
1914 target-module@90000 { /* 0x48090000, ap 55 12.0 */
1916 reg = <0x91fe0 0x4>,
1917 <0x91fe4 0x4>;
1923 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1927 ranges = <0x0 0x90000 0x2000>;
1929 rng: rng@0 {
1931 reg = <0x0 0x2000>;
1938 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1940 reg = <0x98000 0x4>,
1941 <0x98010 0x4>;
1950 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1954 ranges = <0x0 0x98000 0x1000>;
1956 mcspi1: spi@0 {
1958 reg = <0x0 0x200>;
1961 #size-cells = <0>;
1977 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1979 reg = <0x9a000 0x4>,
1980 <0x9a010 0x4>;
1989 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1993 ranges = <0x0 0x9a000 0x1000>;
1995 mcspi2: spi@0 {
1997 reg = <0x0 0x200>;
2000 #size-cells = <0>;
2011 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
2013 reg = <0x9c000 0x4>,
2014 <0x9c010 0x4>;
2027 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2031 ranges = <0x0 0x9c000 0x1000>;
2033 mmc1: mmc@0 {
2035 reg = <0x0 0x400>;
2045 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2050 ranges = <0x0 0xa2000 0x1000>;
2053 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2058 ranges = <0x00000000 0x000a4000 0x00001000>,
2059 <0x00001000 0x000a5000 0x00001000>;
2062 des_target: target-module@a5000 { /* 0x480a5000 */
2064 reg = <0xa5030 0x4>,
2065 <0xa5034 0x4>,
2066 <0xa5038 0x4>;
2076 clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2080 ranges = <0 0xa5000 0x00001000>;
2082 des: des@0 {
2084 reg = <0 0xa0>;
2093 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2098 ranges = <0x0 0xa8000 0x4000>;
2101 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2103 reg = <0xad000 0x4>,
2104 <0xad010 0x4>;
2117 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2121 ranges = <0x0 0xad000 0x1000>;
2123 mmc3: mmc@0 {
2125 reg = <0x0 0x400>;
2131 sdhci-caps-mask = <0x0 0x400000>;
2135 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2137 reg = <0xb2000 0x4>,
2138 <0xb2014 0x4>,
2139 <0xb2018 0x4>;
2146 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2150 ranges = <0x0 0xb2000 0x1000>;
2152 hdqw1w: 1w@0 {
2154 reg = <0x0 0x1000>;
2159 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2161 reg = <0xb4000 0x4>,
2162 <0xb4010 0x4>;
2175 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2179 ranges = <0x0 0xb4000 0x1000>;
2181 mmc2: mmc@0 {
2183 reg = <0x0 0x400>;
2188 sdhci-caps-mask = <0x7 0x0>;
2195 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2197 reg = <0xb8000 0x4>,
2198 <0xb8010 0x4>;
2207 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2211 ranges = <0x0 0xb8000 0x1000>;
2213 mcspi3: spi@0 {
2215 reg = <0x0 0x200>;
2218 #size-cells = <0>;
2226 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2228 reg = <0xba000 0x4>,
2229 <0xba010 0x4>;
2238 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2242 ranges = <0x0 0xba000 0x1000>;
2244 mcspi4: spi@0 {
2246 reg = <0x0 0x200>;
2249 #size-cells = <0>;
2257 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2259 reg = <0xd1000 0x4>,
2260 <0xd1010 0x4>;
2273 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2277 ranges = <0x0 0xd1000 0x1000>;
2279 mmc4: mmc@0 {
2281 reg = <0x0 0x400>;
2286 sdhci-caps-mask = <0x0 0x400000>;
2290 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2295 ranges = <0x0 0xd5000 0x1000>;
2299 segment@200000 { /* 0x48200000 */
2306 &l4_per2 { /* 0x48400000 */
2309 clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;
2311 reg = <0x48400000 0x800>,
2312 <0x48400800 0x800>,
2313 <0x48401000 0x400>,
2314 <0x48401400 0x400>,
2315 <0x48401800 0x400>;
2319 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2320 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2321 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2322 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2323 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2324 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2325 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2326 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2327 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2329 segment@0 { /* 0x48400000 */
2333 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2334 <0x00001000 0x00001000 0x000400>, /* ap 1 */
2335 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2336 <0x00084000 0x00084000 0x004000>, /* ap 3 */
2337 <0x00001400 0x00001400 0x000400>, /* ap 4 */
2338 <0x00001800 0x00001800 0x000400>, /* ap 5 */
2339 <0x00088000 0x00088000 0x001000>, /* ap 6 */
2340 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2341 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2342 <0x00060000 0x00060000 0x002000>, /* ap 9 */
2343 <0x00062000 0x00062000 0x001000>, /* ap 10 */
2344 <0x00064000 0x00064000 0x002000>, /* ap 11 */
2345 <0x00066000 0x00066000 0x001000>, /* ap 12 */
2346 <0x00068000 0x00068000 0x002000>, /* ap 13 */
2347 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2348 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2349 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2350 <0x00036000 0x00036000 0x001000>, /* ap 17 */
2351 <0x00037000 0x00037000 0x001000>, /* ap 18 */
2352 <0x00070000 0x00070000 0x002000>, /* ap 19 */
2353 <0x00072000 0x00072000 0x001000>, /* ap 20 */
2354 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2355 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2356 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2357 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2358 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2359 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2360 <0x00040000 0x00040000 0x001000>, /* ap 27 */
2361 <0x00041000 0x00041000 0x001000>, /* ap 28 */
2362 <0x00042000 0x00042000 0x001000>, /* ap 29 */
2363 <0x00043000 0x00043000 0x001000>, /* ap 30 */
2364 <0x00080000 0x00080000 0x002000>, /* ap 31 */
2365 <0x00082000 0x00082000 0x001000>, /* ap 32 */
2366 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2367 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2368 <0x00074000 0x00074000 0x002000>, /* ap 35 */
2369 <0x00076000 0x00076000 0x001000>, /* ap 36 */
2370 <0x00050000 0x00050000 0x001000>, /* ap 37 */
2371 <0x00051000 0x00051000 0x001000>, /* ap 38 */
2372 <0x00078000 0x00078000 0x002000>, /* ap 39 */
2373 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2374 <0x00054000 0x00054000 0x001000>, /* ap 41 */
2375 <0x00055000 0x00055000 0x001000>, /* ap 42 */
2376 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2377 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2378 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2379 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2380 <0x00020000 0x00020000 0x001000>, /* ap 47 */
2381 <0x00021000 0x00021000 0x001000>, /* ap 48 */
2382 <0x00022000 0x00022000 0x001000>, /* ap 49 */
2383 <0x00023000 0x00023000 0x001000>, /* ap 50 */
2384 <0x00024000 0x00024000 0x001000>, /* ap 51 */
2385 <0x00025000 0x00025000 0x001000>, /* ap 52 */
2386 <0x00046000 0x00046000 0x001000>, /* ap 53 */
2387 <0x00047000 0x00047000 0x001000>, /* ap 54 */
2388 <0x00048000 0x00048000 0x001000>, /* ap 55 */
2389 <0x00049000 0x00049000 0x001000>, /* ap 56 */
2390 <0x00058000 0x00058000 0x002000>, /* ap 57 */
2391 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2392 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2393 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2394 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2395 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2396 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2397 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2398 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2399 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2400 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2401 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2402 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2403 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2405 target-module@20000 { /* 0x48420000, ap 47 02.0 */
2407 reg = <0x20050 0x4>,
2408 <0x20054 0x4>,
2409 <0x20058 0x4>;
2420 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2424 ranges = <0x0 0x20000 0x1000>;
2426 uart7: serial@0 {
2428 reg = <0x0 0x100>;
2435 target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2437 reg = <0x22050 0x4>,
2438 <0x22054 0x4>,
2439 <0x22058 0x4>;
2450 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2454 ranges = <0x0 0x22000 0x1000>;
2456 uart8: serial@0 {
2458 reg = <0x0 0x100>;
2465 target-module@24000 { /* 0x48424000, ap 51 12.0 */
2467 reg = <0x24050 0x4>,
2468 <0x24054 0x4>,
2469 <0x24058 0x4>;
2480 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2484 ranges = <0x0 0x24000 0x1000>;
2486 uart9: serial@0 {
2488 reg = <0x0 0x100>;
2495 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2500 ranges = <0x0 0x2c000 0x1000>;
2503 target-module@36000 { /* 0x48436000, ap 17 06.0 */
2508 ranges = <0x0 0x36000 0x1000>;
2511 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2516 ranges = <0x0 0x3a000 0x1000>;
2519 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2521 reg = <0x3c000 0x4>;
2523 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2527 ranges = <0x0 0x3c000 0x1000>;
2529 atl: atl@0 {
2531 reg = <0x0 0x3ff>;
2540 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2542 reg = <0x3e000 0x4>,
2543 <0x3e004 0x4>;
2550 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2554 ranges = <0x0 0x3e000 0x1000>;
2556 epwmss0: epwmss@0 {
2558 reg = <0x0 0x30>;
2562 ranges = <0 0 0x1000>;
2568 reg = <0x100 0x80>;
2578 reg = <0x200 0x80>;
2586 target-module@40000 { /* 0x48440000, ap 27 38.0 */
2588 reg = <0x40000 0x4>,
2589 <0x40004 0x4>;
2596 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2600 ranges = <0x0 0x40000 0x1000>;
2602 epwmss1: epwmss@0 {
2604 reg = <0x0 0x30>;
2608 ranges = <0 0 0x1000>;
2614 reg = <0x100 0x80>;
2624 reg = <0x200 0x80>;
2632 target-module@42000 { /* 0x48442000, ap 29 20.0 */
2634 reg = <0x42000 0x4>,
2635 <0x42004 0x4>;
2642 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2646 ranges = <0x0 0x42000 0x1000>;
2648 epwmss2: epwmss@0 {
2650 reg = <0x0 0x30>;
2654 ranges = <0 0 0x1000>;
2660 reg = <0x100 0x80>;
2670 reg = <0x200 0x80>;
2678 target-module@46000 { /* 0x48446000, ap 53 40.0 */
2683 ranges = <0x0 0x46000 0x1000>;
2686 target-module@48000 { /* 0x48448000, ap 55 48.0 */
2691 ranges = <0x0 0x48000 0x1000>;
2694 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2699 ranges = <0x0 0x4a000 0x1000>;
2702 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2707 ranges = <0x0 0x4c000 0x1000>;
2710 target-module@50000 { /* 0x48450000, ap 37 24.0 */
2715 ranges = <0x0 0x50000 0x1000>;
2718 target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2723 ranges = <0x0 0x54000 0x1000>;
2726 target-module@58000 { /* 0x48458000, ap 57 28.0 */
2731 ranges = <0x0 0x58000 0x2000>;
2734 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2739 ranges = <0x0 0x5b000 0x1000>;
2742 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2747 ranges = <0x0 0x5d000 0x1000>;
2750 target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2752 reg = <0x60000 0x4>,
2753 <0x60004 0x4>;
2759 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2765 ranges = <0x0 0x60000 0x2000>,
2766 <0x45800000 0x45800000 0x400000>;
2768 mcasp1: mcasp@0 {
2770 reg = <0x0 0x2000>,
2771 <0x45800000 0x1000>; /* L3 data port */
2778 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2786 target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2788 reg = <0x64000 0x4>,
2789 <0x64004 0x4>;
2795 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2801 ranges = <0x0 0x64000 0x2000>,
2802 <0x45c00000 0x45c00000 0x400000>;
2804 mcasp2: mcasp@0 {
2806 reg = <0x0 0x2000>,
2807 <0x45c00000 0x1000>; /* L3 data port */
2814 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2822 target-module@68000 { /* 0x48468000, ap 13 26.0 */
2824 reg = <0x68000 0x4>,
2825 <0x68004 0x4>;
2831 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2836 ranges = <0x0 0x68000 0x2000>,
2837 <0x46000000 0x46000000 0x400000>;
2839 mcasp3: mcasp@0 {
2841 reg = <0x0 0x2000>,
2842 <0x46000000 0x1000>; /* L3 data port */
2849 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2856 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2858 reg = <0x6c000 0x4>,
2859 <0x6c004 0x4>;
2865 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2870 ranges = <0x0 0x6c000 0x2000>,
2871 <0x48436000 0x48436000 0x400000>;
2873 mcasp4: mcasp@0 {
2875 reg = <0x0 0x2000>,
2876 <0x48436000 0x1000>; /* L3 data port */
2883 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2890 target-module@70000 { /* 0x48470000, ap 19 36.0 */
2892 reg = <0x70000 0x4>,
2893 <0x70004 0x4>;
2899 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2904 ranges = <0x0 0x70000 0x2000>,
2905 <0x4843a000 0x4843a000 0x400000>;
2907 mcasp5: mcasp@0 {
2909 reg = <0x0 0x2000>,
2910 <0x4843a000 0x1000>; /* L3 data port */
2917 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2924 target-module@74000 { /* 0x48474000, ap 35 14.0 */
2926 reg = <0x74000 0x4>,
2927 <0x74004 0x4>;
2933 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2938 ranges = <0x0 0x74000 0x2000>,
2939 <0x4844c000 0x4844c000 0x400000>;
2941 mcasp6: mcasp@0 {
2943 reg = <0x0 0x2000>,
2944 <0x4844c000 0x1000>; /* L3 data port */
2951 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2958 target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2960 reg = <0x78000 0x4>,
2961 <0x78004 0x4>;
2967 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2972 ranges = <0x0 0x78000 0x2000>,
2973 <0x48450000 0x48450000 0x400000>;
2975 mcasp7: mcasp@0 {
2977 reg = <0x0 0x2000>,
2978 <0x48450000 0x1000>; /* L3 data port */
2985 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2992 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2994 reg = <0x7c000 0x4>,
2995 <0x7c004 0x4>;
3001 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3006 ranges = <0x0 0x7c000 0x2000>,
3007 <0x48454000 0x48454000 0x400000>;
3009 mcasp8: mcasp@0 {
3011 reg = <0x0 0x2000>,
3012 <0x48454000 0x1000>; /* L3 data port */
3019 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3026 target-module@80000 { /* 0x48480000, ap 31 16.0 */
3028 reg = <0x80020 0x4>;
3030 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3034 ranges = <0x0 0x80000 0x2000>;
3036 dcan2: can@0 {
3038 reg = <0x0 0x2000>;
3039 syscon-raminit = <&scm_conf 0x558 1>;
3046 target-module@84000 { /* 0x48484000, ap 3 10.0 */
3048 reg = <0x85200 0x4>,
3049 <0x85208 0x4>,
3050 <0x85204 0x4>;
3052 ti,sysc-mask = <0>;
3058 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3062 ranges = <0x0 0x84000 0x4000>;
3072 mac_sw: switch@0 {
3074 reg = <0x0 0x4000>;
3075 ranges = <0 0 0x4000>;
3091 #size-cells = <0>;
3113 #size-cells = <0>;
3115 reg = <0x1000 0x100>;
3127 &l4_per3 { /* 0x48800000 */
3130 clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>;
3132 reg = <0x48800000 0x800>,
3133 <0x48800800 0x800>,
3134 <0x48801000 0x400>,
3135 <0x48801400 0x400>,
3136 <0x48801800 0x400>;
3140 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3142 segment@0 { /* 0x48800000 */
3146 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3147 <0x00000800 0x00000800 0x000800>, /* ap 1 */
3148 <0x00001000 0x00001000 0x000400>, /* ap 2 */
3149 <0x00001400 0x00001400 0x000400>, /* ap 3 */
3150 <0x00001800 0x00001800 0x000400>, /* ap 4 */
3151 <0x00020000 0x00020000 0x001000>, /* ap 5 */
3152 <0x00021000 0x00021000 0x001000>, /* ap 6 */
3153 <0x00022000 0x00022000 0x001000>, /* ap 7 */
3154 <0x00023000 0x00023000 0x001000>, /* ap 8 */
3155 <0x00024000 0x00024000 0x001000>, /* ap 9 */
3156 <0x00025000 0x00025000 0x001000>, /* ap 10 */
3157 <0x00026000 0x00026000 0x001000>, /* ap 11 */
3158 <0x00027000 0x00027000 0x001000>, /* ap 12 */
3159 <0x00028000 0x00028000 0x001000>, /* ap 13 */
3160 <0x00029000 0x00029000 0x001000>, /* ap 14 */
3161 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */
3162 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */
3163 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */
3164 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */
3165 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */
3166 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */
3167 <0x00170000 0x00170000 0x010000>, /* ap 21 */
3168 <0x00180000 0x00180000 0x001000>, /* ap 22 */
3169 <0x00190000 0x00190000 0x010000>, /* ap 23 */
3170 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */
3171 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */
3172 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */
3173 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */
3174 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */
3175 <0x00038000 0x00038000 0x001000>, /* ap 29 */
3176 <0x00039000 0x00039000 0x001000>, /* ap 30 */
3177 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */
3178 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */
3179 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */
3180 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */
3181 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */
3182 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */
3183 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */
3184 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */
3185 <0x00040000 0x00040000 0x001000>, /* ap 39 */
3186 <0x00041000 0x00041000 0x001000>, /* ap 40 */
3187 <0x00042000 0x00042000 0x001000>, /* ap 41 */
3188 <0x00043000 0x00043000 0x001000>, /* ap 42 */
3189 <0x00044000 0x00044000 0x001000>, /* ap 43 */
3190 <0x00045000 0x00045000 0x001000>, /* ap 44 */
3191 <0x00046000 0x00046000 0x001000>, /* ap 45 */
3192 <0x00047000 0x00047000 0x001000>, /* ap 46 */
3193 <0x00048000 0x00048000 0x001000>, /* ap 47 */
3194 <0x00049000 0x00049000 0x001000>, /* ap 48 */
3195 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */
3196 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */
3197 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */
3198 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */
3199 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */
3200 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */
3201 <0x00050000 0x00050000 0x001000>, /* ap 55 */
3202 <0x00051000 0x00051000 0x001000>, /* ap 56 */
3203 <0x00052000 0x00052000 0x001000>, /* ap 57 */
3204 <0x00053000 0x00053000 0x001000>, /* ap 58 */
3205 <0x00054000 0x00054000 0x001000>, /* ap 59 */
3206 <0x00055000 0x00055000 0x001000>, /* ap 60 */
3207 <0x00056000 0x00056000 0x001000>, /* ap 61 */
3208 <0x00057000 0x00057000 0x001000>, /* ap 62 */
3209 <0x00058000 0x00058000 0x001000>, /* ap 63 */
3210 <0x00059000 0x00059000 0x001000>, /* ap 64 */
3211 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */
3212 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */
3213 <0x00064000 0x00064000 0x001000>, /* ap 67 */
3214 <0x00065000 0x00065000 0x001000>, /* ap 68 */
3215 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */
3216 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */
3217 <0x00060000 0x00060000 0x001000>, /* ap 71 */
3218 <0x00061000 0x00061000 0x001000>, /* ap 72 */
3219 <0x00062000 0x00062000 0x001000>, /* ap 73 */
3220 <0x00063000 0x00063000 0x001000>, /* ap 74 */
3221 <0x00140000 0x00140000 0x020000>, /* ap 75 */
3222 <0x00160000 0x00160000 0x001000>, /* ap 76 */
3223 <0x00016000 0x00016000 0x001000>, /* ap 77 */
3224 <0x00017000 0x00017000 0x001000>, /* ap 78 */
3225 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */
3226 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */
3227 <0x00004000 0x00004000 0x001000>, /* ap 81 */
3228 <0x00005000 0x00005000 0x001000>, /* ap 82 */
3229 <0x00080000 0x00080000 0x020000>, /* ap 83 */
3230 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */
3231 <0x00100000 0x00100000 0x020000>, /* ap 85 */
3232 <0x00120000 0x00120000 0x001000>, /* ap 86 */
3233 <0x00010000 0x00010000 0x001000>, /* ap 87 */
3234 <0x00011000 0x00011000 0x001000>, /* ap 88 */
3235 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */
3236 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */
3237 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */
3238 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */
3239 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */
3240 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */
3241 <0x00002000 0x00002000 0x001000>, /* ap 95 */
3242 <0x00003000 0x00003000 0x001000>; /* ap 96 */
3244 target-module@2000 { /* 0x48802000, ap 95 7c.0 */
3246 reg = <0x2000 0x4>,
3247 <0x2010 0x4>;
3254 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3258 ranges = <0x0 0x2000 0x1000>;
3260 mailbox13: mailbox@0 {
3262 reg = <0x0 0x200>;
3274 target-module@4000 { /* 0x48804000, ap 81 20.0 */
3279 ranges = <0x0 0x4000 0x1000>;
3282 target-module@a000 { /* 0x4880a000, ap 89 18.0 */
3287 ranges = <0x0 0xa000 0x1000>;
3290 target-module@10000 { /* 0x48810000, ap 87 28.0 */
3295 ranges = <0x0 0x10000 0x1000>;
3298 target-module@16000 { /* 0x48816000, ap 77 1e.0 */
3303 ranges = <0x0 0x16000 0x1000>;
3306 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
3311 ranges = <0x0 0x1c000 0x1000>;
3314 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
3319 ranges = <0x0 0x1e000 0x1000>;
3322 target-module@20000 { /* 0x48820000, ap 5 08.0 */
3324 reg = <0x20000 0x4>,
3325 <0x20010 0x4>;
3334 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3338 ranges = <0x0 0x20000 0x1000>;
3340 timer5: timer@0 {
3342 reg = <0x0 0x80>;
3349 target-module@22000 { /* 0x48822000, ap 7 24.0 */
3351 reg = <0x22000 0x4>,
3352 <0x22010 0x4>;
3361 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3365 ranges = <0x0 0x22000 0x1000>;
3367 timer6: timer@0 {
3369 reg = <0x0 0x80>;
3376 target-module@24000 { /* 0x48824000, ap 9 26.0 */
3378 reg = <0x24000 0x4>,
3379 <0x24010 0x4>;
3388 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3392 ranges = <0x0 0x24000 0x1000>;
3394 timer7: timer@0 {
3396 reg = <0x0 0x80>;
3403 target-module@26000 { /* 0x48826000, ap 11 0c.0 */
3405 reg = <0x26000 0x4>,
3406 <0x26010 0x4>;
3415 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3419 ranges = <0x0 0x26000 0x1000>;
3421 timer8: timer@0 {
3423 reg = <0x0 0x80>;
3430 target-module@28000 { /* 0x48828000, ap 13 16.0 */
3432 reg = <0x28000 0x4>,
3433 <0x28010 0x4>;
3442 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3446 ranges = <0x0 0x28000 0x1000>;
3448 timer13: timer@0 {
3450 reg = <0x0 0x80>;
3458 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
3460 reg = <0x2a000 0x4>,
3461 <0x2a010 0x4>;
3470 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3474 ranges = <0x0 0x2a000 0x1000>;
3476 timer14: timer@0 {
3478 reg = <0x0 0x80>;
3485 timer15_target: target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
3487 reg = <0x2c000 0x4>,
3488 <0x2c010 0x4>;
3497 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3501 ranges = <0x0 0x2c000 0x1000>;
3503 timer15: timer@0 {
3505 reg = <0x0 0x80>;
3513 timer16_target: target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
3515 reg = <0x2e000 0x4>,
3516 <0x2e010 0x4>;
3525 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3529 ranges = <0x0 0x2e000 0x1000>;
3531 timer16: timer@0 {
3533 reg = <0x0 0x80>;
3541 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
3543 reg = <0x38074 0x4>,
3544 <0x38078 0x4>;
3551 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3555 ranges = <0x0 0x38000 0x1000>;
3557 rtc: rtc@0 {
3559 reg = <0x0 0x100>;
3566 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
3568 reg = <0x3a000 0x4>,
3569 <0x3a010 0x4>;
3576 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3580 ranges = <0x0 0x3a000 0x1000>;
3582 mailbox2: mailbox@0 {
3584 reg = <0x0 0x200>;
3596 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
3598 reg = <0x3c000 0x4>,
3599 <0x3c010 0x4>;
3606 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3610 ranges = <0x0 0x3c000 0x1000>;
3612 mailbox3: mailbox@0 {
3614 reg = <0x0 0x200>;
3626 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
3628 reg = <0x3e000 0x4>,
3629 <0x3e010 0x4>;
3636 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3640 ranges = <0x0 0x3e000 0x1000>;
3642 mailbox4: mailbox@0 {
3644 reg = <0x0 0x200>;
3656 target-module@40000 { /* 0x48840000, ap 39 64.0 */
3658 reg = <0x40000 0x4>,
3659 <0x40010 0x4>;
3666 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3670 ranges = <0x0 0x40000 0x1000>;
3672 mailbox5: mailbox@0 {
3674 reg = <0x0 0x200>;
3686 target-module@42000 { /* 0x48842000, ap 41 4e.0 */
3688 reg = <0x42000 0x4>,
3689 <0x42010 0x4>;
3696 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3700 ranges = <0x0 0x42000 0x1000>;
3702 mailbox6: mailbox@0 {
3704 reg = <0x0 0x200>;
3716 target-module@44000 { /* 0x48844000, ap 43 42.0 */
3718 reg = <0x44000 0x4>,
3719 <0x44010 0x4>;
3726 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3730 ranges = <0x0 0x44000 0x1000>;
3732 mailbox7: mailbox@0 {
3734 reg = <0x0 0x200>;
3746 target-module@46000 { /* 0x48846000, ap 45 48.0 */
3748 reg = <0x46000 0x4>,
3749 <0x46010 0x4>;
3756 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3760 ranges = <0x0 0x46000 0x1000>;
3762 mailbox8: mailbox@0 {
3764 reg = <0x0 0x200>;
3776 target-module@48000 { /* 0x48848000, ap 47 36.0 */
3781 ranges = <0x0 0x48000 0x1000>;
3784 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
3789 ranges = <0x0 0x4a000 0x1000>;
3792 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
3797 ranges = <0x0 0x4c000 0x1000>;
3800 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
3805 ranges = <0x0 0x4e000 0x1000>;
3808 target-module@50000 { /* 0x48850000, ap 55 40.0 */
3813 ranges = <0x0 0x50000 0x1000>;
3816 target-module@52000 { /* 0x48852000, ap 57 54.0 */
3821 ranges = <0x0 0x52000 0x1000>;
3824 target-module@54000 { /* 0x48854000, ap 59 1a.0 */
3829 ranges = <0x0 0x54000 0x1000>;
3832 target-module@56000 { /* 0x48856000, ap 61 22.0 */
3837 ranges = <0x0 0x56000 0x1000>;
3840 target-module@58000 { /* 0x48858000, ap 63 2a.0 */
3845 ranges = <0x0 0x58000 0x1000>;
3848 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
3853 ranges = <0x0 0x5a000 0x1000>;
3856 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
3861 ranges = <0x0 0x5c000 0x1000>;
3864 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
3866 reg = <0x5e000 0x4>,
3867 <0x5e010 0x4>;
3874 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3878 ranges = <0x0 0x5e000 0x1000>;
3880 mailbox9: mailbox@0 {
3882 reg = <0x0 0x200>;
3894 target-module@60000 { /* 0x48860000, ap 71 4a.0 */
3896 reg = <0x60000 0x4>,
3897 <0x60010 0x4>;
3904 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3908 ranges = <0x0 0x60000 0x1000>;
3910 mailbox10: mailbox@0 {
3912 reg = <0x0 0x200>;
3924 target-module@62000 { /* 0x48862000, ap 73 74.0 */
3926 reg = <0x62000 0x4>,
3927 <0x62010 0x4>;
3934 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3938 ranges = <0x0 0x62000 0x1000>;
3940 mailbox11: mailbox@0 {
3942 reg = <0x0 0x200>;
3954 target-module@64000 { /* 0x48864000, ap 67 52.0 */
3956 reg = <0x64000 0x4>,
3957 <0x64010 0x4>;
3964 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3968 ranges = <0x0 0x64000 0x1000>;
3970 mailbox12: mailbox@0 {
3972 reg = <0x0 0x200>;
3984 target-module@80000 { /* 0x48880000, ap 83 0e.1 */
3986 reg = <0x80000 0x4>,
3987 <0x80010 0x4>;
3999 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
4003 ranges = <0x0 0x80000 0x20000>;
4005 omap_dwc3_1: omap_dwc3_1@0 {
4007 reg = <0x0 0x10000>;
4012 ranges = <0 0 0x20000>;
4016 reg = <0x10000 0x17000>;
4033 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
4035 reg = <0xc0000 0x4>,
4036 <0xc0010 0x4>;
4048 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4052 ranges = <0x0 0xc0000 0x20000>;
4054 omap_dwc3_2: omap_dwc3_2@0 {
4056 reg = <0x0 0x10000>;
4061 ranges = <0 0 0x20000>;
4065 reg = <0x10000 0x17000>;
4083 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
4085 reg = <0x100000 0x4>,
4086 <0x100010 0x4>;
4098 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4102 ranges = <0x0 0x100000 0x20000>;
4104 omap_dwc3_3: omap_dwc3_3@0 {
4106 reg = <0x0 0x10000>;
4111 ranges = <0 0 0x20000>;
4116 reg = <0x10000 0x17000>;
4131 target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4133 reg = <0x170010 0x4>;
4141 clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4145 ranges = <0x0 0x170000 0x10000>;
4149 target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4151 reg = <0x190010 0x4>;
4159 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4163 ranges = <0x0 0x190000 0x10000>;
4167 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4169 reg = <0x1b0000 0x4>,
4170 <0x1b0010 0x4>;
4178 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4182 ranges = <0x0 0x1b0000 0x10000>;
4186 target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
4188 reg = <0x1d0010 0x4>;
4196 clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4200 ranges = <0x0 0x1d0000 0x10000>;
4202 vpe: vpe@0 {
4204 reg = <0x0000 0x120>,
4205 <0x0700 0x80>,
4206 <0x5700 0x18>,
4207 <0xd000 0x400>;
4218 &l4_wkup { /* 0x4ae00000 */
4221 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>;
4223 reg = <0x4ae00000 0x800>,
4224 <0x4ae00800 0x800>,
4225 <0x4ae01000 0x1000>;
4229 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
4230 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
4231 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */
4232 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */
4234 segment@0 { /* 0x4ae00000 */
4238 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
4239 <0x00001000 0x00001000 0x001000>, /* ap 1 */
4240 <0x00000800 0x00000800 0x000800>, /* ap 2 */
4241 <0x00006000 0x00006000 0x002000>, /* ap 3 */
4242 <0x00008000 0x00008000 0x001000>, /* ap 4 */
4243 <0x00004000 0x00004000 0x001000>, /* ap 15 */
4244 <0x00005000 0x00005000 0x001000>, /* ap 16 */
4245 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */
4246 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */
4248 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
4250 reg = <0x4000 0x4>,
4251 <0x4010 0x4>;
4258 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4262 ranges = <0x0 0x4000 0x1000>;
4264 counter32k: counter@0 {
4266 reg = <0x0 0x40>;
4270 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
4272 reg = <0x6000 0x4>;
4276 ranges = <0x0 0x6000 0x2000>;
4278 prm: prm@0 {
4280 reg = <0 0x3000>;
4284 ranges = <0 0 0x3000>;
4288 #size-cells = <0>;
4296 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
4298 reg = <0xc000 0x4>;
4302 ranges = <0x0 0xc000 0x1000>;
4304 scm_wkup: scm_conf@0 {
4306 reg = <0 0x1000>;
4311 segment@10000 { /* 0x4ae10000 */
4315 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
4316 <0x00001000 0x00011000 0x001000>, /* ap 6 */
4317 <0x00004000 0x00014000 0x001000>, /* ap 7 */
4318 <0x00005000 0x00015000 0x001000>, /* ap 8 */
4319 <0x00008000 0x00018000 0x001000>, /* ap 9 */
4320 <0x00009000 0x00019000 0x001000>, /* ap 10 */
4321 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
4322 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
4324 target-module@0 { /* 0x4ae10000, ap 5 20.0 */
4326 reg = <0x0 0x4>,
4327 <0x10 0x4>,
4328 <0x114 0x4>;
4339 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4344 ranges = <0x0 0x0 0x1000>;
4346 gpio1: gpio@0 {
4348 reg = <0x0 0x200>;
4357 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
4359 reg = <0x4000 0x4>,
4360 <0x4010 0x4>,
4361 <0x4014 0x4>;
4371 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4375 ranges = <0x0 0x4000 0x1000>;
4377 wdt2: wdt@0 {
4379 reg = <0x0 0x80>;
4384 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
4386 reg = <0x8000 0x4>,
4387 <0x8010 0x4>;
4396 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4400 ranges = <0x0 0x8000 0x1000>;
4402 timer1: timer@0 {
4404 reg = <0x0 0x80>;
4412 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
4417 ranges = <0x0 0xc000 0x1000>;
4421 segment@20000 { /* 0x4ae20000 */
4425 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
4426 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
4427 <0x00000000 0x00020000 0x001000>, /* ap 19 */
4428 <0x00001000 0x00021000 0x001000>, /* ap 20 */
4429 <0x00002000 0x00022000 0x001000>, /* ap 21 */
4430 <0x00003000 0x00023000 0x001000>, /* ap 22 */
4431 <0x00007000 0x00027000 0x000400>, /* ap 23 */
4432 <0x00008000 0x00028000 0x000800>, /* ap 24 */
4433 <0x00009000 0x00029000 0x000100>, /* ap 25 */
4434 <0x00008800 0x00028800 0x000200>, /* ap 26 */
4435 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */
4436 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */
4437 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */
4438 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */
4440 target-module@0 { /* 0x4ae20000, ap 19 08.0 */
4442 reg = <0x0 0x4>,
4443 <0x10 0x4>;
4452 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4456 ranges = <0x0 0x0 0x1000>;
4458 timer12: timer@0 {
4460 reg = <0x0 0x80>;
4467 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
4472 ranges = <0x0 0x2000 0x1000>;
4475 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
4480 ranges = <0x00000000 0x00006000 0x00001000>,
4481 <0x00001000 0x00007000 0x00000400>,
4482 <0x00002000 0x00008000 0x00000800>,
4483 <0x00002800 0x00008800 0x00000200>,
4484 <0x00002a00 0x00008a00 0x00000100>,
4485 <0x00003000 0x00009000 0x00000100>;
4488 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
4490 reg = <0xb050 0x4>,
4491 <0xb054 0x4>,
4492 <0xb058 0x4>;
4503 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4507 ranges = <0x0 0xb000 0x1000>;
4509 uart10: serial@0 {
4511 reg = <0x0 0x100>;
4518 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
4523 ranges = <0x0 0xf000 0x1000>;
4527 segment@30000 { /* 0x4ae30000 */
4531 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
4532 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */
4533 <0x00000000 0x00030000 0x001000>, /* ap 33 */
4534 <0x00001000 0x00031000 0x001000>, /* ap 34 */
4535 <0x00002000 0x00032000 0x001000>, /* ap 35 */
4536 <0x00003000 0x00033000 0x001000>, /* ap 36 */
4537 <0x00004000 0x00034000 0x001000>, /* ap 37 */
4538 <0x00005000 0x00035000 0x001000>, /* ap 38 */
4539 <0x00006000 0x00036000 0x001000>, /* ap 39 */
4540 <0x00007000 0x00037000 0x001000>, /* ap 40 */
4541 <0x00008000 0x00038000 0x001000>, /* ap 41 */
4542 <0x00009000 0x00039000 0x001000>, /* ap 42 */
4543 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */
4545 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
4550 ranges = <0x0 0x1000 0x1000>;
4553 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
4558 ranges = <0x0 0x3000 0x1000>;
4561 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
4566 ranges = <0x0 0x5000 0x1000>;
4569 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
4574 ranges = <0x0 0x7000 0x1000>;
4577 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
4582 ranges = <0x0 0x9000 0x1000>;
4585 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
4587 reg = <0xc020 0x4>;
4589 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4593 ranges = <0x0 0xc000 0x2000>;
4595 dcan1: can@0 {
4597 reg = <0x0 0x2000>;
4598 syscon-raminit = <&scm_conf 0x558 0>;