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Searched refs:socclk (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c238 dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; in dml21_apply_soc_bb_overrides()
240 if (i < dml_clk_table->socclk.num_clk_values) { in dml21_apply_soc_bb_overrides()
244 dml_clk_table->socclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.socclk_mhz * 1000; in dml21_apply_soc_bb_overrides()
245 dml_clk_table->socclk.num_clk_values = i + 1; in dml21_apply_soc_bb_overrides()
247 dml_clk_table->socclk.clk_values_khz[i] = 0; in dml21_apply_soc_bb_overrides()
248 dml_clk_table->socclk.num_clk_values = i; in dml21_apply_soc_bb_overrides()
251 dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; in dml21_apply_soc_bb_overrides()
254 dml_clk_table->socclk.clk_values_khz[i] = 0; in dml21_apply_soc_bb_overrides()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c300 clock_limit = smu->smu_table.boot_values.socclk; in renoir_get_dpm_ultimate_freq()
919 uint32_t sclk = 0, socclk = 0, fclk = 0; in renior_set_dpm_profile_freq() local
931 socclk = RENOIR_UMD_PSTATE_SOCCLK; in renior_set_dpm_profile_freq()
933 renoir_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk); in renior_set_dpm_profile_freq()
951 if (socclk) in renior_set_dpm_profile_freq()
952 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk, socclk, false); in renior_set_dpm_profile_freq()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_soc_parameter_types.h123 struct dml2_clk_table socclk; member
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Ddcn_calcs.h127 float socclk; member
564 float socclk; /*MHz*/ member
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/
H A Ddcn4_soc_bb.h114 .socclk = {
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c592 smu->smu_table.boot_values.socclk = 0; in smu_v14_0_get_vbios_bootup_values()
606 smu->smu_table.boot_values.socclk = 0; in smu_v14_0_get_vbios_bootup_values()
621 smu->smu_table.boot_values.socclk = 0; in smu_v14_0_get_vbios_bootup_values()
643 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; in smu_v14_0_get_vbios_bootup_values()
652 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; in smu_v14_0_get_vbios_bootup_values()
1053 clock_limit = smu->smu_table.boot_values.socclk; in smu_v14_0_get_dpm_ultimate_freq()
H A Dsmu_v14_0_0_ppt.c796 clock_limit = smu->smu_table.boot_values.socclk; in smu_v14_0_1_get_dpm_ultimate_freq()
918 clock_limit = smu->smu_table.boot_values.socclk; in smu_v14_0_0_get_dpm_ultimate_freq()
H A Dsmu_v14_0_2_ppt.c518 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v14_0_2_set_default_dpm_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c609 smu->smu_table.boot_values.socclk = 0; in smu_v13_0_get_vbios_bootup_values()
623 smu->smu_table.boot_values.socclk = 0; in smu_v13_0_get_vbios_bootup_values()
638 smu->smu_table.boot_values.socclk = 0; in smu_v13_0_get_vbios_bootup_values()
660 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; in smu_v13_0_get_vbios_bootup_values()
669 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; in smu_v13_0_get_vbios_bootup_values()
893 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_init_max_sustainable_clocks()
1919 *value = smu->smu_table.boot_values.socclk; in smu_v13_0_get_boot_freq_by_index()
H A Dsmu_v13_0_7_ppt.c596 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_7_set_default_dpm_table()
H A Dsmu_v13_0_0_ppt.c589 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_0_set_default_dpm_table()
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c113 .socclk = 208, /*MHz*/
498 input->clks_cfg.socclk_mhz = v->socclk; in dcn_bw_calc_rq_dlg_ttu()
797 v->socclk = dc->dcn_soc->socclk; in dcn_validate_bandwidth()
1364 *socclk_khz = dc->dcn_soc->socclk * 1000; in dcn_get_soc_clks()
1483 dc->dcn_soc->socclk * 1000, in dcn_bw_sync_calcs_and_dml()
H A Ddcn_calc_auto.c1337 …clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c554 smu->smu_table.boot_values.socclk = 0; in smu_v11_0_get_vbios_bootup_values()
571 smu->smu_table.boot_values.socclk = 0; in smu_v11_0_get_vbios_bootup_values()
588 &smu->smu_table.boot_values.socclk); in smu_v11_0_get_vbios_bootup_values()
835 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; in smu_v11_0_init_max_sustainable_clocks()
1724 clock_limit = smu->smu_table.boot_values.socclk; in smu_v11_0_get_dpm_ultimate_freq()
H A Darcturus_ppt.c380 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in arcturus_set_default_dpm_table()
H A Dvangogh_ppt.c918 clock_limit = smu->smu_table.boot_values.socclk; in vangogh_get_dpm_ultimate_freq()
H A Dsienna_cichlid_ppt.c975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in sienna_cichlid_set_default_dpm_table()
H A Dnavi10_ppt.c985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in navi10_set_default_dpm_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h289 uint32_t socclk; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c480 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; in dcn32_set_phantom_stream_timing() local
508 pipes[0].clks_cfg.socclk_mhz = socclk; in dcn32_set_phantom_stream_timing()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_hwmgr.c526 uint16_t virtual_voltage_id, int32_t *socclk) in vega10_get_socclk_for_voltage_evv() argument
548 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk; in vega10_get_socclk_for_voltage_evv()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared.c772 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml2_core_shared_mode_support()
H A Ddml2_core_dcn4_calcs.c7341 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml_core_mode_support()