1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include <linux/acpi_amd_wbrf.h> 26 #include <linux/units.h> 27 28 #include "amdgpu.h" 29 #include "kgd_pp_interface.h" 30 #include "dm_pp_interface.h" 31 #include "dm_pp_smu.h" 32 #include "smu_types.h" 33 #include "linux/firmware.h" 34 35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 38 #define SMU_FW_NAME_LEN 0x24 39 40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 43 44 // Power Throttlers 45 #define SMU_THROTTLER_PPT0_BIT 0 46 #define SMU_THROTTLER_PPT1_BIT 1 47 #define SMU_THROTTLER_PPT2_BIT 2 48 #define SMU_THROTTLER_PPT3_BIT 3 49 #define SMU_THROTTLER_SPL_BIT 4 50 #define SMU_THROTTLER_FPPT_BIT 5 51 #define SMU_THROTTLER_SPPT_BIT 6 52 #define SMU_THROTTLER_SPPT_APU_BIT 7 53 54 // Current Throttlers 55 #define SMU_THROTTLER_TDC_GFX_BIT 16 56 #define SMU_THROTTLER_TDC_SOC_BIT 17 57 #define SMU_THROTTLER_TDC_MEM_BIT 18 58 #define SMU_THROTTLER_TDC_VDD_BIT 19 59 #define SMU_THROTTLER_TDC_CVIP_BIT 20 60 #define SMU_THROTTLER_EDC_CPU_BIT 21 61 #define SMU_THROTTLER_EDC_GFX_BIT 22 62 #define SMU_THROTTLER_APCC_BIT 23 63 64 // Temperature 65 #define SMU_THROTTLER_TEMP_GPU_BIT 32 66 #define SMU_THROTTLER_TEMP_CORE_BIT 33 67 #define SMU_THROTTLER_TEMP_MEM_BIT 34 68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 70 #define SMU_THROTTLER_TEMP_SOC_BIT 37 71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 77 #define SMU_THROTTLER_VRHOT0_BIT 44 78 #define SMU_THROTTLER_VRHOT1_BIT 45 79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 81 82 // Other 83 #define SMU_THROTTLER_PPM_BIT 56 84 #define SMU_THROTTLER_FIT_BIT 57 85 86 struct smu_hw_power_state { 87 unsigned int magic; 88 }; 89 90 struct smu_power_state; 91 92 enum smu_state_ui_label { 93 SMU_STATE_UI_LABEL_NONE, 94 SMU_STATE_UI_LABEL_BATTERY, 95 SMU_STATE_UI_TABEL_MIDDLE_LOW, 96 SMU_STATE_UI_LABEL_BALLANCED, 97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 98 SMU_STATE_UI_LABEL_PERFORMANCE, 99 SMU_STATE_UI_LABEL_BACO, 100 }; 101 102 enum smu_state_classification_flag { 103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 124 }; 125 126 struct smu_state_classification_block { 127 enum smu_state_ui_label ui_label; 128 enum smu_state_classification_flag flags; 129 int bios_index; 130 bool temporary_state; 131 bool to_be_deleted; 132 }; 133 134 struct smu_state_pcie_block { 135 unsigned int lanes; 136 }; 137 138 enum smu_refreshrate_source { 139 SMU_REFRESHRATE_SOURCE_EDID, 140 SMU_REFRESHRATE_SOURCE_EXPLICIT 141 }; 142 143 struct smu_state_display_block { 144 bool disable_frame_modulation; 145 bool limit_refreshrate; 146 enum smu_refreshrate_source refreshrate_source; 147 int explicit_refreshrate; 148 int edid_refreshrate_index; 149 bool enable_vari_bright; 150 }; 151 152 struct smu_state_memory_block { 153 bool dll_off; 154 uint8_t m3arb; 155 uint8_t unused[3]; 156 }; 157 158 struct smu_state_software_algorithm_block { 159 bool disable_load_balancing; 160 bool enable_sleep_for_timestamps; 161 }; 162 163 struct smu_temperature_range { 164 int min; 165 int max; 166 int edge_emergency_max; 167 int hotspot_min; 168 int hotspot_crit_max; 169 int hotspot_emergency_max; 170 int mem_min; 171 int mem_crit_max; 172 int mem_emergency_max; 173 int software_shutdown_temp; 174 int software_shutdown_temp_offset; 175 }; 176 177 struct smu_state_validation_block { 178 bool single_display_only; 179 bool disallow_on_dc; 180 uint8_t supported_power_levels; 181 }; 182 183 struct smu_uvd_clocks { 184 uint32_t vclk; 185 uint32_t dclk; 186 }; 187 188 /** 189 * Structure to hold a SMU Power State. 190 */ 191 struct smu_power_state { 192 uint32_t id; 193 struct list_head ordered_list; 194 struct list_head all_states_list; 195 196 struct smu_state_classification_block classification; 197 struct smu_state_validation_block validation; 198 struct smu_state_pcie_block pcie; 199 struct smu_state_display_block display; 200 struct smu_state_memory_block memory; 201 struct smu_state_software_algorithm_block software; 202 struct smu_uvd_clocks uvd_clocks; 203 struct smu_hw_power_state hardware; 204 }; 205 206 enum smu_power_src_type { 207 SMU_POWER_SOURCE_AC, 208 SMU_POWER_SOURCE_DC, 209 SMU_POWER_SOURCE_COUNT, 210 }; 211 212 enum smu_ppt_limit_type { 213 SMU_DEFAULT_PPT_LIMIT = 0, 214 SMU_FAST_PPT_LIMIT, 215 }; 216 217 enum smu_ppt_limit_level { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size { 225 SMU_MEMORY_POOL_SIZE_ZERO = 0, 226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 230 }; 231 232 struct smu_user_dpm_profile { 233 uint32_t fan_mode; 234 uint32_t power_limit; 235 uint32_t fan_speed_pwm; 236 uint32_t fan_speed_rpm; 237 uint32_t flags; 238 uint32_t user_od; 239 240 /* user clock state information */ 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 uint32_t clk_dependency; 243 uint32_t user_workload_mask; 244 }; 245 246 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 247 do { \ 248 tables[table_id].size = s; \ 249 tables[table_id].align = a; \ 250 tables[table_id].domain = d; \ 251 } while (0) 252 253 struct smu_table { 254 uint64_t size; 255 uint32_t align; 256 uint8_t domain; 257 uint64_t mc_address; 258 void *cpu_addr; 259 struct amdgpu_bo *bo; 260 uint32_t version; 261 }; 262 263 enum smu_perf_level_designation { 264 PERF_LEVEL_ACTIVITY, 265 PERF_LEVEL_POWER_CONTAINMENT, 266 }; 267 268 struct smu_performance_level { 269 uint32_t core_clock; 270 uint32_t memory_clock; 271 uint32_t vddc; 272 uint32_t vddci; 273 uint32_t non_local_mem_freq; 274 uint32_t non_local_mem_width; 275 }; 276 277 struct smu_clock_info { 278 uint32_t min_mem_clk; 279 uint32_t max_mem_clk; 280 uint32_t min_eng_clk; 281 uint32_t max_eng_clk; 282 uint32_t min_bus_bandwidth; 283 uint32_t max_bus_bandwidth; 284 }; 285 286 struct smu_bios_boot_up_values { 287 uint32_t revision; 288 uint32_t gfxclk; 289 uint32_t uclk; 290 uint32_t socclk; 291 uint32_t dcefclk; 292 uint32_t eclk; 293 uint32_t vclk; 294 uint32_t dclk; 295 uint16_t vddc; 296 uint16_t vddci; 297 uint16_t mvddc; 298 uint16_t vdd_gfx; 299 uint8_t cooling_id; 300 uint32_t pp_table_id; 301 uint32_t format_revision; 302 uint32_t content_revision; 303 uint32_t fclk; 304 uint32_t lclk; 305 uint32_t firmware_caps; 306 }; 307 308 enum smu_table_id { 309 SMU_TABLE_PPTABLE = 0, 310 SMU_TABLE_WATERMARKS, 311 SMU_TABLE_CUSTOM_DPM, 312 SMU_TABLE_DPMCLOCKS, 313 SMU_TABLE_AVFS, 314 SMU_TABLE_AVFS_PSM_DEBUG, 315 SMU_TABLE_AVFS_FUSE_OVERRIDE, 316 SMU_TABLE_PMSTATUSLOG, 317 SMU_TABLE_SMU_METRICS, 318 SMU_TABLE_DRIVER_SMU_CONFIG, 319 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 320 SMU_TABLE_OVERDRIVE, 321 SMU_TABLE_I2C_COMMANDS, 322 SMU_TABLE_PACE, 323 SMU_TABLE_ECCINFO, 324 SMU_TABLE_COMBO_PPTABLE, 325 SMU_TABLE_WIFIBAND, 326 SMU_TABLE_COUNT, 327 }; 328 329 struct smu_table_context { 330 void *power_play_table; 331 uint32_t power_play_table_size; 332 void *hardcode_pptable; 333 unsigned long metrics_time; 334 void *metrics_table; 335 void *clocks_table; 336 void *watermarks_table; 337 338 void *max_sustainable_clocks; 339 struct smu_bios_boot_up_values boot_values; 340 void *driver_pptable; 341 void *combo_pptable; 342 void *ecc_table; 343 void *driver_smu_config_table; 344 struct smu_table tables[SMU_TABLE_COUNT]; 345 /* 346 * The driver table is just a staging buffer for 347 * uploading/downloading content from the SMU. 348 * 349 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 350 * SMU_MSG_TransferTableDram2Smu instructs SMU 351 * which content driver is interested. 352 */ 353 struct smu_table driver_table; 354 struct smu_table memory_pool; 355 struct smu_table dummy_read_1_table; 356 uint8_t thermal_controller_type; 357 358 void *overdrive_table; 359 void *boot_overdrive_table; 360 void *user_overdrive_table; 361 362 uint32_t gpu_metrics_table_size; 363 void *gpu_metrics_table; 364 }; 365 366 struct smu_context; 367 struct smu_dpm_policy; 368 369 struct smu_dpm_policy_desc { 370 const char *name; 371 char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level); 372 }; 373 374 struct smu_dpm_policy { 375 struct smu_dpm_policy_desc *desc; 376 enum pp_pm_policy policy_type; 377 unsigned long level_mask; 378 int current_level; 379 int (*set_policy)(struct smu_context *ctxt, int level); 380 }; 381 382 struct smu_dpm_policy_ctxt { 383 struct smu_dpm_policy policies[PP_PM_POLICY_NUM]; 384 unsigned long policy_mask; 385 }; 386 387 struct smu_dpm_context { 388 uint32_t dpm_context_size; 389 void *dpm_context; 390 void *golden_dpm_context; 391 enum amd_dpm_forced_level dpm_level; 392 enum amd_dpm_forced_level saved_dpm_level; 393 enum amd_dpm_forced_level requested_dpm_level; 394 struct smu_power_state *dpm_request_power_state; 395 struct smu_power_state *dpm_current_power_state; 396 struct mclock_latency_table *mclk_latency_table; 397 struct smu_dpm_policy_ctxt *dpm_policies; 398 }; 399 400 struct smu_power_gate { 401 bool uvd_gated; 402 bool vce_gated; 403 atomic_t vcn_gated; 404 atomic_t jpeg_gated; 405 atomic_t vpe_gated; 406 atomic_t umsch_mm_gated; 407 }; 408 409 struct smu_power_context { 410 void *power_context; 411 uint32_t power_context_size; 412 struct smu_power_gate power_gate; 413 }; 414 415 #define SMU_FEATURE_MAX (64) 416 struct smu_feature { 417 uint32_t feature_num; 418 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 419 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 420 }; 421 422 struct smu_clocks { 423 uint32_t engine_clock; 424 uint32_t memory_clock; 425 uint32_t bus_bandwidth; 426 uint32_t engine_clock_in_sr; 427 uint32_t dcef_clock; 428 uint32_t dcef_clock_in_sr; 429 }; 430 431 #define MAX_REGULAR_DPM_NUM 16 432 struct mclk_latency_entries { 433 uint32_t frequency; 434 uint32_t latency; 435 }; 436 struct mclock_latency_table { 437 uint32_t count; 438 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 439 }; 440 441 enum smu_reset_mode { 442 SMU_RESET_MODE_0, 443 SMU_RESET_MODE_1, 444 SMU_RESET_MODE_2, 445 }; 446 447 enum smu_baco_state { 448 SMU_BACO_STATE_ENTER = 0, 449 SMU_BACO_STATE_EXIT, 450 SMU_BACO_STATE_NONE, 451 }; 452 453 struct smu_baco_context { 454 uint32_t state; 455 bool platform_support; 456 bool maco_support; 457 }; 458 459 struct smu_freq_info { 460 uint32_t min; 461 uint32_t max; 462 uint32_t freq_level; 463 }; 464 465 struct pstates_clk_freq { 466 uint32_t min; 467 uint32_t standard; 468 uint32_t peak; 469 struct smu_freq_info custom; 470 struct smu_freq_info curr; 471 }; 472 473 struct smu_umd_pstate_table { 474 struct pstates_clk_freq gfxclk_pstate; 475 struct pstates_clk_freq socclk_pstate; 476 struct pstates_clk_freq uclk_pstate; 477 struct pstates_clk_freq vclk_pstate; 478 struct pstates_clk_freq dclk_pstate; 479 struct pstates_clk_freq fclk_pstate; 480 }; 481 482 struct cmn2asic_msg_mapping { 483 int valid_mapping; 484 int map_to; 485 uint32_t flags; 486 }; 487 488 struct cmn2asic_mapping { 489 int valid_mapping; 490 int map_to; 491 }; 492 493 struct stb_context { 494 uint32_t stb_buf_size; 495 bool enabled; 496 spinlock_t lock; 497 }; 498 499 enum smu_fw_status { 500 SMU_FW_INIT = 0, 501 SMU_FW_RUNTIME, 502 SMU_FW_HANG, 503 }; 504 505 #define WORKLOAD_POLICY_MAX 7 506 507 /* 508 * Configure wbrf event handling pace as there can be only one 509 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. 510 */ 511 #define SMU_WBRF_EVENT_HANDLING_PACE 10 512 513 struct smu_context { 514 struct amdgpu_device *adev; 515 struct amdgpu_irq_src irq_source; 516 517 const struct pptable_funcs *ppt_funcs; 518 const struct cmn2asic_msg_mapping *message_map; 519 const struct cmn2asic_mapping *clock_map; 520 const struct cmn2asic_mapping *feature_map; 521 const struct cmn2asic_mapping *table_map; 522 const struct cmn2asic_mapping *pwr_src_map; 523 const struct cmn2asic_mapping *workload_map; 524 struct mutex message_lock; 525 uint64_t pool_size; 526 527 struct smu_table_context smu_table; 528 struct smu_dpm_context smu_dpm; 529 struct smu_power_context smu_power; 530 struct smu_feature smu_feature; 531 struct amd_pp_display_configuration *display_config; 532 struct smu_baco_context smu_baco; 533 struct smu_temperature_range thermal_range; 534 void *od_settings; 535 536 struct smu_umd_pstate_table pstate_table; 537 uint32_t pstate_sclk; 538 uint32_t pstate_mclk; 539 540 bool od_enabled; 541 uint32_t current_power_limit; 542 uint32_t default_power_limit; 543 uint32_t max_power_limit; 544 uint32_t min_power_limit; 545 546 /* soft pptable */ 547 uint32_t ppt_offset_bytes; 548 uint32_t ppt_size_bytes; 549 uint8_t *ppt_start_addr; 550 551 bool support_power_containment; 552 bool disable_watermark; 553 554 #define WATERMARKS_EXIST (1 << 0) 555 #define WATERMARKS_LOADED (1 << 1) 556 uint32_t watermarks_bitmap; 557 uint32_t hard_min_uclk_req_from_dal; 558 bool disable_uclk_switch; 559 560 uint32_t workload_mask; 561 uint32_t driver_workload_mask; 562 uint32_t workload_priority[WORKLOAD_POLICY_MAX]; 563 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 564 uint32_t power_profile_mode; 565 uint32_t default_power_profile_mode; 566 bool pm_enabled; 567 bool is_apu; 568 569 uint32_t smc_driver_if_version; 570 uint32_t smc_fw_if_version; 571 uint32_t smc_fw_version; 572 uint32_t smc_fw_caps; 573 uint8_t smc_fw_state; 574 575 bool uploading_custom_pp_table; 576 bool dc_controlled_by_gpio; 577 578 struct work_struct throttling_logging_work; 579 atomic64_t throttle_int_counter; 580 struct work_struct interrupt_work; 581 582 unsigned fan_max_rpm; 583 unsigned manual_fan_speed_pwm; 584 585 uint32_t gfx_default_hard_min_freq; 586 uint32_t gfx_default_soft_max_freq; 587 uint32_t gfx_actual_hard_min_freq; 588 uint32_t gfx_actual_soft_max_freq; 589 590 /* APU only */ 591 uint32_t cpu_default_soft_min_freq; 592 uint32_t cpu_default_soft_max_freq; 593 uint32_t cpu_actual_soft_min_freq; 594 uint32_t cpu_actual_soft_max_freq; 595 uint32_t cpu_core_id_select; 596 uint16_t cpu_core_num; 597 598 struct smu_user_dpm_profile user_dpm_profile; 599 600 struct stb_context stb_context; 601 602 struct firmware pptable_firmware; 603 604 u32 param_reg; 605 u32 msg_reg; 606 u32 resp_reg; 607 608 u32 debug_param_reg; 609 u32 debug_msg_reg; 610 u32 debug_resp_reg; 611 612 struct delayed_work swctf_delayed_work; 613 614 /* data structures for wbrf feature support */ 615 bool wbrf_supported; 616 struct notifier_block wbrf_notifier; 617 struct delayed_work wbrf_delayed_work; 618 }; 619 620 struct i2c_adapter; 621 622 /** 623 * struct pptable_funcs - Callbacks used to interact with the SMU. 624 */ 625 struct pptable_funcs { 626 /** 627 * @run_btc: Calibrate voltage/frequency curve to fit the system's 628 * power delivery and voltage margins. Required for adaptive 629 * voltage frequency scaling (AVFS). 630 */ 631 int (*run_btc)(struct smu_context *smu); 632 633 /** 634 * @get_allowed_feature_mask: Get allowed feature mask. 635 * &feature_mask: Array to store feature mask. 636 * &num: Elements in &feature_mask. 637 */ 638 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 639 640 /** 641 * @get_current_power_state: Get the current power state. 642 * 643 * Return: Current power state on success, negative errno on failure. 644 */ 645 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 646 647 /** 648 * @set_default_dpm_table: Retrieve the default overdrive settings from 649 * the SMU. 650 */ 651 int (*set_default_dpm_table)(struct smu_context *smu); 652 653 int (*set_power_state)(struct smu_context *smu); 654 655 /** 656 * @populate_umd_state_clk: Populate the UMD power state table with 657 * defaults. 658 */ 659 int (*populate_umd_state_clk)(struct smu_context *smu); 660 661 /** 662 * @print_clk_levels: Print DPM clock levels for a clock domain 663 * to buffer. Star current level. 664 * 665 * Used for sysfs interfaces. 666 * Return: Number of characters written to the buffer 667 */ 668 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 669 670 /** 671 * @emit_clk_levels: Print DPM clock levels for a clock domain 672 * to buffer using sysfs_emit_at. Star current level. 673 * 674 * Used for sysfs interfaces. 675 * &buf: sysfs buffer 676 * &offset: offset within buffer to start printing, which is updated by the 677 * function. 678 * 679 * Return: 0 on Success or Negative to indicate an error occurred. 680 */ 681 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 682 683 /** 684 * @force_clk_levels: Set a range of allowed DPM levels for a clock 685 * domain. 686 * &clk_type: Clock domain. 687 * &mask: Range of allowed DPM levels. 688 */ 689 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 690 691 /** 692 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 693 * &type: Type of edit. 694 * &input: Edit parameters. 695 * &size: Size of &input. 696 */ 697 int (*od_edit_dpm_table)(struct smu_context *smu, 698 enum PP_OD_DPM_TABLE_COMMAND type, 699 long *input, uint32_t size); 700 701 /** 702 * @restore_user_od_settings: Restore the user customized 703 * OD settings on S3/S4/Runpm resume. 704 */ 705 int (*restore_user_od_settings)(struct smu_context *smu); 706 707 /** 708 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 709 * domain. 710 */ 711 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 712 enum smu_clk_type clk_type, 713 struct 714 pp_clock_levels_with_latency 715 *clocks); 716 /** 717 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 718 * domain. 719 */ 720 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 721 enum amd_pp_clock_type type, 722 struct 723 pp_clock_levels_with_voltage 724 *clocks); 725 726 /** 727 * @get_power_profile_mode: Print all power profile modes to 728 * buffer. Star current mode. 729 */ 730 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 731 732 /** 733 * @set_power_profile_mode: Set a power profile mode. Also used to 734 * create/set custom power profile modes. 735 * &input: Power profile mode parameters. 736 * &size: Size of &input. 737 */ 738 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 739 740 /** 741 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 742 * management. 743 */ 744 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 745 746 /** 747 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 748 * management. 749 */ 750 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 751 752 /** 753 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 754 */ 755 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 756 757 /** 758 * @read_sensor: Read data from a sensor. 759 * &sensor: Sensor to read data from. 760 * &data: Sensor reading. 761 * &size: Size of &data. 762 */ 763 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 764 void *data, uint32_t *size); 765 766 /** 767 * @get_apu_thermal_limit: get apu core limit from smu 768 * &limit: current limit temperature in millidegrees Celsius 769 */ 770 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 771 772 /** 773 * @set_apu_thermal_limit: update all controllers with new limit 774 * &limit: limit temperature to be setted, in millidegrees Celsius 775 */ 776 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 777 778 /** 779 * @pre_display_config_changed: Prepare GPU for a display configuration 780 * change. 781 * 782 * Disable display tracking and pin memory clock speed to maximum. Used 783 * in display component synchronization. 784 */ 785 int (*pre_display_config_changed)(struct smu_context *smu); 786 787 /** 788 * @display_config_changed: Notify the SMU of the current display 789 * configuration. 790 * 791 * Allows SMU to properly track blanking periods for memory clock 792 * adjustment. Used in display component synchronization. 793 */ 794 int (*display_config_changed)(struct smu_context *smu); 795 796 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 797 798 /** 799 * @notify_smc_display_config: Applies display requirements to the 800 * current power state. 801 * 802 * Optimize deep sleep DCEFclk and mclk for the current display 803 * configuration. Used in display component synchronization. 804 */ 805 int (*notify_smc_display_config)(struct smu_context *smu); 806 807 /** 808 * @is_dpm_running: Check if DPM is running. 809 * 810 * Return: True if DPM is running, false otherwise. 811 */ 812 bool (*is_dpm_running)(struct smu_context *smu); 813 814 /** 815 * @get_fan_speed_pwm: Get the current fan speed in PWM. 816 */ 817 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 818 819 /** 820 * @get_fan_speed_rpm: Get the current fan speed in rpm. 821 */ 822 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 823 824 /** 825 * @set_watermarks_table: Configure and upload the watermarks tables to 826 * the SMU. 827 */ 828 int (*set_watermarks_table)(struct smu_context *smu, 829 struct pp_smu_wm_range_sets *clock_ranges); 830 831 /** 832 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 833 */ 834 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 835 836 /** 837 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 838 * &clocks_in_khz: Array of DPM levels. 839 * &num_states: Elements in &clocks_in_khz. 840 */ 841 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 842 843 /** 844 * @set_default_od_settings: Set the overdrive tables to defaults. 845 */ 846 int (*set_default_od_settings)(struct smu_context *smu); 847 848 /** 849 * @set_performance_level: Set a performance level. 850 */ 851 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 852 853 /** 854 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 855 * clock switching. 856 * 857 * Disabling this feature forces memory clock speed to maximum. 858 * Enabling sets the minimum memory clock capable of driving the 859 * current display configuration. 860 */ 861 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 862 863 /** 864 * @dump_pptable: Print the power play table to the system log. 865 */ 866 void (*dump_pptable)(struct smu_context *smu); 867 868 /** 869 * @get_power_limit: Get the device's power limits. 870 */ 871 int (*get_power_limit)(struct smu_context *smu, 872 uint32_t *current_power_limit, 873 uint32_t *default_power_limit, 874 uint32_t *max_power_limit, 875 uint32_t *min_power_limit); 876 877 /** 878 * @get_ppt_limit: Get the device's ppt limits. 879 */ 880 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 881 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 882 883 /** 884 * @set_df_cstate: Set data fabric cstate. 885 */ 886 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 887 888 /** 889 * @update_pcie_parameters: Update and upload the system's PCIe 890 * capabilites to the SMU. 891 * &pcie_gen_cap: Maximum allowed PCIe generation. 892 * &pcie_width_cap: Maximum allowed PCIe width. 893 */ 894 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 895 896 /** 897 * @i2c_init: Initialize i2c. 898 * 899 * The i2c bus is used internally by the SMU voltage regulators and 900 * other devices. The i2c's EEPROM also stores bad page tables on boards 901 * with ECC. 902 */ 903 int (*i2c_init)(struct smu_context *smu); 904 905 /** 906 * @i2c_fini: Tear down i2c. 907 */ 908 void (*i2c_fini)(struct smu_context *smu); 909 910 /** 911 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 912 */ 913 void (*get_unique_id)(struct smu_context *smu); 914 915 /** 916 * @get_dpm_clock_table: Get a copy of the DPM clock table. 917 * 918 * Used by display component in bandwidth and watermark calculations. 919 */ 920 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 921 922 /** 923 * @init_microcode: Request the SMU's firmware from the kernel. 924 */ 925 int (*init_microcode)(struct smu_context *smu); 926 927 /** 928 * @load_microcode: Load firmware onto the SMU. 929 */ 930 int (*load_microcode)(struct smu_context *smu); 931 932 /** 933 * @fini_microcode: Release the SMU's firmware. 934 */ 935 void (*fini_microcode)(struct smu_context *smu); 936 937 /** 938 * @init_smc_tables: Initialize the SMU tables. 939 */ 940 int (*init_smc_tables)(struct smu_context *smu); 941 942 /** 943 * @fini_smc_tables: Release the SMU tables. 944 */ 945 int (*fini_smc_tables)(struct smu_context *smu); 946 947 /** 948 * @init_power: Initialize the power gate table context. 949 */ 950 int (*init_power)(struct smu_context *smu); 951 952 /** 953 * @fini_power: Release the power gate table context. 954 */ 955 int (*fini_power)(struct smu_context *smu); 956 957 /** 958 * @check_fw_status: Check the SMU's firmware status. 959 * 960 * Return: Zero if check passes, negative errno on failure. 961 */ 962 int (*check_fw_status)(struct smu_context *smu); 963 964 /** 965 * @set_mp1_state: put SMU into a correct state for comming 966 * resume from runpm or gpu reset. 967 */ 968 int (*set_mp1_state)(struct smu_context *smu, 969 enum pp_mp1_state mp1_state); 970 971 /** 972 * @setup_pptable: Initialize the power play table and populate it with 973 * default values. 974 */ 975 int (*setup_pptable)(struct smu_context *smu); 976 977 /** 978 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 979 */ 980 int (*get_vbios_bootup_values)(struct smu_context *smu); 981 982 /** 983 * @check_fw_version: Print driver and SMU interface versions to the 984 * system log. 985 * 986 * Interface mismatch is not a critical failure. 987 */ 988 int (*check_fw_version)(struct smu_context *smu); 989 990 /** 991 * @powergate_sdma: Power up/down system direct memory access. 992 */ 993 int (*powergate_sdma)(struct smu_context *smu, bool gate); 994 995 /** 996 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 997 * gating. 998 */ 999 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 1000 1001 /** 1002 * @write_pptable: Write the power play table to the SMU. 1003 */ 1004 int (*write_pptable)(struct smu_context *smu); 1005 1006 /** 1007 * @set_driver_table_location: Send the location of the driver table to 1008 * the SMU. 1009 */ 1010 int (*set_driver_table_location)(struct smu_context *smu); 1011 1012 /** 1013 * @set_tool_table_location: Send the location of the tool table to the 1014 * SMU. 1015 */ 1016 int (*set_tool_table_location)(struct smu_context *smu); 1017 1018 /** 1019 * @notify_memory_pool_location: Send the location of the memory pool to 1020 * the SMU. 1021 */ 1022 int (*notify_memory_pool_location)(struct smu_context *smu); 1023 1024 /** 1025 * @system_features_control: Enable/disable all SMU features. 1026 */ 1027 int (*system_features_control)(struct smu_context *smu, bool en); 1028 1029 /** 1030 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1031 * &msg: Type of message. 1032 * ¶m: Message parameter. 1033 * &read_arg: SMU response (optional). 1034 */ 1035 int (*send_smc_msg_with_param)(struct smu_context *smu, 1036 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1037 1038 /** 1039 * @send_smc_msg: Send a message to the SMU. 1040 * &msg: Type of message. 1041 * &read_arg: SMU response (optional). 1042 */ 1043 int (*send_smc_msg)(struct smu_context *smu, 1044 enum smu_message_type msg, 1045 uint32_t *read_arg); 1046 1047 /** 1048 * @init_display_count: Notify the SMU of the number of display 1049 * components in current display configuration. 1050 */ 1051 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1052 1053 /** 1054 * @set_allowed_mask: Notify the SMU of the features currently allowed 1055 * by the driver. 1056 */ 1057 int (*set_allowed_mask)(struct smu_context *smu); 1058 1059 /** 1060 * @get_enabled_mask: Get a mask of features that are currently enabled 1061 * on the SMU. 1062 * &feature_mask: Enabled feature mask. 1063 */ 1064 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1065 1066 /** 1067 * @feature_is_enabled: Test if a feature is enabled. 1068 * 1069 * Return: One if enabled, zero if disabled. 1070 */ 1071 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1072 1073 /** 1074 * @disable_all_features_with_exception: Disable all features with 1075 * exception to those in &mask. 1076 */ 1077 int (*disable_all_features_with_exception)(struct smu_context *smu, 1078 enum smu_feature_mask mask); 1079 1080 /** 1081 * @notify_display_change: General interface call to let SMU know about DC change 1082 */ 1083 int (*notify_display_change)(struct smu_context *smu); 1084 1085 /** 1086 * @set_power_limit: Set power limit in watts. 1087 */ 1088 int (*set_power_limit)(struct smu_context *smu, 1089 enum smu_ppt_limit_type limit_type, 1090 uint32_t limit); 1091 1092 /** 1093 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1094 * table with values from the SMU. 1095 */ 1096 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1097 1098 /** 1099 * @enable_thermal_alert: Enable thermal alert interrupts. 1100 */ 1101 int (*enable_thermal_alert)(struct smu_context *smu); 1102 1103 /** 1104 * @disable_thermal_alert: Disable thermal alert interrupts. 1105 */ 1106 int (*disable_thermal_alert)(struct smu_context *smu); 1107 1108 /** 1109 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1110 * clock speed in MHz. 1111 */ 1112 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1113 1114 /** 1115 * @display_clock_voltage_request: Set a hard minimum frequency 1116 * for a clock domain. 1117 */ 1118 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1119 pp_display_clock_request 1120 *clock_req); 1121 1122 /** 1123 * @get_fan_control_mode: Get the current fan control mode. 1124 */ 1125 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1126 1127 /** 1128 * @set_fan_control_mode: Set the fan control mode. 1129 */ 1130 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1131 1132 /** 1133 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1134 */ 1135 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1136 1137 /** 1138 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1139 */ 1140 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1141 1142 /** 1143 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1144 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1145 */ 1146 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1147 1148 /** 1149 * @gfx_off_control: Enable/disable graphics engine poweroff. 1150 */ 1151 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1152 1153 1154 /** 1155 * @get_gfx_off_status: Get graphics engine poweroff status. 1156 * 1157 * Return: 1158 * 0 - GFXOFF(default). 1159 * 1 - Transition out of GFX State. 1160 * 2 - Not in GFXOFF. 1161 * 3 - Transition into GFXOFF. 1162 */ 1163 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1164 1165 /** 1166 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1167 * query since system power-up 1168 */ 1169 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1170 1171 /** 1172 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1173 */ 1174 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1175 1176 /** 1177 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1178 */ 1179 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1180 1181 /** 1182 * @register_irq_handler: Register interupt request handlers. 1183 */ 1184 int (*register_irq_handler)(struct smu_context *smu); 1185 1186 /** 1187 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1188 */ 1189 int (*set_azalia_d3_pme)(struct smu_context *smu); 1190 1191 /** 1192 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1193 * clock speeds table. 1194 * 1195 * Provides a way for the display component (DC) to get the max 1196 * sustainable clocks from the SMU. 1197 */ 1198 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1199 1200 /** 1201 * @get_bamaco_support: Check if GPU supports BACO/MACO 1202 * BACO: Bus Active, Chip Off 1203 * MACO: Memory Active, Chip Off 1204 */ 1205 int (*get_bamaco_support)(struct smu_context *smu); 1206 1207 /** 1208 * @baco_get_state: Get the current BACO state. 1209 * 1210 * Return: Current BACO state. 1211 */ 1212 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1213 1214 /** 1215 * @baco_set_state: Enter/exit BACO. 1216 */ 1217 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1218 1219 /** 1220 * @baco_enter: Enter BACO. 1221 */ 1222 int (*baco_enter)(struct smu_context *smu); 1223 1224 /** 1225 * @baco_exit: Exit Baco. 1226 */ 1227 int (*baco_exit)(struct smu_context *smu); 1228 1229 /** 1230 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1231 */ 1232 bool (*mode1_reset_is_support)(struct smu_context *smu); 1233 /** 1234 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1235 */ 1236 bool (*mode2_reset_is_support)(struct smu_context *smu); 1237 1238 /** 1239 * @mode1_reset: Perform mode1 reset. 1240 * 1241 * Complete GPU reset. 1242 */ 1243 int (*mode1_reset)(struct smu_context *smu); 1244 1245 /** 1246 * @mode2_reset: Perform mode2 reset. 1247 * 1248 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1249 * IPs reset varies by asic. 1250 */ 1251 int (*mode2_reset)(struct smu_context *smu); 1252 /* for gfx feature enablement after mode2 reset */ 1253 int (*enable_gfx_features)(struct smu_context *smu); 1254 1255 /** 1256 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1257 * domain in MHz. 1258 */ 1259 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1260 1261 /** 1262 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1263 * domain in MHz. 1264 */ 1265 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1266 1267 /** 1268 * @set_power_source: Notify the SMU of the current power source. 1269 */ 1270 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1271 1272 /** 1273 * @log_thermal_throttling_event: Print a thermal throttling warning to 1274 * the system's log. 1275 */ 1276 void (*log_thermal_throttling_event)(struct smu_context *smu); 1277 1278 /** 1279 * @get_pp_feature_mask: Print a human readable table of enabled 1280 * features to buffer. 1281 */ 1282 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1283 1284 /** 1285 * @set_pp_feature_mask: Request the SMU enable/disable features to 1286 * match those enabled in &new_mask. 1287 */ 1288 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1289 1290 /** 1291 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1292 * 1293 * Return: Size of &table 1294 */ 1295 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1296 1297 /** 1298 * @get_pm_metrics: Get one snapshot of power management metrics from 1299 * PMFW. 1300 * 1301 * Return: Size of the metrics sample 1302 */ 1303 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1304 size_t size); 1305 1306 /** 1307 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1308 */ 1309 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1310 1311 /** 1312 * @gfx_ulv_control: Enable/disable ultra low voltage. 1313 */ 1314 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1315 1316 /** 1317 * @deep_sleep_control: Enable/disable deep sleep. 1318 */ 1319 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1320 1321 /** 1322 * @get_fan_parameters: Get fan parameters. 1323 * 1324 * Get maximum fan speed from the power play table. 1325 */ 1326 int (*get_fan_parameters)(struct smu_context *smu); 1327 1328 /** 1329 * @post_init: Helper function for asic specific workarounds. 1330 */ 1331 int (*post_init)(struct smu_context *smu); 1332 1333 /** 1334 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1335 */ 1336 void (*interrupt_work)(struct smu_context *smu); 1337 1338 /** 1339 * @gpo_control: Enable/disable graphics power optimization if supported. 1340 */ 1341 int (*gpo_control)(struct smu_context *smu, bool enablement); 1342 1343 /** 1344 * @gfx_state_change_set: Send the current graphics state to the SMU. 1345 */ 1346 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1347 1348 /** 1349 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1350 * parameters to defaults. 1351 */ 1352 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1353 1354 /** 1355 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1356 */ 1357 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1358 1359 /** 1360 * @wait_for_event: Wait for events from SMU. 1361 */ 1362 int (*wait_for_event)(struct smu_context *smu, 1363 enum smu_event_type event, uint64_t event_arg); 1364 1365 /** 1366 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1367 * of SMUBUS table. 1368 */ 1369 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1370 1371 /** 1372 * @send_rma_reason: message rma reason event to SMU. 1373 */ 1374 int (*send_rma_reason)(struct smu_context *smu); 1375 1376 /** 1377 * @get_ecc_table: message SMU to get ECC INFO table. 1378 */ 1379 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1380 1381 1382 /** 1383 * @stb_collect_info: Collects Smart Trace Buffers data. 1384 */ 1385 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1386 1387 /** 1388 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1389 */ 1390 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1391 1392 /** 1393 * @set_config_table: Apply the input DriverSmuConfig table settings. 1394 */ 1395 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1396 1397 /** 1398 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1399 * of SMUBUS table. 1400 */ 1401 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1402 1403 /** 1404 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1405 */ 1406 int (*init_pptable_microcode)(struct smu_context *smu); 1407 1408 /** 1409 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1410 * management. 1411 */ 1412 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1413 1414 /** 1415 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1416 * management. 1417 */ 1418 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1419 1420 /** 1421 * @set_mall_enable: Init MALL power gating control. 1422 */ 1423 int (*set_mall_enable)(struct smu_context *smu); 1424 1425 /** 1426 * @notify_rlc_state: Notify RLC power state to SMU. 1427 */ 1428 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1429 1430 /** 1431 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature 1432 */ 1433 bool (*is_asic_wbrf_supported)(struct smu_context *smu); 1434 1435 /** 1436 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported 1437 */ 1438 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable); 1439 1440 /** 1441 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied 1442 */ 1443 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu, 1444 struct freq_band_range *exclusion_ranges); 1445 }; 1446 1447 typedef enum { 1448 METRICS_CURR_GFXCLK, 1449 METRICS_CURR_SOCCLK, 1450 METRICS_CURR_UCLK, 1451 METRICS_CURR_VCLK, 1452 METRICS_CURR_VCLK1, 1453 METRICS_CURR_DCLK, 1454 METRICS_CURR_DCLK1, 1455 METRICS_CURR_FCLK, 1456 METRICS_CURR_DCEFCLK, 1457 METRICS_AVERAGE_CPUCLK, 1458 METRICS_AVERAGE_GFXCLK, 1459 METRICS_AVERAGE_SOCCLK, 1460 METRICS_AVERAGE_FCLK, 1461 METRICS_AVERAGE_UCLK, 1462 METRICS_AVERAGE_VCLK, 1463 METRICS_AVERAGE_DCLK, 1464 METRICS_AVERAGE_VCLK1, 1465 METRICS_AVERAGE_DCLK1, 1466 METRICS_AVERAGE_GFXACTIVITY, 1467 METRICS_AVERAGE_MEMACTIVITY, 1468 METRICS_AVERAGE_VCNACTIVITY, 1469 METRICS_AVERAGE_SOCKETPOWER, 1470 METRICS_TEMPERATURE_EDGE, 1471 METRICS_TEMPERATURE_HOTSPOT, 1472 METRICS_TEMPERATURE_MEM, 1473 METRICS_TEMPERATURE_VRGFX, 1474 METRICS_TEMPERATURE_VRSOC, 1475 METRICS_TEMPERATURE_VRMEM, 1476 METRICS_THROTTLER_STATUS, 1477 METRICS_CURR_FANSPEED, 1478 METRICS_VOLTAGE_VDDSOC, 1479 METRICS_VOLTAGE_VDDGFX, 1480 METRICS_SS_APU_SHARE, 1481 METRICS_SS_DGPU_SHARE, 1482 METRICS_UNIQUE_ID_UPPER32, 1483 METRICS_UNIQUE_ID_LOWER32, 1484 METRICS_PCIE_RATE, 1485 METRICS_PCIE_WIDTH, 1486 METRICS_CURR_FANPWM, 1487 METRICS_CURR_SOCKETPOWER, 1488 METRICS_AVERAGE_VPECLK, 1489 METRICS_AVERAGE_IPUCLK, 1490 METRICS_AVERAGE_MPIPUCLK, 1491 METRICS_THROTTLER_RESIDENCY_PROCHOT, 1492 METRICS_THROTTLER_RESIDENCY_SPL, 1493 METRICS_THROTTLER_RESIDENCY_FPPT, 1494 METRICS_THROTTLER_RESIDENCY_SPPT, 1495 METRICS_THROTTLER_RESIDENCY_THM_CORE, 1496 METRICS_THROTTLER_RESIDENCY_THM_GFX, 1497 METRICS_THROTTLER_RESIDENCY_THM_SOC, 1498 } MetricsMember_t; 1499 1500 enum smu_cmn2asic_mapping_type { 1501 CMN2ASIC_MAPPING_MSG, 1502 CMN2ASIC_MAPPING_CLK, 1503 CMN2ASIC_MAPPING_FEATURE, 1504 CMN2ASIC_MAPPING_TABLE, 1505 CMN2ASIC_MAPPING_PWR, 1506 CMN2ASIC_MAPPING_WORKLOAD, 1507 }; 1508 1509 enum smu_baco_seq { 1510 BACO_SEQ_BACO = 0, 1511 BACO_SEQ_MSR, 1512 BACO_SEQ_BAMACO, 1513 BACO_SEQ_ULPS, 1514 BACO_SEQ_COUNT, 1515 }; 1516 1517 #define MSG_MAP(msg, index, flags) \ 1518 [SMU_MSG_##msg] = {1, (index), (flags)} 1519 1520 #define CLK_MAP(clk, index) \ 1521 [SMU_##clk] = {1, (index)} 1522 1523 #define FEA_MAP(fea) \ 1524 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1525 1526 #define FEA_MAP_REVERSE(fea) \ 1527 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1528 1529 #define FEA_MAP_HALF_REVERSE(fea) \ 1530 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1531 1532 #define TAB_MAP(tab) \ 1533 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1534 1535 #define TAB_MAP_VALID(tab) \ 1536 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1537 1538 #define TAB_MAP_INVALID(tab) \ 1539 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1540 1541 #define PWR_MAP(tab) \ 1542 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1543 1544 #define WORKLOAD_MAP(profile, workload) \ 1545 [profile] = {1, (workload)} 1546 1547 /** 1548 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1549 * 1550 * @dst: Pointer to destination struct 1551 * @first_dst_member: The member name in @dst where the overwrite begins 1552 * @last_dst_member: The member name in @dst where the overwrite ends after 1553 * @src: Pointer to the source struct 1554 * @first_src_member: The member name in @src where the copy begins 1555 * 1556 */ 1557 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1558 src, first_src_member) \ 1559 ({ \ 1560 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1561 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1562 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1563 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1564 __dst_offset; \ 1565 BUILD_BUG_ON(__src_size != __dst_size); \ 1566 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1567 (u8 *)(src) + __src_offset, \ 1568 __dst_size); \ 1569 }) 1570 1571 typedef struct { 1572 uint16_t LowFreq; 1573 uint16_t HighFreq; 1574 } WifiOneBand_t; 1575 1576 typedef struct { 1577 uint32_t WifiBandEntryNum; 1578 WifiOneBand_t WifiBandEntry[11]; 1579 uint32_t MmHubPadding[8]; 1580 } WifiBandEntryTable_t; 1581 1582 #define STR_SOC_PSTATE_POLICY "soc_pstate" 1583 #define STR_XGMI_PLPD_POLICY "xgmi_plpd" 1584 1585 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 1586 enum pp_pm_policy p_type); 1587 1588 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1589 int smu_get_power_limit(void *handle, 1590 uint32_t *limit, 1591 enum pp_power_limit_level pp_limit_level, 1592 enum pp_power_type pp_power_type); 1593 1594 bool smu_mode1_reset_is_support(struct smu_context *smu); 1595 bool smu_mode2_reset_is_support(struct smu_context *smu); 1596 int smu_mode1_reset(struct smu_context *smu); 1597 1598 extern const struct amd_ip_funcs smu_ip_funcs; 1599 1600 bool is_support_sw_smu(struct amdgpu_device *adev); 1601 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1602 int smu_write_watermarks_table(struct smu_context *smu); 1603 1604 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1605 uint32_t *min, uint32_t *max); 1606 1607 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1608 uint32_t min, uint32_t max); 1609 1610 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1611 1612 int smu_set_ac_dc(struct smu_context *smu); 1613 1614 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1615 enum pp_xgmi_plpd_mode mode); 1616 1617 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1618 1619 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1620 1621 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1622 1623 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1624 1625 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1626 1627 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1628 uint64_t event_arg); 1629 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1630 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1631 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1632 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1633 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1634 int smu_send_rma_reason(struct smu_context *smu); 1635 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 1636 int level); 1637 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 1638 enum pp_pm_policy p_type, char *sysbuf); 1639 1640 #endif 1641 #endif 1642