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Searched refs:se_mask (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; in update_cu_mask() local
54 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); in update_cu_mask()
57 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
58 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
59 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
62 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
63 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
64 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
H A Dkfd_mqd_manager_v11.c48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; in update_cu_mask() local
74 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); in update_cu_mask()
76 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
77 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
78 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
79 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
80 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
81 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
82 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
83 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
H A Dkfd_mqd_manager_v12_1.c51 uint32_t *se_mask, uint32_t inst) in mqd_symmetrically_map_cu_mask_v12_1() argument
91 se_mask[i] = 0; in mqd_symmetrically_map_cu_mask_v12_1()
100 se_mask[se] |= en_mask << 30; in mqd_symmetrically_map_cu_mask_v12_1()
102 se_mask[se] |= en_mask << (cu_inc + sh * 16); in mqd_symmetrically_map_cu_mask_v12_1()
118 uint32_t se_mask[2] = {0}; in update_cu_mask() local
124 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); in update_cu_mask()
127 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
128 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
H A Dkfd_mqd_manager_vi.c52 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ in update_cu_mask() local
58 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); in update_cu_mask()
61 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
62 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
63 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
64 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
H A Dkfd_mqd_manager_v10.c49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ in update_cu_mask() local
55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); in update_cu_mask()
58 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
59 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
H A Dkfd_mqd_manager_v9.c74 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; in update_cu_mask() local
80 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); in update_cu_mask()
84 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
85 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
86 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
87 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
91 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
92 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
93 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
94 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
H A Dkfd_mqd_manager.h176 uint32_t *se_mask, uint32_t inst);
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c39 enc110->se_shift->field_name, enc110->se_mask->field_name
321 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) in dce110_stream_encoder_dp_set_stream_attribute()
324 if (enc110->se_mask->DP_VID_N_MUL) in dce110_stream_encoder_dp_set_stream_attribute()
448 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) in dce110_stream_encoder_dp_set_stream_attribute()
571 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { in dce110_stream_encoder_hdmi_set_stream_attribute()
620 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { in dce110_stream_encoder_hdmi_set_stream_attribute()
745 if (enc110->se_mask->HDMI_AVI_INFO_CONT && in dce110_stream_encoder_update_hdmi_info_packets()
746 enc110->se_mask->HDMI_AVI_INFO_SEND) { in dce110_stream_encoder_update_hdmi_info_packets()
780 if (enc110->se_mask->HDMI_AVI_INFO_CONT && in dce110_stream_encoder_update_hdmi_info_packets()
781 enc110->se_mask->HDMI_AVI_INFO_SEND) { in dce110_stream_encoder_update_hdmi_info_packets()
[all …]
H A Ddce_stream_encoder.h705 const struct dce_stream_encoder_mask *se_mask; member
715 const struct dce_stream_encoder_mask *se_mask);
724 const struct dce_stream_encoder_mask *se_mask);
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_stream_encoder.h97 const struct dcn10_stream_encoder_mask *se_mask);
/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c253 static const struct dce_stream_encoder_mask se_mask = { variable
496 &stream_enc_regs[eng_id], &se_shift, &se_mask); in dce100_stream_encoder_create()
501 &stream_enc_regs[eng_id], &se_shift, &se_mask); in dce100_stream_encoder_create()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c3495 unsigned se_mask[4]; in gfx_v8_0_write_harvested_raster_configs() local
3498 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3499 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3500 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3501 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3507 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v8_0_write_harvested_raster_configs()
3508 (!se_mask[2] && !se_mask[3]))) { in gfx_v8_0_write_harvested_raster_configs()
3511 if (!se_mask[0] && !se_mask[1]) { in gfx_v8_0_write_harvested_raster_configs()
3526 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v8_0_write_harvested_raster_configs()
3529 if (!se_mask[idx]) { in gfx_v8_0_write_harvested_raster_configs()
H A Damdgpu_gfx.c533 uint32_t cu_mask_count, uint32_t *se_mask) in amdgpu_gfx_mqd_symmetrically_map_cu_mask() argument
563 se_mask[i] = 0; in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
571 se_mask[se] |= en_mask << (cu + sh * 16); in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
H A Dgfx_v12_0.c3149 uint32_t se_mask[8] = {0}; in gfx_v12_0_compute_mqd_set_cu_mask() local
3168 prop->cu_mask_count, se_mask); in gfx_v12_0_compute_mqd_set_cu_mask()
3170 mqd->compute_static_thread_mgmt_se0 = se_mask[0]; in gfx_v12_0_compute_mqd_set_cu_mask()
3171 mqd->compute_static_thread_mgmt_se1 = se_mask[1]; in gfx_v12_0_compute_mqd_set_cu_mask()
3172 mqd->compute_static_thread_mgmt_se2 = se_mask[2]; in gfx_v12_0_compute_mqd_set_cu_mask()
3173 mqd->compute_static_thread_mgmt_se3 = se_mask[3]; in gfx_v12_0_compute_mqd_set_cu_mask()
H A Dgfx_v11_0.c4308 uint32_t se_mask[8] = {0}; in gfx_v11_0_compute_mqd_set_cu_mask() local
4327 prop->cu_mask_count, se_mask); in gfx_v11_0_compute_mqd_set_cu_mask()
4329 mqd->compute_static_thread_mgmt_se0 = se_mask[0]; in gfx_v11_0_compute_mqd_set_cu_mask()
4330 mqd->compute_static_thread_mgmt_se1 = se_mask[1]; in gfx_v11_0_compute_mqd_set_cu_mask()
4331 mqd->compute_static_thread_mgmt_se2 = se_mask[2]; in gfx_v11_0_compute_mqd_set_cu_mask()
4332 mqd->compute_static_thread_mgmt_se3 = se_mask[3]; in gfx_v11_0_compute_mqd_set_cu_mask()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c270 static const struct dce_stream_encoder_mask se_mask = { variable
613 &stream_enc_regs[eng_id], &se_shift, &se_mask); in dce60_stream_encoder_create()
619 &se_shift, &se_mask); in dce60_stream_encoder_create()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
H A Ddcn32_dio_stream_encoder.h196 const struct dcn10_stream_encoder_mask *se_mask);
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
H A Ddcn35_dio_stream_encoder.h284 const struct dcn10_stream_encoder_mask *se_mask);
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
H A Ddcn314_dio_stream_encoder.h274 const struct dcn10_stream_encoder_mask *se_mask);
/linux/drivers/ntb/hw/idt/
H A Dntb_hw_idt.c637 u32 part_mask, port_mask, se_mask; in idt_init_link() local
669 se_mask = ~(IDT_SEMSK_LINKUP | IDT_SEMSK_LINKDN | IDT_SEMSK_GSIGNAL); in idt_init_link()
670 idt_sw_write(ndev, IDT_SW_SEMSK, se_mask); in idt_init_link()