1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v12_structs.h" 31 #include "gc/gc_12_1_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_device_queue_manager.h" 34 35 static inline struct v12_1_compute_mqd *get_mqd(void *mqd) 36 { 37 return (struct v12_1_compute_mqd *)mqd; 38 } 39 40 static inline struct v12_sdma_mqd *get_sdma_mqd(void *mqd) 41 { 42 return (struct v12_sdma_mqd *)mqd; 43 } 44 45 static void mqd_symmetrically_map_cu_mask_v12_1(struct mqd_manager *mm, 46 const uint32_t *cu_mask, uint32_t cu_mask_count, 47 uint32_t *se_mask, uint32_t inst) 48 { 49 struct amdgpu_cu_info *cu_info = &mm->dev->adev->gfx.cu_info; 50 struct amdgpu_gfx_config *gfx_info = &mm->dev->adev->gfx.config; 51 uint32_t cu_per_sh[2][2] = {0}; 52 uint32_t en_mask = 0x3; 53 int i, se, sh, cu, cu_inc = 0; 54 uint32_t cu_active_per_node; 55 int inc = NUM_XCC(mm->dev->xcc_mask); 56 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; 57 58 cu_active_per_node = cu_info->number / mm->dev->kfd->num_nodes; 59 if (cu_mask_count > cu_active_per_node) 60 cu_mask_count = cu_active_per_node; 61 62 /* 63 * Count active CUs per SE/SH. 64 */ 65 for (se = 0; se < gfx_info->max_shader_engines; se++) 66 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) 67 cu_per_sh[se][sh] = hweight32( 68 cu_info->bitmap[xcc_inst][se][sh]); 69 70 /* Symmetrically map cu_mask to all SEs & SHs: 71 * For GFX 12.1.0, the following code only looks at a 72 * subset of the cu_mask corresponding to the inst parameter. 73 * If we have n XCCs under one GPU node 74 * cu_mask[0] bit0 -> XCC0 se_mask[0] bit0 (XCC0,SE0,SH0,CU0) 75 * cu_mask[0] bit1 -> XCC1 se_mask[0] bit0 (XCC1,SE0,SH0,CU0) 76 * .. 77 * cu_mask[0] bitn -> XCCn se_mask[0] bit0 (XCCn,SE0,SH0,CU0) 78 * cu_mask[0] bit n+1 -> XCC0 se_mask[1] bit0 (XCC0,SE1,SH0,CU0) 79 * 80 * For example, if there are 6 XCCs under 1 KFD node, this code 81 * running for each inst, will look at the bits as: 82 * inst, inst + 6, inst + 12... 83 * 84 * First ensure all CUs are disabled, then enable user specified CUs. 85 */ 86 for (i = 0; i < gfx_info->max_shader_engines; i++) 87 se_mask[i] = 0; 88 89 i = inst; 90 for (cu = 0; cu < 16; cu++) { 91 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { 92 for (se = 0; se < gfx_info->max_shader_engines; se++) { 93 if (cu_per_sh[se][sh] > cu) { 94 if (cu_mask[i / 32] & (1U << (i % 32))) { 95 if (cu == 8 && sh == 0) 96 se_mask[se] |= en_mask << 30; 97 else 98 se_mask[se] |= en_mask << (cu_inc + sh * 16); 99 } 100 i += inc; 101 if (i >= cu_mask_count) 102 return; 103 } 104 } 105 } 106 cu_inc += 2; 107 } 108 } 109 110 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 111 struct mqd_update_info *minfo, uint32_t inst) 112 { 113 struct v12_1_compute_mqd *m; 114 uint32_t se_mask[2] = {0}; 115 116 if (!minfo || !minfo->cu_mask.ptr) 117 return; 118 119 mqd_symmetrically_map_cu_mask_v12_1(mm, 120 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); 121 122 m = get_mqd(mqd); 123 m->compute_static_thread_mgmt_se0 = se_mask[0]; 124 m->compute_static_thread_mgmt_se1 = se_mask[1]; 125 126 pr_debug("update cu mask to %#x %#x\n", 127 m->compute_static_thread_mgmt_se0, 128 m->compute_static_thread_mgmt_se1); 129 } 130 131 static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q) 132 { 133 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 134 /* m->cp_hqd_queue_priority = q->priority; */ 135 } 136 137 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 138 struct queue_properties *q) 139 { 140 u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 141 struct kfd_node *node = mm->dev; 142 struct kfd_mem_obj *mqd_mem_obj; 143 144 if (q->type == KFD_QUEUE_TYPE_COMPUTE) 145 mqd_size *= NUM_XCC(node->xcc_mask); 146 147 if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) 148 return NULL; 149 150 return mqd_mem_obj; 151 } 152 153 static void init_mqd(struct mqd_manager *mm, void **mqd, 154 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 155 struct queue_properties *q) 156 { 157 uint64_t addr; 158 struct v12_1_compute_mqd *m; 159 u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 160 161 m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr; 162 addr = mqd_mem_obj->gpu_addr; 163 164 memset(m, 0, mqd_size); 165 166 m->header = 0xC0310800; 167 m->compute_pipelinestat_enable = 1; 168 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 169 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 170 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 171 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 172 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 173 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 174 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 175 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 176 m->compute_static_thread_mgmt_se8 = 0xFFFFFFFF; 177 178 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 179 0x63 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 180 181 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 182 183 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 184 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 185 186 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 187 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 188 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 189 190 /* Set cp_hqd_hq_status0.c_queue_debug_en to 1 to have the CP set up the 191 * DISPATCH_PTR. This is required for the kfd debugger 192 */ 193 m->cp_hqd_hq_status0 = 1 << 14; 194 195 if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) 196 m->cp_hqd_hq_status0 |= 1 << 29; 197 198 if (q->format == KFD_QUEUE_FORMAT_AQL) { 199 m->cp_hqd_aql_control = 200 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 201 } 202 203 if (mm->dev->kfd->cwsr_enabled) { 204 m->cp_hqd_persistent_state |= 205 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 206 m->cp_hqd_ctx_save_base_addr_lo = 207 lower_32_bits(q->ctx_save_restore_area_address); 208 m->cp_hqd_ctx_save_base_addr_hi = 209 upper_32_bits(q->ctx_save_restore_area_address); 210 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 211 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 212 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 213 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 214 } 215 216 *mqd = m; 217 if (gart_addr) 218 *gart_addr = addr; 219 mm->update_mqd(mm, m, q, NULL); 220 } 221 222 static int load_mqd(struct mqd_manager *mm, void *mqd, 223 uint32_t pipe_id, uint32_t queue_id, 224 struct queue_properties *p, struct mm_struct *mms) 225 { 226 int r = 0; 227 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 228 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 229 230 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 231 (uint32_t __user *)p->write_ptr, 232 wptr_shift, 0, mms, 0); 233 return r; 234 } 235 236 static void update_mqd(struct mqd_manager *mm, void *mqd, 237 struct queue_properties *q, 238 struct mqd_update_info *minfo) 239 { 240 struct v12_1_compute_mqd *m; 241 242 m = get_mqd(mqd); 243 244 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 245 m->cp_hqd_pq_control |= 246 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 247 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 248 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 249 250 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 251 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 252 253 if (q->metadata_queue_size) { 254 /* On GC 12.1 is 64 DWs which is 4 times size of AQL packet */ 255 if (q->metadata_queue_size == q->queue_size * 4) { 256 /* 257 * User application allocates main queue ring and metadata queue ring 258 * with a single allocation. metadata queue ring starts after main 259 * queue ring. 260 */ 261 m->cp_hqd_kd_base = 262 lower_32_bits((q->queue_address + q->queue_size) >> 8); 263 m->cp_hqd_kd_base_hi = 264 upper_32_bits((q->queue_address + q->queue_size) >> 8); 265 266 m->cp_hqd_kd_cntl |= CP_HQD_KD_CNTL__KD_FETCHER_ENABLE_MASK; 267 /* KD_SIZE = 2 for metadata packet = 64 DWs */ 268 m->cp_hqd_kd_cntl |= 2 << CP_HQD_KD_CNTL__KD_SIZE__SHIFT; 269 } else { 270 pr_warn("Invalid metadata ring size, metadata queue will be ignored\n"); 271 } 272 } 273 274 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 275 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 276 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 277 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 278 279 m->cp_hqd_pq_doorbell_control = 280 q->doorbell_off << 281 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 282 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 283 m->cp_hqd_pq_doorbell_control); 284 285 m->cp_hqd_ib_control = 1 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 286 287 /* 288 * HW does not clamp this field correctly. Maximum EOP queue size 289 * is constrained by per-SE EOP done signal count, which is 8-bit. 290 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 291 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 292 * is safe, giving a maximum field value of 0xA. 293 */ 294 m->cp_hqd_eop_control = min(0xA, 295 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 296 m->cp_hqd_eop_base_addr_lo = 297 lower_32_bits(q->eop_ring_buffer_address >> 8); 298 m->cp_hqd_eop_base_addr_hi = 299 upper_32_bits(q->eop_ring_buffer_address >> 8); 300 301 m->cp_hqd_iq_timer = 0; 302 303 m->cp_hqd_vmid = q->vmid; 304 305 if (q->format == KFD_QUEUE_FORMAT_AQL) { 306 /* GC 10 removed WPP_CLAMP from PQ Control */ 307 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 308 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 309 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; 310 m->cp_hqd_pq_doorbell_control |= 311 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 312 } 313 if (mm->dev->kfd->cwsr_enabled) 314 m->cp_hqd_ctx_save_control = 0; 315 316 set_priority(m, q); 317 318 q->is_active = QUEUE_IS_ACTIVE(*q); 319 } 320 321 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 322 { 323 return false; 324 } 325 326 static int get_wave_state(struct mqd_manager *mm, void *mqd, 327 struct queue_properties *q, 328 void __user *ctl_stack, 329 u32 *ctl_stack_used_size, 330 u32 *save_area_used_size) 331 { 332 struct v12_1_compute_mqd *m; 333 struct mqd_user_context_save_area_header header; 334 335 m = get_mqd(mqd); 336 337 /* Control stack is written backwards, while workgroup context data 338 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 339 * Current position is at m->cp_hqd_cntl_stack_offset and 340 * m->cp_hqd_wg_state_offset, respectively. 341 */ 342 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 343 m->cp_hqd_cntl_stack_offset; 344 *save_area_used_size = m->cp_hqd_wg_state_offset - 345 m->cp_hqd_cntl_stack_size; 346 347 /* Control stack is not copied to user mode for GFXv12 because 348 * it's part of the context save area that is already 349 * accessible to user mode 350 */ 351 header.control_stack_size = *ctl_stack_used_size; 352 header.wave_state_size = *save_area_used_size; 353 354 header.wave_state_offset = m->cp_hqd_wg_state_offset; 355 header.control_stack_offset = m->cp_hqd_cntl_stack_offset; 356 357 if (copy_to_user(ctl_stack, &header, sizeof(header))) 358 return -EFAULT; 359 360 return 0; 361 } 362 363 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 364 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 365 struct queue_properties *q) 366 { 367 struct v12_1_compute_mqd *m; 368 369 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 370 371 m = get_mqd(*mqd); 372 373 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 374 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 375 } 376 377 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 378 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 379 struct queue_properties *q) 380 { 381 struct v12_sdma_mqd *m; 382 383 m = (struct v12_sdma_mqd *) mqd_mem_obj->cpu_ptr; 384 385 memset(m, 0, PAGE_SIZE); 386 387 *mqd = m; 388 if (gart_addr) 389 *gart_addr = mqd_mem_obj->gpu_addr; 390 391 mm->update_mqd(mm, m, q, NULL); 392 } 393 394 #define SDMA_RLC_DUMMY_DEFAULT 0xf 395 396 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 397 struct queue_properties *q, 398 struct mqd_update_info *minfo) 399 { 400 struct v12_sdma_mqd *m; 401 402 m = get_sdma_mqd(mqd); 403 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 404 << SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 405 q->vmid << SDMA0_SDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 406 1 << SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 407 6 << SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 408 1 << SDMA0_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; 409 410 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 411 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 412 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 413 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 414 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 415 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 416 m->sdmax_rlcx_doorbell_offset = 417 q->doorbell_off << SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 418 419 m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum 420 << SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) 421 & SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; 422 423 m->sdma_engine_id = q->sdma_engine_id; 424 m->sdma_queue_id = q->sdma_queue_id; 425 426 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 427 428 /* Allow context switch so we don't cross-process starve with a massive 429 * command buffer of long-running SDMA commands 430 * sdmax_rlcx_ib_cntl represent SDMA_QUEUE0_IB_CNTL register 431 */ 432 m->sdmax_rlcx_ib_cntl |= SDMA0_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK; 433 434 q->is_active = QUEUE_IS_ACTIVE(*q); 435 } 436 437 static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj, 438 struct kfd_mem_obj *xcc_mqd_mem_obj, 439 uint64_t offset) 440 { 441 xcc_mqd_mem_obj->mem = (offset == 0) ? 442 mqd_mem_obj->mem : NULL; 443 xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; 444 xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr 445 + offset); 446 } 447 448 static void init_mqd_v12_1(struct mqd_manager *mm, void **mqd, 449 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 450 struct queue_properties *q) 451 { 452 struct v12_1_compute_mqd *m; 453 int xcc = 0; 454 struct kfd_mem_obj xcc_mqd_mem_obj; 455 uint64_t xcc_gart_addr = 0; 456 uint64_t xcc_ctx_save_restore_area_address; 457 uint64_t offset = mm->mqd_stride(mm, q); 458 uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++; 459 460 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 461 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 462 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc); 463 464 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 465 466 m->cp_mqd_stride_size = offset; 467 468 /* 469 * Update the CWSR address for each XCC if CWSR is enabled 470 * and CWSR area is allocated in thunk 471 */ 472 if (mm->dev->kfd->cwsr_enabled && 473 q->ctx_save_restore_area_address) { 474 xcc_ctx_save_restore_area_address = 475 q->ctx_save_restore_area_address + 476 (xcc * q->ctx_save_restore_area_size); 477 478 m->cp_hqd_ctx_save_base_addr_lo = 479 lower_32_bits(xcc_ctx_save_restore_area_address); 480 m->cp_hqd_ctx_save_base_addr_hi = 481 upper_32_bits(xcc_ctx_save_restore_area_address); 482 } 483 484 if (q->format == KFD_QUEUE_FORMAT_AQL) { 485 m->compute_tg_chunk_size = 1; 486 m->compute_current_logical_xcc_id = 487 (local_xcc_start + xcc) % 488 NUM_XCC(mm->dev->xcc_mask); 489 } else { 490 /* PM4 Queue */ 491 m->compute_current_logical_xcc_id = 0; 492 m->compute_tg_chunk_size = 0; 493 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 494 } 495 496 if (xcc == 0) { 497 /* Set the MQD pointer and gart address to XCC0 MQD */ 498 *mqd = m; 499 *gart_addr = xcc_gart_addr; 500 } 501 } 502 } 503 504 static void update_mqd_v12_1(struct mqd_manager *mm, void *mqd, 505 struct queue_properties *q, struct mqd_update_info *minfo) 506 { 507 struct v12_1_compute_mqd *m; 508 int xcc = 0; 509 uint64_t size = mm->mqd_stride(mm, q); 510 511 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 512 m = get_mqd(mqd + size * xcc); 513 update_mqd(mm, m, q, minfo); 514 515 update_cu_mask(mm, m, minfo, xcc); 516 517 if (q->format == KFD_QUEUE_FORMAT_AQL) { 518 m->compute_tg_chunk_size = 1; 519 } else { 520 /* PM4 Queue */ 521 m->compute_current_logical_xcc_id = 0; 522 m->compute_tg_chunk_size = 0; 523 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 524 } 525 } 526 } 527 528 static int destroy_mqd_v12_1(struct mqd_manager *mm, void *mqd, 529 enum kfd_preempt_type type, unsigned int timeout, 530 uint32_t pipe_id, uint32_t queue_id) 531 { 532 uint32_t xcc_mask = mm->dev->xcc_mask; 533 int xcc_id, err, inst = 0; 534 void *xcc_mqd; 535 struct v12_1_compute_mqd *m; 536 uint64_t mqd_offset; 537 538 m = get_mqd(mqd); 539 mqd_offset = m->cp_mqd_stride_size; 540 541 for_each_inst(xcc_id, xcc_mask) { 542 xcc_mqd = mqd + mqd_offset * inst; 543 err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd, 544 type, timeout, pipe_id, 545 queue_id, xcc_id); 546 if (err) { 547 pr_debug("Destroy MQD failed for xcc: %d\n", inst); 548 break; 549 } 550 ++inst; 551 } 552 553 return err; 554 } 555 556 static int load_mqd_v12_1(struct mqd_manager *mm, void *mqd, 557 uint32_t pipe_id, uint32_t queue_id, 558 struct queue_properties *p, struct mm_struct *mms) 559 { 560 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 561 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 562 uint32_t xcc_mask = mm->dev->xcc_mask; 563 int xcc_id, err, inst = 0; 564 void *xcc_mqd; 565 uint64_t mqd_stride_size = mm->mqd_stride(mm, p); 566 567 for_each_inst(xcc_id, xcc_mask) { 568 xcc_mqd = mqd + mqd_stride_size * inst; 569 err = mm->dev->kfd2kgd->hqd_load( 570 mm->dev->adev, xcc_mqd, pipe_id, queue_id, 571 (uint32_t __user *)p->write_ptr, wptr_shift, 0, mms, 572 xcc_id); 573 if (err) { 574 pr_debug("Load MQD failed for xcc: %d\n", inst); 575 break; 576 } 577 ++inst; 578 } 579 580 return err; 581 } 582 583 static int get_wave_state_v12_1(struct mqd_manager *mm, void *mqd, 584 struct queue_properties *q, 585 void __user *ctl_stack, 586 u32 *ctl_stack_used_size, 587 u32 *save_area_used_size) 588 { 589 int xcc, err = 0; 590 void *xcc_mqd; 591 void __user *xcc_ctl_stack; 592 uint64_t mqd_stride_size = mm->mqd_stride(mm, q); 593 u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0; 594 595 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 596 xcc_mqd = mqd + mqd_stride_size * xcc; 597 xcc_ctl_stack = (void __user *)((uintptr_t)ctl_stack + 598 q->ctx_save_restore_area_size * xcc); 599 600 err = get_wave_state(mm, xcc_mqd, q, xcc_ctl_stack, 601 &tmp_ctl_stack_used_size, 602 &tmp_save_area_used_size); 603 if (err) 604 break; 605 606 /* 607 * Set the ctl_stack_used_size and save_area_used_size to 608 * ctl_stack_used_size and save_area_used_size of XCC 0 when 609 * passing the info to user-space. 610 * For multi XCC, user-space would have to look at the header 611 * info of each Control stack area to determine the control 612 * stack size and save area used. 613 */ 614 if (xcc == 0) { 615 *ctl_stack_used_size = tmp_ctl_stack_used_size; 616 *save_area_used_size = tmp_save_area_used_size; 617 } 618 } 619 620 return err; 621 } 622 623 #if defined(CONFIG_DEBUG_FS) 624 625 static int debugfs_show_mqd(struct seq_file *m, void *data) 626 { 627 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 628 data, sizeof(struct v12_1_compute_mqd), false); 629 return 0; 630 } 631 632 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 633 { 634 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 635 data, sizeof(struct v12_sdma_mqd), false); 636 return 0; 637 } 638 639 #endif 640 641 struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, 642 struct kfd_node *dev) 643 { 644 struct mqd_manager *mqd; 645 646 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 647 return NULL; 648 649 mqd = kzalloc_obj(*mqd); 650 if (!mqd) 651 return NULL; 652 653 mqd->dev = dev; 654 655 switch (type) { 656 case KFD_MQD_TYPE_CP: 657 pr_debug("%s@%i\n", __func__, __LINE__); 658 mqd->allocate_mqd = allocate_mqd; 659 mqd->init_mqd = init_mqd_v12_1; 660 mqd->free_mqd = kfd_free_mqd_cp; 661 mqd->load_mqd = load_mqd_v12_1; 662 mqd->update_mqd = update_mqd_v12_1; 663 mqd->destroy_mqd = destroy_mqd_v12_1; 664 mqd->is_occupied = kfd_is_occupied_cp; 665 mqd->mqd_size = sizeof(struct v12_1_compute_mqd); 666 mqd->get_wave_state = get_wave_state_v12_1; 667 mqd->mqd_stride = kfd_mqd_stride; 668 #if defined(CONFIG_DEBUG_FS) 669 mqd->debugfs_show_mqd = debugfs_show_mqd; 670 #endif 671 pr_debug("%s@%i\n", __func__, __LINE__); 672 break; 673 case KFD_MQD_TYPE_HIQ: 674 pr_debug("%s@%i\n", __func__, __LINE__); 675 mqd->allocate_mqd = allocate_hiq_mqd; 676 mqd->init_mqd = init_mqd_hiq; 677 mqd->free_mqd = free_mqd_hiq_sdma; 678 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 679 mqd->update_mqd = update_mqd; 680 mqd->destroy_mqd = kfd_destroy_mqd_cp; 681 mqd->is_occupied = kfd_is_occupied_cp; 682 mqd->mqd_size = sizeof(struct v12_1_compute_mqd); 683 mqd->mqd_stride = kfd_mqd_stride; 684 #if defined(CONFIG_DEBUG_FS) 685 mqd->debugfs_show_mqd = debugfs_show_mqd; 686 #endif 687 mqd->check_preemption_failed = check_preemption_failed; 688 pr_debug("%s@%i\n", __func__, __LINE__); 689 break; 690 case KFD_MQD_TYPE_DIQ: 691 mqd->allocate_mqd = allocate_mqd; 692 mqd->init_mqd = init_mqd_hiq; 693 mqd->free_mqd = kfd_free_mqd_cp; 694 mqd->load_mqd = load_mqd; 695 mqd->update_mqd = update_mqd; 696 mqd->destroy_mqd = kfd_destroy_mqd_cp; 697 mqd->is_occupied = kfd_is_occupied_cp; 698 mqd->mqd_size = sizeof(struct v12_1_compute_mqd); 699 #if defined(CONFIG_DEBUG_FS) 700 mqd->debugfs_show_mqd = debugfs_show_mqd; 701 #endif 702 break; 703 case KFD_MQD_TYPE_SDMA: 704 pr_debug("%s@%i\n", __func__, __LINE__); 705 mqd->allocate_mqd = allocate_mqd; 706 mqd->init_mqd = init_mqd_sdma; 707 mqd->free_mqd = kfd_free_mqd_cp; 708 mqd->load_mqd = kfd_load_mqd_sdma; 709 mqd->update_mqd = update_mqd_sdma; 710 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 711 mqd->is_occupied = kfd_is_occupied_sdma; 712 mqd->mqd_size = sizeof(struct v12_sdma_mqd); 713 mqd->mqd_stride = kfd_mqd_stride; 714 #if defined(CONFIG_DEBUG_FS) 715 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 716 #endif 717 pr_debug("%s@%i\n", __func__, __LINE__); 718 break; 719 default: 720 kfree(mqd); 721 return NULL; 722 } 723 724 return mqd; 725 } 726