1d87f36a0SRajneesh Bhardwaj // SPDX-License-Identifier: GPL-2.0 OR MIT
214328aa5SPhilip Cox /*
3d87f36a0SRajneesh Bhardwaj * Copyright 2018-2022 Advanced Micro Devices, Inc.
414328aa5SPhilip Cox *
514328aa5SPhilip Cox * Permission is hereby granted, free of charge, to any person obtaining a
614328aa5SPhilip Cox * copy of this software and associated documentation files (the "Software"),
714328aa5SPhilip Cox * to deal in the Software without restriction, including without limitation
814328aa5SPhilip Cox * the rights to use, copy, modify, merge, publish, distribute, sublicense,
914328aa5SPhilip Cox * and/or sell copies of the Software, and to permit persons to whom the
1014328aa5SPhilip Cox * Software is furnished to do so, subject to the following conditions:
1114328aa5SPhilip Cox *
1214328aa5SPhilip Cox * The above copyright notice and this permission notice shall be included in
1314328aa5SPhilip Cox * all copies or substantial portions of the Software.
1414328aa5SPhilip Cox *
1514328aa5SPhilip Cox * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1614328aa5SPhilip Cox * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1714328aa5SPhilip Cox * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1814328aa5SPhilip Cox * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1914328aa5SPhilip Cox * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2014328aa5SPhilip Cox * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2114328aa5SPhilip Cox * OTHER DEALINGS IN THE SOFTWARE.
2214328aa5SPhilip Cox *
2314328aa5SPhilip Cox */
2414328aa5SPhilip Cox
2514328aa5SPhilip Cox #include <linux/printk.h>
2614328aa5SPhilip Cox #include <linux/slab.h>
2714328aa5SPhilip Cox #include <linux/uaccess.h>
2814328aa5SPhilip Cox #include "kfd_priv.h"
2914328aa5SPhilip Cox #include "kfd_mqd_manager.h"
3014328aa5SPhilip Cox #include "v10_structs.h"
3114328aa5SPhilip Cox #include "gc/gc_10_1_0_offset.h"
3214328aa5SPhilip Cox #include "gc/gc_10_1_0_sh_mask.h"
3314328aa5SPhilip Cox #include "amdgpu_amdkfd.h"
3414328aa5SPhilip Cox
get_mqd(void * mqd)3514328aa5SPhilip Cox static inline struct v10_compute_mqd *get_mqd(void *mqd)
3614328aa5SPhilip Cox {
3714328aa5SPhilip Cox return (struct v10_compute_mqd *)mqd;
3814328aa5SPhilip Cox }
3914328aa5SPhilip Cox
get_sdma_mqd(void * mqd)4014328aa5SPhilip Cox static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
4114328aa5SPhilip Cox {
4214328aa5SPhilip Cox return (struct v10_sdma_mqd *)mqd;
4314328aa5SPhilip Cox }
4414328aa5SPhilip Cox
update_cu_mask(struct mqd_manager * mm,void * mqd,struct mqd_update_info * minfo)4514328aa5SPhilip Cox static void update_cu_mask(struct mqd_manager *mm, void *mqd,
467c695a2cSLang Yu struct mqd_update_info *minfo)
4714328aa5SPhilip Cox {
4814328aa5SPhilip Cox struct v10_compute_mqd *m;
4914328aa5SPhilip Cox uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
5014328aa5SPhilip Cox
5169a8c3aeSJonathan Kim if (!minfo || !minfo->cu_mask.ptr)
5214328aa5SPhilip Cox return;
5314328aa5SPhilip Cox
5414328aa5SPhilip Cox mqd_symmetrically_map_cu_mask(mm,
55fc6efed2SMukul Joshi minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);
5614328aa5SPhilip Cox
5714328aa5SPhilip Cox m = get_mqd(mqd);
5814328aa5SPhilip Cox m->compute_static_thread_mgmt_se0 = se_mask[0];
5914328aa5SPhilip Cox m->compute_static_thread_mgmt_se1 = se_mask[1];
6014328aa5SPhilip Cox m->compute_static_thread_mgmt_se2 = se_mask[2];
6114328aa5SPhilip Cox m->compute_static_thread_mgmt_se3 = se_mask[3];
6214328aa5SPhilip Cox
6314328aa5SPhilip Cox pr_debug("update cu mask to %#x %#x %#x %#x\n",
6414328aa5SPhilip Cox m->compute_static_thread_mgmt_se0,
6514328aa5SPhilip Cox m->compute_static_thread_mgmt_se1,
6614328aa5SPhilip Cox m->compute_static_thread_mgmt_se2,
6714328aa5SPhilip Cox m->compute_static_thread_mgmt_se3);
6814328aa5SPhilip Cox }
6914328aa5SPhilip Cox
set_priority(struct v10_compute_mqd * m,struct queue_properties * q)704d428e91SYong Zhao static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q)
714d428e91SYong Zhao {
724d428e91SYong Zhao m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
734d428e91SYong Zhao m->cp_hqd_queue_priority = q->priority;
744d428e91SYong Zhao }
754d428e91SYong Zhao
allocate_mqd(struct kfd_node * kfd,struct queue_properties * q)768dc1db31SMukul Joshi static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd,
7714328aa5SPhilip Cox struct queue_properties *q)
7814328aa5SPhilip Cox {
7922471a58SYong Zhao struct kfd_mem_obj *mqd_mem_obj;
8014328aa5SPhilip Cox
8122471a58SYong Zhao if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),
8222471a58SYong Zhao &mqd_mem_obj))
8314328aa5SPhilip Cox return NULL;
8414328aa5SPhilip Cox
8514328aa5SPhilip Cox return mqd_mem_obj;
8614328aa5SPhilip Cox }
8714328aa5SPhilip Cox
init_mqd(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)8814328aa5SPhilip Cox static void init_mqd(struct mqd_manager *mm, void **mqd,
8914328aa5SPhilip Cox struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
9014328aa5SPhilip Cox struct queue_properties *q)
9114328aa5SPhilip Cox {
9214328aa5SPhilip Cox uint64_t addr;
9314328aa5SPhilip Cox struct v10_compute_mqd *m;
9414328aa5SPhilip Cox
9514328aa5SPhilip Cox m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr;
9614328aa5SPhilip Cox addr = mqd_mem_obj->gpu_addr;
9714328aa5SPhilip Cox
9814328aa5SPhilip Cox memset(m, 0, sizeof(struct v10_compute_mqd));
9914328aa5SPhilip Cox
10014328aa5SPhilip Cox m->header = 0xC0310800;
10114328aa5SPhilip Cox m->compute_pipelinestat_enable = 1;
10214328aa5SPhilip Cox m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
10314328aa5SPhilip Cox m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
10414328aa5SPhilip Cox m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
10514328aa5SPhilip Cox m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
10614328aa5SPhilip Cox
10714328aa5SPhilip Cox m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
10814328aa5SPhilip Cox 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
10914328aa5SPhilip Cox
11014328aa5SPhilip Cox m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
11114328aa5SPhilip Cox
11214328aa5SPhilip Cox m->cp_mqd_base_addr_lo = lower_32_bits(addr);
11314328aa5SPhilip Cox m->cp_mqd_base_addr_hi = upper_32_bits(addr);
11414328aa5SPhilip Cox
11514328aa5SPhilip Cox m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
11614328aa5SPhilip Cox 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
1175d7c6f18SJoseph Greathouse 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
11814328aa5SPhilip Cox
1194504f143SJonathan Kim /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the
1204504f143SJonathan Kim * DISPATCH_PTR. This is required for the kfd debugger
1214504f143SJonathan Kim */
1224504f143SJonathan Kim m->cp_hqd_hq_scheduler0 = 1 << 14;
1234504f143SJonathan Kim
12414328aa5SPhilip Cox if (q->format == KFD_QUEUE_FORMAT_AQL) {
12514328aa5SPhilip Cox m->cp_hqd_aql_control =
12614328aa5SPhilip Cox 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
12714328aa5SPhilip Cox }
12814328aa5SPhilip Cox
1298dc1db31SMukul Joshi if (mm->dev->kfd->cwsr_enabled) {
13014328aa5SPhilip Cox m->cp_hqd_persistent_state |=
13114328aa5SPhilip Cox (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
13214328aa5SPhilip Cox m->cp_hqd_ctx_save_base_addr_lo =
13314328aa5SPhilip Cox lower_32_bits(q->ctx_save_restore_area_address);
13414328aa5SPhilip Cox m->cp_hqd_ctx_save_base_addr_hi =
13514328aa5SPhilip Cox upper_32_bits(q->ctx_save_restore_area_address);
13614328aa5SPhilip Cox m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
13714328aa5SPhilip Cox m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
13814328aa5SPhilip Cox m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
13914328aa5SPhilip Cox m->cp_hqd_wg_state_offset = q->ctl_stack_size;
14014328aa5SPhilip Cox }
14114328aa5SPhilip Cox
14214328aa5SPhilip Cox *mqd = m;
14314328aa5SPhilip Cox if (gart_addr)
14414328aa5SPhilip Cox *gart_addr = addr;
145c6e559ebSLang Yu mm->update_mqd(mm, m, q, NULL);
14614328aa5SPhilip Cox }
14714328aa5SPhilip Cox
load_mqd(struct mqd_manager * mm,void * mqd,uint32_t pipe_id,uint32_t queue_id,struct queue_properties * p,struct mm_struct * mms)14814328aa5SPhilip Cox static int load_mqd(struct mqd_manager *mm, void *mqd,
14914328aa5SPhilip Cox uint32_t pipe_id, uint32_t queue_id,
15014328aa5SPhilip Cox struct queue_properties *p, struct mm_struct *mms)
15114328aa5SPhilip Cox {
15214328aa5SPhilip Cox int r = 0;
15314328aa5SPhilip Cox /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
15414328aa5SPhilip Cox uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
15514328aa5SPhilip Cox
156420185fdSGraham Sider r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
15714328aa5SPhilip Cox (uint32_t __user *)p->write_ptr,
158e2069a7bSMukul Joshi wptr_shift, 0, mms, 0);
15914328aa5SPhilip Cox return r;
16014328aa5SPhilip Cox }
16114328aa5SPhilip Cox
update_mqd(struct mqd_manager * mm,void * mqd,struct queue_properties * q,struct mqd_update_info * minfo)16214328aa5SPhilip Cox static void update_mqd(struct mqd_manager *mm, void *mqd,
163c6e559ebSLang Yu struct queue_properties *q,
164c6e559ebSLang Yu struct mqd_update_info *minfo)
16514328aa5SPhilip Cox {
16614328aa5SPhilip Cox struct v10_compute_mqd *m;
16714328aa5SPhilip Cox
16814328aa5SPhilip Cox m = get_mqd(mqd);
16914328aa5SPhilip Cox
17014328aa5SPhilip Cox m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
17114328aa5SPhilip Cox m->cp_hqd_pq_control |=
17214328aa5SPhilip Cox ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
17303ff6d72SAlex Deucher m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
17414328aa5SPhilip Cox pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
17514328aa5SPhilip Cox
17614328aa5SPhilip Cox m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
17714328aa5SPhilip Cox m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
17814328aa5SPhilip Cox
17914328aa5SPhilip Cox m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
18014328aa5SPhilip Cox m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
18114328aa5SPhilip Cox m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
18214328aa5SPhilip Cox m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
18314328aa5SPhilip Cox
18414328aa5SPhilip Cox m->cp_hqd_pq_doorbell_control =
18514328aa5SPhilip Cox q->doorbell_off <<
18614328aa5SPhilip Cox CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
18714328aa5SPhilip Cox pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
18814328aa5SPhilip Cox m->cp_hqd_pq_doorbell_control);
18914328aa5SPhilip Cox
19014328aa5SPhilip Cox m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT;
19114328aa5SPhilip Cox
19214328aa5SPhilip Cox /*
19314328aa5SPhilip Cox * HW does not clamp this field correctly. Maximum EOP queue size
19414328aa5SPhilip Cox * is constrained by per-SE EOP done signal count, which is 8-bit.
19514328aa5SPhilip Cox * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
19614328aa5SPhilip Cox * more than (EOP entry count - 1) so a queue size of 0x800 dwords
19714328aa5SPhilip Cox * is safe, giving a maximum field value of 0xA.
19814328aa5SPhilip Cox */
19914328aa5SPhilip Cox m->cp_hqd_eop_control = min(0xA,
20014328aa5SPhilip Cox ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
20114328aa5SPhilip Cox m->cp_hqd_eop_base_addr_lo =
20214328aa5SPhilip Cox lower_32_bits(q->eop_ring_buffer_address >> 8);
20314328aa5SPhilip Cox m->cp_hqd_eop_base_addr_hi =
20414328aa5SPhilip Cox upper_32_bits(q->eop_ring_buffer_address >> 8);
20514328aa5SPhilip Cox
20614328aa5SPhilip Cox m->cp_hqd_iq_timer = 0;
20714328aa5SPhilip Cox
20814328aa5SPhilip Cox m->cp_hqd_vmid = q->vmid;
20914328aa5SPhilip Cox
21014328aa5SPhilip Cox if (q->format == KFD_QUEUE_FORMAT_AQL) {
21114328aa5SPhilip Cox /* GC 10 removed WPP_CLAMP from PQ Control */
21214328aa5SPhilip Cox m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
21314328aa5SPhilip Cox 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
21414328aa5SPhilip Cox 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT;
21514328aa5SPhilip Cox m->cp_hqd_pq_doorbell_control |=
21614328aa5SPhilip Cox 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
21714328aa5SPhilip Cox }
2188dc1db31SMukul Joshi if (mm->dev->kfd->cwsr_enabled)
21914328aa5SPhilip Cox m->cp_hqd_ctx_save_control = 0;
22014328aa5SPhilip Cox
2217c695a2cSLang Yu update_cu_mask(mm, mqd, minfo);
2224d428e91SYong Zhao set_priority(m, q);
22314328aa5SPhilip Cox
2242a7f8883SYong Zhao q->is_active = QUEUE_IS_ACTIVE(*q);
22514328aa5SPhilip Cox }
22614328aa5SPhilip Cox
check_preemption_failed(struct mqd_manager * mm,void * mqd)227*0991a4c1SMukul Joshi static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)
22851a0f459SOak Zeng {
22951a0f459SOak Zeng struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd;
23051a0f459SOak Zeng
231*0991a4c1SMukul Joshi return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0);
23251a0f459SOak Zeng }
23351a0f459SOak Zeng
get_wave_state(struct mqd_manager * mm,void * mqd,struct queue_properties * q,void __user * ctl_stack,u32 * ctl_stack_used_size,u32 * save_area_used_size)23414328aa5SPhilip Cox static int get_wave_state(struct mqd_manager *mm, void *mqd,
2357fe51e6fSMukul Joshi struct queue_properties *q,
23614328aa5SPhilip Cox void __user *ctl_stack,
23714328aa5SPhilip Cox u32 *ctl_stack_used_size,
23814328aa5SPhilip Cox u32 *save_area_used_size)
23914328aa5SPhilip Cox {
24014328aa5SPhilip Cox struct v10_compute_mqd *m;
241a70a93faSJonathan Kim struct kfd_context_save_area_header header;
24214328aa5SPhilip Cox
24314328aa5SPhilip Cox m = get_mqd(mqd);
24414328aa5SPhilip Cox
245681a9167SYong Zhao /* Control stack is written backwards, while workgroup context data
246681a9167SYong Zhao * is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
247681a9167SYong Zhao * Current position is at m->cp_hqd_cntl_stack_offset and
248681a9167SYong Zhao * m->cp_hqd_wg_state_offset, respectively.
249681a9167SYong Zhao */
25014328aa5SPhilip Cox *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
25114328aa5SPhilip Cox m->cp_hqd_cntl_stack_offset;
25214328aa5SPhilip Cox *save_area_used_size = m->cp_hqd_wg_state_offset -
25314328aa5SPhilip Cox m->cp_hqd_cntl_stack_size;
25414328aa5SPhilip Cox
255681a9167SYong Zhao /* Control stack is not copied to user mode for GFXv10 because
256681a9167SYong Zhao * it's part of the context save area that is already
257681a9167SYong Zhao * accessible to user mode
258681a9167SYong Zhao */
25914328aa5SPhilip Cox
260a70a93faSJonathan Kim header.wave_state.control_stack_size = *ctl_stack_used_size;
261a70a93faSJonathan Kim header.wave_state.wave_state_size = *save_area_used_size;
262a70a93faSJonathan Kim
263a70a93faSJonathan Kim header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset;
264a70a93faSJonathan Kim header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset;
265a70a93faSJonathan Kim
266a70a93faSJonathan Kim if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state)))
267a70a93faSJonathan Kim return -EFAULT;
268a70a93faSJonathan Kim
26914328aa5SPhilip Cox return 0;
27014328aa5SPhilip Cox }
27114328aa5SPhilip Cox
checkpoint_mqd(struct mqd_manager * mm,void * mqd,void * mqd_dst,void * ctl_stack_dst)2723a9822d7SDavid Yat Sin static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
27342c6c482SDavid Yat Sin {
27442c6c482SDavid Yat Sin struct v10_compute_mqd *m;
27542c6c482SDavid Yat Sin
27642c6c482SDavid Yat Sin m = get_mqd(mqd);
27742c6c482SDavid Yat Sin
27842c6c482SDavid Yat Sin memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd));
27942c6c482SDavid Yat Sin }
28042c6c482SDavid Yat Sin
restore_mqd(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * qp,const void * mqd_src,const void * ctl_stack_src,const u32 ctl_stack_size)28142c6c482SDavid Yat Sin static void restore_mqd(struct mqd_manager *mm, void **mqd,
28242c6c482SDavid Yat Sin struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
28342c6c482SDavid Yat Sin struct queue_properties *qp,
2843a9822d7SDavid Yat Sin const void *mqd_src,
2853a9822d7SDavid Yat Sin const void *ctl_stack_src, const u32 ctl_stack_size)
28642c6c482SDavid Yat Sin {
28742c6c482SDavid Yat Sin uint64_t addr;
28842c6c482SDavid Yat Sin struct v10_compute_mqd *m;
28942c6c482SDavid Yat Sin
29042c6c482SDavid Yat Sin m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr;
29142c6c482SDavid Yat Sin addr = mqd_mem_obj->gpu_addr;
29242c6c482SDavid Yat Sin
29342c6c482SDavid Yat Sin memcpy(m, mqd_src, sizeof(*m));
29442c6c482SDavid Yat Sin
29542c6c482SDavid Yat Sin *mqd = m;
29642c6c482SDavid Yat Sin if (gart_addr)
29742c6c482SDavid Yat Sin *gart_addr = addr;
29842c6c482SDavid Yat Sin
29942c6c482SDavid Yat Sin m->cp_hqd_pq_doorbell_control =
30042c6c482SDavid Yat Sin qp->doorbell_off <<
30142c6c482SDavid Yat Sin CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
30242c6c482SDavid Yat Sin pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
30342c6c482SDavid Yat Sin m->cp_hqd_pq_doorbell_control);
30442c6c482SDavid Yat Sin
30542c6c482SDavid Yat Sin qp->is_active = 0;
30642c6c482SDavid Yat Sin }
30742c6c482SDavid Yat Sin
init_mqd_hiq(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)30814328aa5SPhilip Cox static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
30914328aa5SPhilip Cox struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
31014328aa5SPhilip Cox struct queue_properties *q)
31114328aa5SPhilip Cox {
31214328aa5SPhilip Cox struct v10_compute_mqd *m;
31314328aa5SPhilip Cox
31414328aa5SPhilip Cox init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
31514328aa5SPhilip Cox
31614328aa5SPhilip Cox m = get_mqd(*mqd);
31714328aa5SPhilip Cox
31814328aa5SPhilip Cox m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
31914328aa5SPhilip Cox 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
32014328aa5SPhilip Cox }
32114328aa5SPhilip Cox
destroy_hiq_mqd(struct mqd_manager * mm,void * mqd,enum kfd_preempt_type type,unsigned int timeout,uint32_t pipe_id,uint32_t queue_id)3229041b53aSMukul Joshi static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd,
3239041b53aSMukul Joshi enum kfd_preempt_type type, unsigned int timeout,
3249041b53aSMukul Joshi uint32_t pipe_id, uint32_t queue_id)
3259041b53aSMukul Joshi {
3269041b53aSMukul Joshi int err;
3279041b53aSMukul Joshi struct v10_compute_mqd *m;
3289041b53aSMukul Joshi u32 doorbell_off;
3299041b53aSMukul Joshi
3309041b53aSMukul Joshi m = get_mqd(mqd);
3319041b53aSMukul Joshi
3329041b53aSMukul Joshi doorbell_off = m->cp_hqd_pq_doorbell_control >>
3339041b53aSMukul Joshi CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
3349041b53aSMukul Joshi
3359041b53aSMukul Joshi err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0);
3369041b53aSMukul Joshi if (err)
3379041b53aSMukul Joshi pr_debug("Destroy HIQ MQD failed: %d\n", err);
3389041b53aSMukul Joshi
3399041b53aSMukul Joshi return err;
3409041b53aSMukul Joshi }
3419041b53aSMukul Joshi
init_mqd_sdma(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)34214328aa5SPhilip Cox static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
34314328aa5SPhilip Cox struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
34414328aa5SPhilip Cox struct queue_properties *q)
34514328aa5SPhilip Cox {
34614328aa5SPhilip Cox struct v10_sdma_mqd *m;
34714328aa5SPhilip Cox
34814328aa5SPhilip Cox m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr;
34914328aa5SPhilip Cox
35014328aa5SPhilip Cox memset(m, 0, sizeof(struct v10_sdma_mqd));
35114328aa5SPhilip Cox
35214328aa5SPhilip Cox *mqd = m;
35314328aa5SPhilip Cox if (gart_addr)
35414328aa5SPhilip Cox *gart_addr = mqd_mem_obj->gpu_addr;
35514328aa5SPhilip Cox
356c6e559ebSLang Yu mm->update_mqd(mm, m, q, NULL);
35714328aa5SPhilip Cox }
35814328aa5SPhilip Cox
35914328aa5SPhilip Cox #define SDMA_RLC_DUMMY_DEFAULT 0xf
36014328aa5SPhilip Cox
update_mqd_sdma(struct mqd_manager * mm,void * mqd,struct queue_properties * q,struct mqd_update_info * minfo)36114328aa5SPhilip Cox static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
362c6e559ebSLang Yu struct queue_properties *q,
363c6e559ebSLang Yu struct mqd_update_info *minfo)
36414328aa5SPhilip Cox {
36514328aa5SPhilip Cox struct v10_sdma_mqd *m;
36614328aa5SPhilip Cox
36714328aa5SPhilip Cox m = get_sdma_mqd(mqd);
36814328aa5SPhilip Cox m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
36914328aa5SPhilip Cox << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
37014328aa5SPhilip Cox q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
37114328aa5SPhilip Cox 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
37214328aa5SPhilip Cox 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
37314328aa5SPhilip Cox
37414328aa5SPhilip Cox m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
37514328aa5SPhilip Cox m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
37614328aa5SPhilip Cox m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
37714328aa5SPhilip Cox m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
37814328aa5SPhilip Cox m->sdmax_rlcx_doorbell_offset =
37914328aa5SPhilip Cox q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
38014328aa5SPhilip Cox
38114328aa5SPhilip Cox m->sdma_engine_id = q->sdma_engine_id;
38214328aa5SPhilip Cox m->sdma_queue_id = q->sdma_queue_id;
38314328aa5SPhilip Cox m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
38414328aa5SPhilip Cox
3852a7f8883SYong Zhao q->is_active = QUEUE_IS_ACTIVE(*q);
38614328aa5SPhilip Cox }
38714328aa5SPhilip Cox
checkpoint_mqd_sdma(struct mqd_manager * mm,void * mqd,void * mqd_dst,void * ctl_stack_dst)3883a9822d7SDavid Yat Sin static void checkpoint_mqd_sdma(struct mqd_manager *mm,
3893a9822d7SDavid Yat Sin void *mqd,
3903a9822d7SDavid Yat Sin void *mqd_dst,
3913a9822d7SDavid Yat Sin void *ctl_stack_dst)
39242c6c482SDavid Yat Sin {
39342c6c482SDavid Yat Sin struct v10_sdma_mqd *m;
39442c6c482SDavid Yat Sin
39542c6c482SDavid Yat Sin m = get_sdma_mqd(mqd);
39642c6c482SDavid Yat Sin
39742c6c482SDavid Yat Sin memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd));
39842c6c482SDavid Yat Sin }
39942c6c482SDavid Yat Sin
restore_mqd_sdma(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * qp,const void * mqd_src,const void * ctl_stack_src,const u32 ctl_stack_size)40042c6c482SDavid Yat Sin static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd,
40142c6c482SDavid Yat Sin struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
40242c6c482SDavid Yat Sin struct queue_properties *qp,
4033a9822d7SDavid Yat Sin const void *mqd_src,
4043a9822d7SDavid Yat Sin const void *ctl_stack_src,
4053a9822d7SDavid Yat Sin const u32 ctl_stack_size)
40642c6c482SDavid Yat Sin {
40742c6c482SDavid Yat Sin uint64_t addr;
40842c6c482SDavid Yat Sin struct v10_sdma_mqd *m;
40942c6c482SDavid Yat Sin
41042c6c482SDavid Yat Sin m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr;
41142c6c482SDavid Yat Sin addr = mqd_mem_obj->gpu_addr;
41242c6c482SDavid Yat Sin
41342c6c482SDavid Yat Sin memcpy(m, mqd_src, sizeof(*m));
41442c6c482SDavid Yat Sin
41542c6c482SDavid Yat Sin m->sdmax_rlcx_doorbell_offset =
41642c6c482SDavid Yat Sin qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
41742c6c482SDavid Yat Sin
41842c6c482SDavid Yat Sin *mqd = m;
41942c6c482SDavid Yat Sin if (gart_addr)
42042c6c482SDavid Yat Sin *gart_addr = addr;
42142c6c482SDavid Yat Sin
42242c6c482SDavid Yat Sin qp->is_active = 0;
42342c6c482SDavid Yat Sin }
42442c6c482SDavid Yat Sin
42514328aa5SPhilip Cox #if defined(CONFIG_DEBUG_FS)
42614328aa5SPhilip Cox
debugfs_show_mqd(struct seq_file * m,void * data)42714328aa5SPhilip Cox static int debugfs_show_mqd(struct seq_file *m, void *data)
42814328aa5SPhilip Cox {
42914328aa5SPhilip Cox seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
43014328aa5SPhilip Cox data, sizeof(struct v10_compute_mqd), false);
43114328aa5SPhilip Cox return 0;
43214328aa5SPhilip Cox }
43314328aa5SPhilip Cox
debugfs_show_mqd_sdma(struct seq_file * m,void * data)43414328aa5SPhilip Cox static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
43514328aa5SPhilip Cox {
43614328aa5SPhilip Cox seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
43714328aa5SPhilip Cox data, sizeof(struct v10_sdma_mqd), false);
43814328aa5SPhilip Cox return 0;
43914328aa5SPhilip Cox }
44014328aa5SPhilip Cox
44114328aa5SPhilip Cox #endif
44214328aa5SPhilip Cox
mqd_manager_init_v10(enum KFD_MQD_TYPE type,struct kfd_node * dev)44314328aa5SPhilip Cox struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
4448dc1db31SMukul Joshi struct kfd_node *dev)
44514328aa5SPhilip Cox {
44614328aa5SPhilip Cox struct mqd_manager *mqd;
44714328aa5SPhilip Cox
44814328aa5SPhilip Cox if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
44914328aa5SPhilip Cox return NULL;
45014328aa5SPhilip Cox
4518c27a0c4SYong Zhao mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
45214328aa5SPhilip Cox if (!mqd)
45314328aa5SPhilip Cox return NULL;
45414328aa5SPhilip Cox
45514328aa5SPhilip Cox mqd->dev = dev;
45614328aa5SPhilip Cox
45714328aa5SPhilip Cox switch (type) {
45814328aa5SPhilip Cox case KFD_MQD_TYPE_CP:
45914328aa5SPhilip Cox pr_debug("%s@%i\n", __func__, __LINE__);
46014328aa5SPhilip Cox mqd->allocate_mqd = allocate_mqd;
46114328aa5SPhilip Cox mqd->init_mqd = init_mqd;
462a439b890SMukul Joshi mqd->free_mqd = kfd_free_mqd_cp;
46314328aa5SPhilip Cox mqd->load_mqd = load_mqd;
46414328aa5SPhilip Cox mqd->update_mqd = update_mqd;
465a439b890SMukul Joshi mqd->destroy_mqd = kfd_destroy_mqd_cp;
466a439b890SMukul Joshi mqd->is_occupied = kfd_is_occupied_cp;
46714328aa5SPhilip Cox mqd->mqd_size = sizeof(struct v10_compute_mqd);
46814328aa5SPhilip Cox mqd->get_wave_state = get_wave_state;
46942c6c482SDavid Yat Sin mqd->checkpoint_mqd = checkpoint_mqd;
47042c6c482SDavid Yat Sin mqd->restore_mqd = restore_mqd;
4712f77b9a2SMukul Joshi mqd->mqd_stride = kfd_mqd_stride;
47214328aa5SPhilip Cox #if defined(CONFIG_DEBUG_FS)
47314328aa5SPhilip Cox mqd->debugfs_show_mqd = debugfs_show_mqd;
47414328aa5SPhilip Cox #endif
47514328aa5SPhilip Cox pr_debug("%s@%i\n", __func__, __LINE__);
47614328aa5SPhilip Cox break;
47714328aa5SPhilip Cox case KFD_MQD_TYPE_HIQ:
47814328aa5SPhilip Cox pr_debug("%s@%i\n", __func__, __LINE__);
47914328aa5SPhilip Cox mqd->allocate_mqd = allocate_hiq_mqd;
48014328aa5SPhilip Cox mqd->init_mqd = init_mqd_hiq;
48114328aa5SPhilip Cox mqd->free_mqd = free_mqd_hiq_sdma;
482a439b890SMukul Joshi mqd->load_mqd = kfd_hiq_load_mqd_kiq;
483c8c50a7eSYong Zhao mqd->update_mqd = update_mqd;
4849041b53aSMukul Joshi mqd->destroy_mqd = destroy_hiq_mqd;
485a439b890SMukul Joshi mqd->is_occupied = kfd_is_occupied_cp;
48614328aa5SPhilip Cox mqd->mqd_size = sizeof(struct v10_compute_mqd);
4872f77b9a2SMukul Joshi mqd->mqd_stride = kfd_mqd_stride;
48814328aa5SPhilip Cox #if defined(CONFIG_DEBUG_FS)
48914328aa5SPhilip Cox mqd->debugfs_show_mqd = debugfs_show_mqd;
49014328aa5SPhilip Cox #endif
49126d97182SMukul Joshi mqd->check_preemption_failed = check_preemption_failed;
49214328aa5SPhilip Cox pr_debug("%s@%i\n", __func__, __LINE__);
49314328aa5SPhilip Cox break;
49414328aa5SPhilip Cox case KFD_MQD_TYPE_DIQ:
4957633c5e0SYong Zhao mqd->allocate_mqd = allocate_mqd;
49614328aa5SPhilip Cox mqd->init_mqd = init_mqd_hiq;
497a439b890SMukul Joshi mqd->free_mqd = kfd_free_mqd_cp;
49814328aa5SPhilip Cox mqd->load_mqd = load_mqd;
499c8c50a7eSYong Zhao mqd->update_mqd = update_mqd;
500a439b890SMukul Joshi mqd->destroy_mqd = kfd_destroy_mqd_cp;
501a439b890SMukul Joshi mqd->is_occupied = kfd_is_occupied_cp;
50214328aa5SPhilip Cox mqd->mqd_size = sizeof(struct v10_compute_mqd);
50314328aa5SPhilip Cox #if defined(CONFIG_DEBUG_FS)
50414328aa5SPhilip Cox mqd->debugfs_show_mqd = debugfs_show_mqd;
50514328aa5SPhilip Cox #endif
50614328aa5SPhilip Cox break;
50714328aa5SPhilip Cox case KFD_MQD_TYPE_SDMA:
50814328aa5SPhilip Cox pr_debug("%s@%i\n", __func__, __LINE__);
50914328aa5SPhilip Cox mqd->allocate_mqd = allocate_sdma_mqd;
51014328aa5SPhilip Cox mqd->init_mqd = init_mqd_sdma;
51114328aa5SPhilip Cox mqd->free_mqd = free_mqd_hiq_sdma;
512a439b890SMukul Joshi mqd->load_mqd = kfd_load_mqd_sdma;
51314328aa5SPhilip Cox mqd->update_mqd = update_mqd_sdma;
514a439b890SMukul Joshi mqd->destroy_mqd = kfd_destroy_mqd_sdma;
515a439b890SMukul Joshi mqd->is_occupied = kfd_is_occupied_sdma;
51642c6c482SDavid Yat Sin mqd->checkpoint_mqd = checkpoint_mqd_sdma;
51742c6c482SDavid Yat Sin mqd->restore_mqd = restore_mqd_sdma;
51814328aa5SPhilip Cox mqd->mqd_size = sizeof(struct v10_sdma_mqd);
5192f77b9a2SMukul Joshi mqd->mqd_stride = kfd_mqd_stride;
52014328aa5SPhilip Cox #if defined(CONFIG_DEBUG_FS)
52114328aa5SPhilip Cox mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
52214328aa5SPhilip Cox #endif
52314328aa5SPhilip Cox pr_debug("%s@%i\n", __func__, __LINE__);
52414328aa5SPhilip Cox break;
52514328aa5SPhilip Cox default:
52614328aa5SPhilip Cox kfree(mqd);
52714328aa5SPhilip Cox return NULL;
52814328aa5SPhilip Cox }
52914328aa5SPhilip Cox
53014328aa5SPhilip Cox return mqd;
53114328aa5SPhilip Cox }
532