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Searched refs:rs1 (Results 1 – 23 of 23) sorted by relevance

/linux/arch/riscv/net/
H A Dbpf_jit.h232 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument
235 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_r_insn()
239 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument
241 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn()
245 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_s_insn() argument
249 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_s_insn()
253 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_b_insn() argument
258 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_b_insn()
277 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1, in rv_amo_insn() argument
282 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn()
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H A Dbpf_jit_comp32.c576 const s8 *rs1 = bpf_get_reg64(src1, tmp1, ctx); in emit_branch_r64() local
592 emit(rv_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
593 emit(rv_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
596 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
597 emit(rv_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
598 emit(rv_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
601 emit(rv_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
602 emit(rv_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
603 emit(rv_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
606 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
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/linux/arch/sparc/kernel/
H A Dvisemul.c140 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
143 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
296 unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val; in edge() local
300 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); in edge()
304 rs1 = rs1 & 0xffffffff; in edge()
311 left = edge8_tab[rs1 & 0x7].left; in edge()
316 left = edge8_tab_l[rs1 & 0x7].left; in edge()
322 left = edge16_tab[(rs1 >> 1) & 0x3].left; in edge()
328 left = edge16_tab_l[(rs1 >> 1) & 0x3].left; in edge()
334 left = edge32_tab[(rs1 >> 2) & 0x1].left; in edge()
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H A Dunaligned_32.c72 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
75 if(rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
139 unsigned int rs1 = (insn >> 14) & 0x1f; in compute_effective_address() local
144 maybe_flush_windows(rs1, 0, rd); in compute_effective_address()
145 return (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in compute_effective_address()
147 maybe_flush_windows(rs1, rs2, rd); in compute_effective_address()
148 return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address()
155 unsigned int rs1 = (insn >> 14) & 0x1f; in safe_compute_effective_address() local
160 maybe_flush_windows(rs1, 0, rd); in safe_compute_effective_address()
161 return (safe_fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in safe_compute_effective_address()
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H A Dunaligned_64.c104 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
107 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
173 unsigned int rs1 = (insn >> 14) & 0x1f; in compute_effective_address() local
178 maybe_flush_windows(rs1, 0, rd, from_kernel); in compute_effective_address()
179 addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in compute_effective_address()
181 maybe_flush_windows(rs1, rs2, rd, from_kernel); in compute_effective_address()
182 addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address()
/linux/arch/riscv/include/asm/
H A Dinsn-def.h32 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
33 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2
36 .macro insn_i, opcode, func3, rd, rs1, simm12
37 .insn i \opcode, \func3, \rd, \rs1, \simm12
40 .macro insn_s, opcode, func3, rs2, simm12, rs1
41 .insn s \opcode, \func3, \rs2, \simm12(\rs1)
48 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
53 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \
57 .macro insn_i, opcode, func3, rd, rs1, simm12
61 (.L__gpr_num_\rs1 << INSN_I_RS1_SHIF
84 __INSN_R(opcode,func3,func7,rd,rs1,rs2) global() argument
87 __INSN_I(opcode,func3,rd,rs1,simm12) global() argument
90 __INSN_S(opcode,func3,rs2,simm12,rs1) global() argument
139 __INSN_R(opcode,func3,func7,rd,rs1,rs2) global() argument
144 __INSN_I(opcode,func3,rd,rs1,simm12) global() argument
149 __INSN_S(opcode,func3,rs2,simm12,rs1) global() argument
158 INSN_R(opcode,func3,func7,rd,rs1,rs2) global() argument
162 INSN_I(opcode,func3,rd,rs1,simm12) global() argument
166 INSN_S(opcode,func3,rs2,simm12,rs1) global() argument
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/linux/arch/riscv/kernel/probes/
H A Dsimulate-insn.c184 u32 rs1 = RVC_EXTRACT_C2_RS1_REG(opcode); in simulate_c_jr_jalr() local
186 if (rs1 == 0) /* C.JR is only valid when rs1 != x0 */ in simulate_c_jr_jalr()
189 if (!rv_insn_reg_get_val(regs, rs1, &jump_addr)) in simulate_c_jr_jalr()
220 u32 rs1; in simulate_c_bnez_beqz() local
223 rs1 = 0x8 | ((opcode >> 7) & 0x7); in simulate_c_bnez_beqz()
225 if (!rv_insn_reg_get_val(regs, rs1, &rs1_val)) in simulate_c_bnez_beqz()
/linux/arch/parisc/net/
H A Dbpf_jit_comp32.c706 const s8 *rs1 = bpf_get_reg64(src1, tmp1, ctx); in emit_branch_r64() local
722 emit(hppa_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
723 emit(hppa_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
726 emit(hppa_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
727 emit(hppa_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
728 emit(hppa_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
731 emit(hppa_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
732 emit(hppa_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
733 emit(hppa_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
736 emit(hppa_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
[all …]
/linux/arch/arm/kernel/
H A Dsleep.S38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
44 ARM( orr \dst, \dst, \mask, lsr \rs1 ) @ dst|=(aff1>>rs1)
45 THUMB( lsr \mask, \mask, \rs1 )
/linux/lib/crypto/mips/
H A Dpoly1305-mips.pl224 my ($h0,$h1,$h2,$r0,$r1,$rs1,$d0,$d1,$d2) =
281 ld $rs1,40($ctx)
378 dmultu ($rs1,$d1) # h1*5*r1
381 mflo ($tmp0,$rs1,$d1)
382 mfhi ($tmp1,$rs1,$d1)
397 dmultu ($rs1,$d2) # h2*5*r1
400 mflo ($tmp2,$rs1,$d2)
729 my ($h0,$h1,$h2,$h3,$h4, $r0,$r1,$r2,$r3, $rs1,$rs2,$rs3) =
783 lw $rs1,36($ctx)
923 maddu $rs1,$d3 # d3*s1
[all …]
/linux/arch/sparc/math-emu/
H A Dmath_32.c284 argp rs1 = NULL, rs2 = NULL, rd = NULL; in do_one_mathemu() local
369 rs1 = (argp)&fregs[freg]; in do_one_mathemu()
371 case 7: FP_UNPACK_QP (QA, rs1); break; in do_one_mathemu()
372 case 6: FP_UNPACK_DP (DA, rs1); break; in do_one_mathemu()
373 case 5: FP_UNPACK_SP (SA, rs1); break; in do_one_mathemu()
H A Dmath_64.c359 argp rs1 = NULL, rs2 = NULL, rd = NULL; in do_mathemu() local
380 case 1: rs1 = (argp)&f->regs[freg]; in do_mathemu()
383 rs1 = (argp)&zero; in do_mathemu()
387 case 7: FP_UNPACK_QP (QA, rs1); break; in do_mathemu()
388 case 6: FP_UNPACK_DP (DA, rs1); break; in do_mathemu()
389 case 5: FP_UNPACK_SP (SA, rs1); break; in do_mathemu()
/linux/lib/crypto/riscv/
H A Dpoly1305-riscv.pl127 my ($h0,$h1,$h2,$r0,$r1,$rs1,$d0,$d1,$d2) =
160 ld $rs1,40($ctx)
203 mulhu $tmp1,$rs1,$d1 # h1*5*r1
204 mul $tmp0,$rs1,$d1
219 mul $tmp2,$rs1,$d2 # h2*5*r1
457 my ($h0,$h1,$h2,$h3,$h4, $r0,$r1,$r2,$r3, $rs1,$rs2,$rs3) =
505 lw $rs1,36($ctx)
580 MULX ($t4,$t3,$rs1,$d3) # d3*s1
610 mulw $a3,$rs1,$h4 # h4*s1
/linux/arch/arm64/kernel/
H A Dsleep.S39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
44 lsr \mask ,\mask, \rs1
/linux/Documentation/arch/riscv/
H A Dzicfilp.rst33 - rs1 = x1 or rs1 = x5, i.e. a return from a function and returns are
36 - rs1 = x7. On RISC-V, the compiler usually does the following to reach a
43 rely on memory. Thus rs1=x7 is exempted from tracking and
/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts80 arm,v2m-memory-map = "rs1";
/linux/arch/arm64/boot/dts/arm/
H A Dvexpress-v2f-1xv7-ca53x2.dts16 #include "arm/arm/vexpress-v2m-rs1.dtsi"
/linux/drivers/edac/
H A Dpnd2_edac.h224 u32 rs1 : 5; member
H A Dpnd2_edac.c980 daddr->rank |= dnv_get_bit(pmiaddr, dmap[pmiidx].rs1 + 13, 1); in dnv_pmi2mem()
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts12 #include "vexpress-v2m-rs1.dtsi"
H A Dvexpress-v2m.dtsi14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
H A Dvexpress-v2p-ca15-tc1.dts12 #include "vexpress-v2m-rs1.dtsi"
/linux/arch/riscv/
H A DKconfig.errata41 with rd=0, rs1=0 and imm=5. It will behave as a NOP