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Searched refs:riscv (Results 1 – 25 of 139) sorted by relevance

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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044-cpus.dtsi16 compatible = "thead,c920", "riscv";
25 mmu-type = "riscv,sv48";
27 riscv,isa = "rv64imafdcv";
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 riscv,cbom-block-size = <64>;
41 riscv,cbop-block-size = <64>;
42 riscv,cboz-block-size = <64>;
45 compatible = "riscv,cpu-intc";
52 compatible = "thead,c920", "riscv";
[all …]
H A Dcv180x-cpus.dtsi14 compatible = "thead,c906", "riscv";
23 mmu-type = "riscv,sv39";
24 riscv,isa = "rv64imafdc";
25 riscv,isa-base = "rv64i";
26 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
30 compatible = "riscv,cpu-intc";
/linux/drivers/gpu/drm/tegra/
H A Driscv.c32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
76 riscv_writel(riscv, RISCV_BCR_CTRL_CORE_SELECT_RISCV, RISCV_BCR_CTRL); in tegra_drm_riscv_boot_bootrom()
[all …]
H A Driscv.h26 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv);
27 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
/linux/arch/riscv/boot/dts/tenstorrent/
H A Dblackhole.dtsi16 compatible = "sifive,x280", "sifive,rocket0", "riscv";
19 mmu-type = "riscv,sv57";
20 riscv,isa-base = "rv64i";
21 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
25 compatible = "riscv,cpu-intc";
32 compatible = "sifive,x280", "sifive,rocket0", "riscv";
35 mmu-type = "riscv,sv57";
36 riscv,isa-base = "rv64i";
37 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
41 compatible = "riscv,cpu-intc";
[all …]
/linux/arch/riscv/
H A DMakefile61 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
62 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
63 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
64 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
65 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
75 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
79 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
82 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha
86 KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\…
88 KBUILD_AFLAGS += -march=$(riscv-march-y)
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/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi20 compatible = "andestech,ax45mp", "riscv";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
27 mmu-type = "riscv,sv39";
38 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
45 compatible = "andestech,ax45mp", "riscv";
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
52 mmu-type = "riscv,sv39";
64 "riscv,cpu-intc";
[all …]
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
H A Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux/arch/riscv/boot/dts/spacemit/
H A Dk1.dtsi53 compatible = "spacemit,x60", "riscv";
56 …riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_z…
57 riscv,isa-base = "rv64i";
58 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
63 riscv,cbom-block-size = <64>;
64 riscv,cbop-block-size = <64>;
65 riscv,cboz-block-size = <64>;
73 mmu-type = "riscv,sv39";
76 compatible = "riscv,cpu-intc";
83 compatible = "spacemit,x60", "riscv";
[all …]
/linux/arch/riscv/kernel/tests/
H A DKconfig.debug2 menu "arch/riscv/kernel Testing and Coverage"
8 bool "arch/riscv/kernel runtime Testing"
11 Enable riscv kernel runtime testing.
16 bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
20 Enable this option to test riscv module linking at boot. This will
34 tristate "KUnit test for riscv kprobes" if !KUNIT_ALL_TESTS
39 Enable testing for riscv kprobes. Useful for riscv and/or kprobes
47 endmenu # "arch/riscv/kernel runtime Testing"
/linux/tools/testing/selftests/riscv/
H A DREADME4 - These tests are riscv specific and so not built or run but just skipped
5 completely when env-variable ARCH is found to be different than 'riscv'.
10 $ make TARGETS=riscv kselftest-clean
11 $ make TARGETS=riscv kselftest
15 $ make -C tools/testing/selftests TARGETS=riscv \
18 or, alternatively, only specific riscv/ subtargets can be picked:
20 $ make -C tools/testing/selftests TARGETS=riscv RISCV_SUBTARGETS="mm vector" \
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi15 compatible = "thead,c906", "riscv";
25 mmu-type = "riscv,sv39";
27 riscv,isa = "rv64imafdc";
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
35 compatible = "riscv,cpu-intc";
74 riscv,ndev = <175>;
81 compatible = "riscv,pmu";
82 riscv,event-to-mhpmcounters =
93 riscv,event-to-mhpmevent =
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 compatible = "riscv,cpu-intc";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux/Documentation/arch/riscv/
H A Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
42 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
136 riscv,ndev = <511>;
/linux/arch/riscv/boot/dts/anlogic/
H A Ddr1v90.dtsi19 compatible = "nuclei,ux900", "riscv";
27 mmu-type = "riscv,sv39";
29 riscv,isa-base = "rv64i";
30 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
35 compatible = "riscv,cpu-intc";
77 riscv,ndev = <150>;
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi23 compatible = "thead,c910", "riscv";
25 riscv,isa = "rv64imafdc";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 mmu-type = "riscv,sv39";
43 compatible = "riscv,cpu-intc";
50 compatible = "thead,c910", "riscv";
52 riscv,isa = "rv64imafdc";
53 riscv,isa-base = "rv64i";
54 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
[all …]
/linux/lib/crc/
H A DMakefile19 crc-t10dif-$(CONFIG_RISCV) += riscv/crc16_msb.o
30 crc32-$(CONFIG_RISCV) += riscv/crc32_lsb.o riscv/crc32_msb.o
41 crc64-$(CONFIG_RISCV) += riscv/crc64_lsb.o riscv/crc64_msb.o
/linux/arch/riscv/purgatory/
H A DMakefile17 $(obj)/memcpy.o: $(srctree)/arch/riscv/lib/memcpy.S FORCE
20 $(obj)/memset.o: $(srctree)/arch/riscv/lib/memset.S FORCE
23 $(obj)/strcmp.o: $(srctree)/arch/riscv/lib/strcmp.S FORCE
26 $(obj)/strlen.o: $(srctree)/arch/riscv/lib/strlen.S FORCE
29 $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE
/linux/arch/riscv/kernel/
H A DMakefile.syscalls3 syscall_abis_32 += riscv memfd_secret
4 syscall_abis_64 += riscv rlimit memfd_secret
H A Dvmlinux.lds.S25 OUTPUT_ARCH(riscv)
174 .riscv.attributes 0 : { *(.riscv.attributes) }
/linux/drivers/firmware/efi/
H A DMakefile39 riscv-obj-$(CONFIG_EFI) := efi-init.o riscv-runtime.o
40 obj-$(CONFIG_RISCV) += $(riscv-obj-y)
/linux/lib/crypto/
H A DMakefile75 libchacha-$(CONFIG_RISCV) += riscv/chacha-riscv64-zvkb.o
171 libpoly1305-y += riscv/poly1305-core.o
177 $(obj)/riscv/poly1305-core.S: $(src)/riscv/poly1305-riscv.pl FORCE
179 targets += riscv/poly1305-core.S
195 riscv/poly1305-core.S \
252 libsha256-$(CONFIG_RISCV) += riscv/sha256-riscv64-zvknha_or_zvknhb-zvkb.o
281 libsha512-$(CONFIG_RISCV) += riscv/sha512-riscv64-zvknhb-zvkb.o
/linux/Documentation/translations/zh_CN/arch/riscv/
H A Dpatch-acceptance.rst5 :Original: Documentation/arch/riscv/patch-acceptance.rst
13 arch/riscv 开发者维护指南

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