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Searched refs:riscv (Results 1 – 25 of 124) sorted by relevance

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/linux/drivers/gpu/drm/tegra/
H A Driscv.c32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
76 riscv_writel(riscv, RISCV_BCR_CTRL_CORE_SELECT_RISCV, RISCV_BCR_CTRL); in tegra_drm_riscv_boot_bootrom()
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H A Dnvdec.c51 struct tegra_drm_riscv riscv; member
118 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1, in nvdec_boot_riscv()
119 &nvdec->riscv.bl_desc); in nvdec_boot_riscv()
135 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1, in nvdec_boot_riscv()
136 &nvdec->riscv.os_desc); in nvdec_boot_riscv()
498 nvdec->riscv.dev = dev; in nvdec_probe()
499 nvdec->riscv.regs = nvdec->regs; in nvdec_probe()
501 err = tegra_drm_riscv_read_descriptors(&nvdec->riscv); in nvdec_probe()
H A Driscv.h26 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv);
27 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
/linux/arch/riscv/boot/dts/tenstorrent/
H A Dblackhole.dtsi16 compatible = "sifive,x280", "sifive,rocket0", "riscv";
19 mmu-type = "riscv,sv57";
20 riscv,isa-base = "rv64i";
21 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
25 compatible = "riscv,cpu-intc";
32 compatible = "sifive,x280", "sifive,rocket0", "riscv";
35 mmu-type = "riscv,sv57";
36 riscv,isa-base = "rv64i";
37 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
41 compatible = "riscv,cpu-intc";
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/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi20 compatible = "andestech,ax45mp", "riscv";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
27 mmu-type = "riscv,sv39";
38 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
45 compatible = "andestech,ax45mp", "riscv";
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
52 mmu-type = "riscv,sv39";
64 "riscv,cpu-intc";
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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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H A Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 compatible = "riscv,cpu-intc";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux/arch/riscv/kernel/tests/
H A DKconfig.debug2 menu "arch/riscv/kernel Testing and Coverage"
8 bool "arch/riscv/kernel runtime Testing"
11 Enable riscv kernel runtime testing.
16 bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
20 Enable this option to test riscv module linking at boot. This will
34 tristate "KUnit test for riscv kprobes" if !KUNIT_ALL_TESTS
39 Enable testing for riscv kprobes. Useful for riscv and/or kprobes
47 endmenu # "arch/riscv/kernel runtime Testing"
/linux/tools/testing/selftests/riscv/
H A DREADME4 - These tests are riscv specific and so not built or run but just skipped
5 completely when env-variable ARCH is found to be different than 'riscv'.
10 $ make TARGETS=riscv kselftest-clean
11 $ make TARGETS=riscv kselftest
15 $ make -C tools/testing/selftests TARGETS=riscv \
18 or, alternatively, only specific riscv/ subtargets can be picked:
20 $ make -C tools/testing/selftests TARGETS=riscv RISCV_SUBTARGETS="mm vector" \
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x-cpus.dtsi14 compatible = "thead,c906", "riscv";
23 mmu-type = "riscv,sv39";
24 riscv,isa = "rv64imafdc";
25 riscv,isa-base = "rv64i";
26 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
30 compatible = "riscv,cpu-intc";
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi23 compatible = "thead,c910", "riscv";
25 riscv,isa = "rv64imafdc";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 mmu-type = "riscv,sv39";
43 compatible = "riscv,cpu-intc";
50 compatible = "thead,c910", "riscv";
52 riscv,isa = "rv64imafdc";
53 riscv,isa-base = "rv64i";
54 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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/linux/Documentation/arch/riscv/
H A Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/linux/lib/crc/
H A DMakefile19 crc-t10dif-$(CONFIG_RISCV) += riscv/crc16_msb.o
30 crc32-$(CONFIG_RISCV) += riscv/crc32_lsb.o riscv/crc32_msb.o
41 crc64-$(CONFIG_RISCV) += riscv/crc64_lsb.o riscv/crc64_msb.o
/linux/arch/riscv/purgatory/
H A DMakefile17 $(obj)/memcpy.o: $(srctree)/arch/riscv/lib/memcpy.S FORCE
20 $(obj)/memset.o: $(srctree)/arch/riscv/lib/memset.S FORCE
23 $(obj)/strcmp.o: $(srctree)/arch/riscv/lib/strcmp.S FORCE
26 $(obj)/strlen.o: $(srctree)/arch/riscv/lib/strlen.S FORCE
29 $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE
/linux/lib/crypto/
H A DMakefile53 libaes-$(CONFIG_RISCV) += riscv/aes-riscv64-zvkned.o
117 libchacha-$(CONFIG_RISCV) += riscv/chacha-riscv64-zvkb.o
229 libpoly1305-y += riscv/poly1305-core.o
235 $(obj)/riscv/poly1305-core.S: $(src)/riscv/poly1305-riscv.pl FORCE
237 targets += riscv/poly1305-core.S
253 riscv/poly1305-core.S \
310 libsha256-$(CONFIG_RISCV) += riscv/sha256-riscv64-zvknha_or_zvknhb-zvkb.o
339 libsha512-$(CONFIG_RISCV) += riscv/sha512-riscv64-zvknhb-zvkb.o
/linux/arch/riscv/kernel/
H A DMakefile.syscalls3 syscall_abis_32 += riscv memfd_secret
4 syscall_abis_64 += riscv rlimit memfd_secret
H A Dvmlinux.lds.S25 OUTPUT_ARCH(riscv)
175 .riscv.attributes 0 : { *(.riscv.attributes) }
/linux/drivers/firmware/efi/
H A DMakefile39 riscv-obj-$(CONFIG_EFI) := efi-init.o riscv-runtime.o
40 obj-$(CONFIG_RISCV) += $(riscv-obj-y)
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi31 compatible = "canaan,k210", "riscv";
33 riscv,isa = "rv64imafdc";
34 mmu-type = "riscv,none";
42 compatible = "riscv,cpu-intc";
47 compatible = "canaan,k210", "riscv";
49 riscv,isa = "rv64imafdc";
50 mmu-type = "riscv,none";
58 compatible = "riscv,cpu-intc";
125 riscv,ndev = <65>;
/linux/Documentation/translations/zh_CN/arch/riscv/
H A Dpatch-acceptance.rst5 :Original: Documentation/arch/riscv/patch-acceptance.rst
13 arch/riscv 开发者维护指南
/linux/Documentation/features/sched/membarrier-sync-core/
H A Darch-support.txt13 # * riscv
15 # riscv uses xRET as return from interrupt and to return to user-space.
62 | riscv: | ok |
/linux/scripts/
H A Dxz_wrap.sh99 riscv)
108 BCJ=--riscv
H A Dsubarch.include13 -e s/riscv.*/riscv/ -e s/loongarch.*/loongarch/)
/linux/tools/scripts/
H A DMakefile.arch8 -e s/riscv.*/riscv/ -e s/loongarch.*/loongarch/)

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