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Searched refs:readl (Results 1 – 25 of 1667) sorted by relevance

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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dmmc_core.c237 u32 value = readl(mmcaddr + MMC_CNTRL); in dwmac_mmc_ctrl()
262 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB); in dwmac_mmc_read()
263 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB); in dwmac_mmc_read()
264 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr + in dwmac_mmc_read()
266 mmc->mmc_tx_multicastframe_g += readl(mmcaddr + in dwmac_mmc_read()
268 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB); in dwmac_mmc_read()
270 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB); in dwmac_mmc_read()
272 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB); in dwmac_mmc_read()
274 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB); in dwmac_mmc_read()
276 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB); in dwmac_mmc_read()
[all …]
H A Ddwmac4_dma.c20 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
81 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan)); in dwmac4_dma_init_rx_chan()
102 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); in dwmac4_dma_init_tx_chan()
126 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); in dwmac4_dma_init_channel()
144 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); in dwmac410_dma_init_channel()
158 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_init()
176 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_init()
201 readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel)); in _dwmac4_dump_dma_regs()
203 readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel)); in _dwmac4_dump_dma_regs()
205 readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel)); in _dwmac4_dump_dma_regs()
[all …]
H A Ddwxgmac2_dma.c13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
40 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
57 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
74 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
86 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi()
143 reg_space[i] = readl(ioaddr + i * 4); in dwxgmac2_dma_dump_regs()
149 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode()
170 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); in dwxgmac2_dma_rx_mode()
208 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
[all …]
H A Ddwxgmac2_core.c22 tx = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_core_init()
23 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_core_init()
53 u32 tx = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_set_mac()
54 u32 rx = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_set_mac()
73 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
80 return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC); in dwxgmac2_rx_ipc()
89 value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue); in dwxgmac2_rx_queue_enable()
105 ctrl2 = readl(ioaddr + XGMAC_RXQ_CTRL2); in dwxgmac2_rx_queue_prio()
106 ctrl3 = readl(ioaddr + XGMAC_RXQ_CTRL3); in dwxgmac2_rx_queue_prio()
148 value = readl(ioaddr + reg); in dwxgmac2_tx_queue_prio()
[all …]
/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-hw-s5p.c22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
59 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_proc_mode()
74 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode()
82 return readl(regs + S5P_JPGMOD) & S5P_SUBSAMPLING_MODE_MASK; in s5p_jpeg_get_subsampling_mode()
89 reg = readl(regs + S5P_JPGDRI_U); in s5p_jpeg_dri()
94 reg = readl(regs + S5P_JPGDRI_L); in s5p_jpeg_dri()
104 reg = readl(regs + S5P_JPG_QTBL); in s5p_jpeg_qtbl()
114 reg = readl(regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_ac()
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-fhctl.c59 readl(regs->reg_hp_en), readl(regs->reg_clk_con), in dump_hw()
60 readl(regs->reg_slope0), readl(regs->reg_slope1)); in dump_hw()
62 readl(regs->reg_cfg), readl(regs->reg_updnlmt), in dump_hw()
63 readl(regs->reg_dds), readl(regs->reg_dvfs), in dump_hw()
64 readl(regs->reg_mon)); in dump_hw()
65 pr_info("pcw<%x>\n", readl(pll->pcw_addr)); in dump_hw()
73 writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
74 writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
75 writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
79 r = readl(regs->reg_cfg); in fhctl_set_ssc_regs()
[all …]
/linux/sound/arm/
H A Dpxa2xx-ac97-lib.c68 val = (readl(reg_addr) & 0xffff); in pxa2xx_ac97_read()
71 if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1) <= 0 && in pxa2xx_ac97_read()
72 !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE)) { in pxa2xx_ac97_read()
74 __func__, reg, readl(ac97_reg_base + GSR) | gsr_bits); in pxa2xx_ac97_read()
82 val = (readl(reg_addr) & 0xffff); in pxa2xx_ac97_read()
84 wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1); in pxa2xx_ac97_read()
110 if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE, 1) <= 0 && in pxa2xx_ac97_write()
111 !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE)) { in pxa2xx_ac97_write()
113 __func__, reg, readl(ac97_reg_base + GSR) | gsr_bits); in pxa2xx_ac97_write()
127 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa25x()
[all …]
/linux/drivers/scsi/bfa/
H A Dbfa_ioc_ct.c60 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
67 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
74 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_ct_firmware_lock()
87 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
98 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
113 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
120 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock()
134 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
135 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
138 readl(ioc->ioc_regs.err_set); in bfa_ioc_ct_notify_fail()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
54 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_get_lpi_status()
74 irq_status = readl(ioaddr + SXGBE_CORE_INT_STATUS_REG); in sxgbe_core_host_irq_status()
106 high_word = readl(ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n)); in sxgbe_core_get_umac_addr()
107 low_word = readl(ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n)); in sxgbe_core_get_umac_addr()
122 tx_config = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_enable_tx()
134 rx_config = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx()
144 return readl(ioaddr + SXGBE_CORE_VERSION_REG); in sxgbe_get_controller_version()
151 return readl(ioaddr + (SXGBE_CORE_HW_FEA_REG(feature_index))); in sxgbe_get_hw_feature()
[all …]
H A Dsxgbe_mtl.c25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
68 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_txfifosize()
80 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_rxfifosize()
89 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_enable_txqueue()
98 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_disable_txqueue()
108 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_active()
119 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_enable()
129 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_deactive()
140 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fep_enable()
150 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fep_disable()
[all …]
/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_ioc_ct.c125 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
137 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_ct_firmware_lock()
178 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
194 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
195 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
377 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
389 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
400 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
427 r32 = readl(ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat()
450 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
[all …]
/linux/sound/soc/pxa/
H A Dpxa2xx-i2s.c115 readl(i2s_reg_base + SADR); in pxa_i2s_wait()
177 writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
179 writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
180 writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1); in pxa2xx_i2s_hw_params()
183 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR); in pxa2xx_i2s_hw_params()
185 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR); in pxa2xx_i2s_hw_params()
222 writel(readl(i2s_reg_base + SACR1) & (~SACR1_DRPL), i2s_reg_base + SACR1); in pxa2xx_i2s_trigger()
224 writel(readl(i2s_reg_base + SACR1) & (~SACR1_DREC), i2s_reg_base + SACR1); in pxa2xx_i2s_trigger()
225 writel(readl(i2s_reg_base + SACR0) | (SACR0_ENB), i2s_reg_base + SACR0); in pxa2xx_i2s_trigger()
244 writel(readl(i2s_reg_base + SACR1) | (SACR1_DRPL), i2s_reg_base + SACR1); in pxa2xx_i2s_shutdown()
[all …]
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_mac.c26 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
32 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
42 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
48 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
72 ret = read_poll_timeout(readl, reg, reg & MAC_W_MAC_DONE, 1, 200, true, in spl2sw_mac_addr_add()
80 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0), in spl2sw_mac_addr_add()
82 readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)), in spl2sw_mac_addr_add()
84 readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0))); in spl2sw_mac_addr_add()
108 ret = read_poll_timeout(readl, reg, reg & MAC_W_MAC_DONE, 1, 200, true, in spl2sw_mac_addr_del()
116 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0), in spl2sw_mac_addr_del()
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
199 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); in analogix_dp_mute_hpd_interrupt()
203 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); in analogix_dp_mute_hpd_interrupt()
240 reg = readl(dp->reg_base + pd_addr); in analogix_dp_set_pll_power_down()
266 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
275 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
285 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
295 reg = readl(dp->reg_base + phy_pd_addr); in analogix_dp_set_analog_power_down()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-pxa.c357 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_show_state()
372 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)), in i2c_pxa_scream_blue_murder()
373 readl(_ISR(i2c))); in i2c_pxa_scream_blue_murder()
395 return !(readl(_ICR(i2c)) & ICR_SCLE); in i2c_pxa_is_slavemode()
407 while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) { in i2c_pxa_abort()
408 unsigned long icr = readl(_ICR(i2c)); in i2c_pxa_abort()
421 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), in i2c_pxa_abort()
431 isr = readl(_ISR(i2c)); in i2c_pxa_wait_bus_not_busy()
457 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_wait_master()
459 if (readl(_ISR(i2c)) & ISR_SAD) { in i2c_pxa_wait_master()
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-lite-reg.c25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq()
49 u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_get_interrupt_source()
56 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); in flite_hw_clear_last_capture_end()
77 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_interrupt_mask()
85 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_start()
92 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_stop()
103 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_test_pattern()
144 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_source_format()
[all …]
/linux/drivers/ata/
H A Dsata_sx4.c468 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_dma_prep()
502 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_nodata_prep()
535 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in __pdc20621_push_hdma()
538 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */ in __pdc20621_push_hdma()
588 readl(dimm_mmio), readl(dimm_mmio + 4), in pdc20621_dump_hdma()
589 readl(dimm_mmio + 8), readl(dimm_mmio + 12)); in pdc20621_dump_hdma()
621 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in pdc20621_packet_start()
625 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); in pdc20621_packet_start()
672 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
683 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
[all …]
/linux/drivers/usb/early/
H A Dehci-dbgp.c82 dbgp_printk(" Debug control: %08x", readl(&ehci_debug->control)); in dbgp_ehci_status()
83 dbgp_printk(" ehci cmd : %08x", readl(&ehci_regs->command)); in dbgp_ehci_status()
85 readl(&ehci_regs->configured_flag)); in dbgp_ehci_status()
86 dbgp_printk(" ehci status : %08x", readl(&ehci_regs->status)); in dbgp_ehci_status()
88 readl(&ehci_regs->port_status[dbgp_phys_port - 1])); in dbgp_ehci_status()
203 pids = readl(&ehci_debug->pids); in dbgp_wait_until_done()
257 lo = readl(&ehci_debug->data03); in dbgp_get_data()
258 hi = readl(&ehci_debug->data47); in dbgp_get_data()
277 pids = readl(&ehci_debug->pids); in dbgp_bulk_write()
280 ctrl = readl(&ehci_debug->control); in dbgp_bulk_write()
[all …]
/linux/sound/soc/sunxi/
H A Dsun8i-adda-pr-regmap.c35 writel(readl(base) | ADDA_PR_RESET, base); in adda_reg_read()
38 writel(readl(base) & ~ADDA_PR_WRITE, base); in adda_reg_read()
41 tmp = readl(base); in adda_reg_read()
47 *val = readl(base) & ADDA_PR_DATA_OUT_MASK; in adda_reg_read()
58 writel(readl(base) | ADDA_PR_RESET, base); in adda_reg_write()
61 tmp = readl(base); in adda_reg_write()
67 tmp = readl(base); in adda_reg_write()
73 writel(readl(base) | ADDA_PR_WRITE, base); in adda_reg_write()
76 writel(readl(base) & ~ADDA_PR_WRITE, base); in adda_reg_write()
/linux/drivers/rtc/
H A Drtc-ftrtc010.c71 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_read_time()
72 min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE); in ftrtc010_rtc_read_time()
73 hour = readl(rtc->rtc_base + FTRTC010_RTC_HOUR); in ftrtc010_rtc_read_time()
74 days = readl(rtc->rtc_base + FTRTC010_RTC_DAYS); in ftrtc010_rtc_read_time()
75 offset = readl(rtc->rtc_base + FTRTC010_RTC_RECORD); in ftrtc010_rtc_read_time()
92 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_set_time()
93 min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE); in ftrtc010_rtc_set_time()
94 hour = readl(rtc->rtc_base + FTRTC010_RTC_HOUR); in ftrtc010_rtc_set_time()
95 day = readl(rtc->rtc_base + FTRTC010_RTC_DAYS); in ftrtc010_rtc_set_time()
171 sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND); in ftrtc010_rtc_probe()
[all …]
/linux/drivers/cache/
H A Dsifive_ccache.c109 cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); in ccache_config_read()
116 cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); in ccache_config_read()
173 return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; in ccache_largest_wayenabled()
209 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); in ccache_int_handler()
210 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); in ccache_int_handler()
213 readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); in ccache_int_handler()
219 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); in ccache_int_handler()
220 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); in ccache_int_handler()
222 readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); in ccache_int_handler()
229 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); in ccache_int_handler()
[all …]
/linux/sound/soc/ux500/
H A Dux500_msp_i2s.c203 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
222 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
261 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
291 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
312 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
331 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
363 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in enable_msp()
373 reg_val_GCR = readl(msp->registers + MSP_GCR); in enable_msp()
384 reg_val_GCR = readl(msp->registers + MSP_GCR); in flush_fifo_rx()
[all …]
/linux/sound/soc/amd/acp/
H A Damd.h265 high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH(adata)); in acp_get_byte_count()
266 low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW(adata)); in acp_get_byte_count()
269 high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH(adata)); in acp_get_byte_count()
270 low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW(adata)); in acp_get_byte_count()
273 high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH); in acp_get_byte_count()
274 low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW); in acp_get_byte_count()
283 high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH(adata)); in acp_get_byte_count()
284 low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW(adata)); in acp_get_byte_count()
287 high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH(adata)); in acp_get_byte_count()
288 low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW(adata)); in acp_get_byte_count()
[all …]
/linux/arch/arm/mach-dove/
H A Dmpp.c60 readl(DOVE_MPP_CTRL4_VIRT_BASE)); in dove_mpp_dump_regs()
63 readl(DOVE_PMU_MPP_GENERAL_CTRL)); in dove_mpp_dump_regs()
65 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); in dove_mpp_dump_regs()
70 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_nfc()
81 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_cfg_au1()
82 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); in dove_mpp_cfg_au1()
83 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_au1()
84 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); in dove_mpp_cfg_au1()
121 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_conf_grp()
/linux/drivers/clk/mvebu/
H A Dorion.c30 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & in mv88f5181_get_tclk_freq()
47 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_cpu_freq()
62 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_clk_ratio()
100 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & in mv88f5182_get_tclk_freq()
115 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_cpu_freq()
130 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_clk_ratio()
174 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & in mv88f5281_get_cpu_freq()
187 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & in mv88f5281_get_clk_ratio()
225 u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) & in mv88f6183_get_tclk_freq()
240 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & in mv88f6183_get_cpu_freq()
[all …]

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