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/linux/Documentation/arch/powerpc/
H A Dqe_firmware.rst44 In this document, the term 'microcode' refers to the sequence of 32-bit
45 integers that compose the actual QE microcode.
47 The term 'firmware' refers to a binary blob that contains the microcode as
50 1) describes the microcode's purpose
51 2) describes how and where to upload the microcode
60 The QE architecture allows for only one microcode present in I-RAM for each
61 RISC processor. To replace any current microcode, a full QE reset (which
62 disables the microcode) must be performed first.
64 QE microcode is uploaded using the following procedure:
66 1) The microcode is placed into I-RAM at a specific location, using the
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H A Dimc.rst21 The Nest PMU counters are handled by a Nest IMC microcode which runs in the OCC
22 (On-Chip Controller) complex. The microcode collects the counter data and moves
/linux/Documentation/arch/x86/
H A Dmicrocode.rst11 The kernel has a x86 microcode loading facility which is supposed to
12 provide microcode loading methods in the OS. Potential use cases are
13 updating the microcode on platforms beyond the OEM End-Of-Life support,
14 and updating the microcode on long-running systems without rebooting.
18 Early load microcode
21 The kernel can update microcode very early during boot. Loading
22 microcode early can fix CPU issues before they are observed during
25 The microcode is stored in an initrd file. During boot, it is read from
28 The format of the combined initrd image is microcode in (uncompressed)
32 The microcode files in cpio name space are:
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H A Dmds.rst77 instruction in combination with a microcode update. The microcode clears
87 executed on a CPU without the microcode update there is no side effect
105 the microcode updated, but the hypervisor does not (yet) expose the
127 scenarios where the host has the updated microcode but the
207 functionality in microcode. Aside of that the IO-Port mechanism is a
209 not affected or do not receive microcode updates anymore.
H A Dindex.rst35 microcode
H A Dtsx_async_abort.rst26 microcode update which can be used to disable TSX. In addition, it
48 scenarios where the host has the updated microcode but the
/linux/arch/x86/kernel/cpu/microcode/
H A DMakefile2 microcode-y := core.o
3 obj-$(CONFIG_MICROCODE) += microcode.o
4 microcode-$(CONFIG_CPU_SUP_INTEL) += intel.o
5 microcode-$(CONFIG_CPU_SUP_AMD) += amd.o
H A Dcore.c584 int old_rev = boot_cpu_data.microcode; in load_late_stop_cpus()
659 pr_info("revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode); in load_late_stop_cpus()
847 cpu_data(cpu).microcode = uci->cpu_sig.rev; in mc_cpu_online()
849 boot_cpu_data.microcode = uci->cpu_sig.rev; in mc_cpu_online()
H A Damd.c5 * This driver allows to upgrade microcode on F10h AMD
22 #define pr_fmt(fmt) "microcode: " fmt
35 #include <asm/microcode.h>
123 * This points to the current valid container of microcode patches which we will
125 * microcode patch we found to match.
136 * format. See Documentation/arch/x86/microcode.rst
139 ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin";
147 * already contains the f/m/s for which the microcode is destined
366 * Check whether there is a valid microcode container file at the beginning
374 ucode_dbg("Truncated microcode containe in verify_container()
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/linux/Documentation/admin-guide/hw-vuln/
H A Dgather_data_sampling.rst48 This issue is mitigated in microcode. The microcode defines the following new
62 GDS can also be mitigated on systems that don't have updated microcode by
76 use the microcode mitigation when available or disable AVX on affected systems
77 where the microcode hasn't been updated to include the mitigation.
91 Vulnerable: No microcode Processor vulnerable and microcode is missing
94 no microcode Processor is vulnerable and microcode is missing
108 The updated microcode will enable the mitigation by default. The kernel's
H A Dtsx_async_abort.rst99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
100 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
101 - The processor is vulnerable but microcode is not updated. The
104 If the processor is vulnerable but the availability of the microcode
110 microcode update applied, but the hypervisor is not yet updated to
111 expose the CPUID to the guest. If the host has updated microcode the
115 - The microcode has been updated to clear the buffers. TSX is still enabled.
124 The kernel detects the affected CPUs and the presence of the microcode which is
125 required. If a CPU is affected and the microcode is available, then the kernel
135 Affected systems where the host has TAA microcode and TAA is mitigated by
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H A Dspecial-register-buffer-data-sampling.rst64 Intel will release microcode updates that modify the RDRAND, RDSEED, and
86 The microcode updates provide an opt-out mechanism (RNGDS_MITG_DIS) to disable
100 9]==1. This MSR is introduced through the microcode update.
132 Vulnerable: No microcode Processor vulnerable and microcode is missing
147 This new microcode serializes processor access during execution of RDRAND,
H A Dprocessor_mmio_stale_data.rst14 vulnerabilities includes a combination of microcode update and software
115 Newer processors and microcode update on existing affected processors added new
157 combination with a microcode update. The microcode clears the affected CPU
225 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
226 - The processor is vulnerable but microcode is not updated. The
229 If the processor is vulnerable but the availability of the microcode
235 microcode update applied, but the hypervisor is not yet updated to
236 expose the CPUID to the guest. If the host has updated microcode the
H A Dindirect-target-selection.rst22 executed prior to the IBPB. This is fixed by the IPU 2025.1 microcode, which
23 should be available via distro updates. Alternatively microcode can be
48 - IBPB isolation is affected on all ITS affected CPUs, and need a microcode
143 Note, microcode mitigation status is not reported in this file.
/linux/drivers/net/wireless/intel/iwlegacy/
H A DKconfig22 In order to use this driver, you will need a microcode (uCode)
23 image for it. You can obtain the microcode from:
27 The microcode is typically installed in /lib/firmware. You can
49 In order to use this driver, you will need a microcode (uCode)
50 image for it. You can obtain the microcode from:
54 The microcode is typically installed in /lib/firmware. You can
/linux/drivers/crypto/cavium/cpt/
H A Dcptpf.h22 struct microcode { struct
53 struct microcode mcode[CPT_MAX_CORE_GROUPS]; argument
H A Dcptpf_mbox.c61 struct microcode *mcode = cpt->mcode; in cpt_bind_vq_to_grp()
/linux/arch/x86/kernel/cpu/
H A Dintel.c104 u32 microcode; member
144 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
207 c->microcode = intel_get_microcode_revision(); in early_init_intel()
234 c->microcode < 0x20e) { in early_init_intel()
H A DMakefile54 obj-$(CONFIG_MICROCODE) += microcode/
H A Damd.c414 pr_debug("%s: current revision: 0x%x\n", __func__, c->microcode); in tsa_init()
620 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); in early_init_amd()
969 if (boot_cpu_data.microcode < good_rev) in cpu_has_zenbleed_microcode()
H A Dhygon.c131 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); in early_init_hygon()
/linux/drivers/soc/fsl/qe/
H A Dqe.c484 calc_size = struct_size(firmware, microcode, firmware->count); in qe_upload_firmware()
493 be32_to_cpu(firmware->microcode[i].count); in qe_upload_firmware()
535 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware()
/linux/Documentation/
H A DChanges296 Intel IA32 microcode
299 A driver has been added to allow updating of Intel IA32 microcode,
304 mknod /dev/cpu/microcode c 10 184
305 chmod 0644 /dev/cpu/microcode
511 Intel P6 microcode
/linux/Documentation/networking/devlink/
H A Dsfc.rst41 - Datapath software/microcode/firmware version.
/linux/drivers/scsi/
H A Dwd33c93.h217 uchar microcode; /* microcode rev */ member

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