Searched refs:mailboxes (Results 1 – 12 of 12) sorted by relevance
121 struct tegra_hsp_mailbox *mailboxes; member234 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; in tegra_hsp_shared_irq()260 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; in tegra_hsp_shared_irq()632 mb = &hsp->mailboxes[index]; in tegra_hsp_sm_xlate()672 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes), in tegra_hsp_add_mailboxes()674 if (!hsp->mailboxes) in tegra_hsp_add_mailboxes()678 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; in tegra_hsp_add_mailboxes()889 if (hsp->mailboxes) { in tegra_hsp_resume()891 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; in tegra_hsp_resume()
7 signals. Say Y if your platform supports hardware mailboxes.24 which provides unidirectional mailboxes between processing elements.33 which provides unidirectional mailboxes between processing elements.
23 messaging mailboxes in case of multi-packet message (up to 4KB) and24 up to 64 mailboxes if single-packet messages (up to 256 B) are used. In addition26 have reduced number of messaging mailboxes. RapidIO aware applications must95 mailboxes.
39 resources such as mailboxes and doorbells. The rio_mport also includes a unique
27 users of these mailboxes for IPC, one for each mailbox. This shared
8 tristate "Apple SoC mailboxes"
40 resources, and manage mailboxes/doorbells.
137 mailboxes_ick: clock-mailboxes-ick@7 {
440 mailboxes) and only first 22 bytes (for 64-bit mailboxes). This is to
214 mailboxes are basically a fixed length array that serves as the call-stack.216 Firmware mailboxes can be located by searching the encoder and decoder memory226 The firmware implements 20 mailboxes of 20 32-bit words. The first 10 are272 mailboxes for pending commands, processes them, sets the result code, populates
194 device HW queue (FIFO, mailboxes or whatever the implementation is)