| /linux/tools/perf/tests/shell/ |
| H A D | stat_bpf_counters.sh | 44 …base_instructions=$(perf stat --no-big-num -e instructions -- $workload 2>&1 | awk '/instructions/…
45 …bpf_instructions=$(perf stat --no-big-num --bpf-counters -e instructions -- $workload 2>&1 | awk …
54 …stat_output=$(perf stat --no-big-num -e instructions/name=base_instructions/,instructions/name=bpf…
63 if ! perf stat -e instructions --bpf-counters true > /dev/null 2>&1; then
66 perf --no-pager stat -e instructions --bpf-counters true || true
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| /linux/Documentation/arch/arm64/ |
| H A D | legacy_instructions.rst | 2 Legacy instructions
6 emulation of instructions which have been deprecated, or obsoleted in
18 Generates undefined instruction abort. Default for instructions that
27 instructions, .e.g., CP15 barriers
34 instructions. Using hardware execution generally provides better
36 about the use of the deprecated instructions.
39 architecture. Deprecated instructions should default to emulation
40 while obsolete instructions must be undefined by default.
45 Supported legacy instructions
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| H A D | pointer-authentication.rst | 25 The extension adds instructions to insert a valid PAC into a pointer,
30 A subset of these instructions have been allocated from the HINT
32 these instructions behave as NOPs. Applications and libraries using
33 these instructions operate correctly regardless of the presence of the
57 with HINT space pointer authentication instructions protecting
107 register. Any attempt to use the Pointer Authentication instructions will
128 instructions to sign and authenticate function pointers and other pointers
135 but before executing any PAC instructions.
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| /linux/Documentation/bpf/standardization/ |
| H A D | instruction-set.rst | 33 mnemonic functions when describing the semantics of instructions.
120 An implementation does not need to support all instructions specified in this
121 document (e.g., deprecated instructions). Instead, a number of conformance
124 conformance group means it MUST support all instructions in that conformance
128 that executes instructions, and tools such as compilers that generate
129 instructions for the runtime. Thus, capability discovery in terms of
133 corresponds to a set of instructions that are mandatory. That is, each
138 * base32: includes all instructions defined in this
140 * base64: includes base32, plus instructions explicitly noted
142 * atomic32: includes 32-bit atomic operation instructions (see `Atomic operations`_).
[all …]
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| /linux/drivers/watchdog/ |
| H A D | wdat_wdt.c | 47 struct list_head *instructions[MAX_WDAT_ACTIONS]; member
119 if (action >= ARRAY_SIZE(wdat->instructions)) in wdat_wdt_run_action()
122 if (!wdat->instructions[action]) in wdat_wdt_run_action()
128 list_for_each_entry(instr, wdat->instructions[action], node) { in wdat_wdt_run_action()
389 struct list_head *instructions; in wdat_wdt_probe() local
439 instructions = wdat->instructions[action]; in wdat_wdt_probe()
440 if (!instructions) { in wdat_wdt_probe()
441 instructions = devm_kzalloc(dev, in wdat_wdt_probe()
442 sizeof(*instructions), in wdat_wdt_probe()
444 if (!instructions) { in wdat_wdt_probe()
[all …]
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| /linux/Documentation/bpf/ |
| H A D | linux-notes.rst | 10 Byte swap instructions
15 Jump instructions
45 Legacy BPF Packet access instructions
49 <instruction-set.html#legacy-bpf-packet-access-instructions>`_,
50 Linux has special eBPF instructions for access to packet data that have been
54 The instructions come in two forms: ``BPF_ABS | <size> | BPF_LD`` and
57 These instructions are used to access packet data and can only be used when
63 These instructions have seven implicit operands:
72 These instructions have an implicit program exit condition as well. If an
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| H A D | bpf_design_QA.rst | 93 It's the maximum number of instructions that the unprivileged bpf
95 Like the maximum number of instructions that can be explored during
98 of 1 million NOP instructions. There is a limit to the maximum number
119 Q: LD_ABS and LD_IND instructions vs C code
129 Q: BPF instructions mapping not one-to-one to native CPU
131 Q: It seems not all BPF instructions are one-to-one to native CPU.
149 of LD_ABS insn). Those instructions need to invoke epilogue and
152 Q: Why BPF_JLT and BPF_JLE instructions were not introduced in the beginning?
156 due to lack of these compare instructions and they were added.
157 These two instructions is a perfect example what kind of new BPF
[all …]
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| H A D | clang-notes.rst | 17 Arithmetic instructions
23 Jump instructions
32 Clang can generate atomic instructions by default when ``-mcpu=v3`` is
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| /linux/Documentation/arch/x86/x86_64/ |
| H A D | fsgs.rst | 69 Accessing FS/GS base with the FSGSBASE instructions
73 instructions to access the FS and GS base registers directly from user
74 space. These instructions are also supported on AMD Family 17H CPUs. The
75 following instructions are available:
84 The instructions avoid the overhead of the arch_prctl() syscall and allow
90 FSGSBASE instructions enablement
92 The instructions are enumerated in CPUID leaf 7, bit 0 of EBX. If
95 The availability of the instructions does not enable them
103 instructions will fault with a #UD exception.
107 kernel has FSGSBASE instructions enabled and applications can use them.
[all …]
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| /linux/Documentation/arch/arm/ |
| H A D | kernel_mode_neon.rst | 7 * Use only NEON instructions, or VFP instructions that don't rely on support
19 It is possible to use NEON instructions (and in some cases, VFP instructions) in
24 may call schedule()], as NEON or VFP instructions will be executed in a
43 should be called before any kernel mode NEON or VFP instructions are issued.
74 Such software assistance is currently not implemented for VFP instructions
82 kernel_neon_end(), i.e., that it is only allowed to issue NEON/VFP instructions
84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
86 instructions appearing in unexpected places if no special care is taken.
98 both NEON and VFP instructions will only ever appear in designated compilation
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| H A D | swp_emulation.rst | 4 ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommends
5 moving to the load-locked/store-conditional instructions LDREX and STREX.
8 instructions, triggering an undefined instruction exception when executed.
9 Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
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| /linux/tools/testing/selftests/powerpc/pmu/ |
| H A D | count_instructions.c | 29 static int do_count_loop(struct event *events, u64 instructions, in do_count_loop() argument
38 thirty_two_instruction_loop(instructions >> 5); in do_count_loop()
45 expected = instructions + overhead; in do_count_loop()
53 printf("Looped for %llu instructions, overhead %llu\n", instructions, overhead); in do_count_loop()
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| /linux/tools/testing/selftests/powerpc/pmu/ebb/ |
| H A D | instruction_count_test.c | 25 static int do_count_loop(struct event *event, uint64_t instructions, in do_count_loop() argument
37 thirty_two_instruction_loop(instructions >> 5); in do_count_loop()
46 expected = instructions + overhead; in do_count_loop()
51 printf("Looped for %lu instructions, overhead %lu\n", instructions, overhead); in do_count_loop()
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| /linux/tools/perf/Documentation/ |
| H A D | intel-acr.txt | 18 perf record -e {cpu_atom/instructions,period=200000,acr_mask=0x2/, \
21 In this case, if the "instructions" counter exceeds the sample period of
28 example above, "instructions" is assigned an acr_mask of 0x2, meaning
43 perf record -e {cpu_atom/instructions/, \
53 cpu_atom/instructions,period=200000,ratio-to-prev=2.0/} -- true
|
| H A D | intel-hybrid.txt | 29 [Fixed Counter: Counts the number of instructions retired. Unit: cpu_atom]
31 [Number of instructions retired. Fixed Counter - architectural event. Unit: cpu_core]
184 cpu_core/instructions/,
185 cpu_atom/instructions/,
199 perf stat -e cpu_core/cycles/,cpu_atom/instructions/
200 perf stat -e '{cpu_core/cycles/,cpu_core/instructions/}'
202 But '{cpu_core/cycles/,cpu_atom/instructions/}' will return
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| /linux/Documentation/virt/kvm/ |
| H A D | ppc-pv.rst | 9 instructions and can emulate them accordingly.
12 instructions that needlessly return us to the hypervisor even though they
15 This is what the PPC PV interface helps with. It takes privileged instructions
35 'hypercall-instructions'. This property contains at most 4 opcodes that make
36 up the hypercall. To call a hypercall, just call these instructions.
138 Patched instructions
141 The "ld" and "std" instructions are transformed to "lwz" and "stw" instructions
147 also act on the shared page. So calling privileged instructions still works as
187 Some instructions require more logic to determine what's going on than a load
189 RAM around where we can live translate instructions to. What happens is the
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| /linux/tools/memory-model/ |
| H A D | linux-kernel.bell | 21 instructions R[Accesses]
22 instructions W[Accesses]
23 instructions RMW[Accesses]
37 instructions F[Barriers]
52 instructions SRCU[SRCU]
|
| /linux/Documentation/virt/ |
| H A D | paravirt_ops.rst | 16 corresponding to low-level critical instructions and high-level
28 Usually these operations correspond to low-level critical instructions. They
34 because they include sensitive instructions or some code paths in
|
| /linux/arch/arm/kernel/ |
| H A D | phys2virt.S | 41 mov r0, r3, lsr #21 @ constant for add/sub instructions
77 @ In the non-LPAE case, all patchable instructions are MOVW
78 @ instructions, where we need to patch in the offset into the
131 @ in BE8, we load data in BE, but instructions still in LE
155 @ In the non-LPAE case, all patchable instructions are ADD or SUB
156 @ instructions, where we need to patch in the offset into the
173 @ instructions based on bits 23:22 of the opcode, and ADD/SUB can be
|
| /linux/Documentation/arch/powerpc/ |
| H A D | elf_hwcaps.rst | 48 The Power ISA uses the term "facility" to describe a class of instructions,
52 instructions that can be used differ between the v3.0B and v3.1B ISA
59 classes of instructions and operating modes which may be optional or
97 The processor has a unified L1 cache for instructions and data, as
139 instructions with the sequence (as described in, e.g., POWER9 Processor
202 v2.07 crypto instructions are available.
214 quad-precision instructions and data types.
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| /linux/arch/m68k/ifpsp060/ |
| H A D | fplsp.doc | 36 FP instructions not implemented in 68060 hardware. These
37 instructions normally take exception vector #11
40 By re-compiling a program that uses these instructions, and
42 instructions, a program can avoid the overhead associated
110 this exception using implemented floating-point instructions.
120 The package does not attempt to correctly emulate instructions
126 subroutine calls for all fp instructions. The code does NOT emulate
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| /linux/Documentation/arch/arm/nwfpe/ |
| H A D | netwinder-fpe.rst | 9 instructions. It follows the conventions in the ARM manual.
28 These instructions are fully implemented.
40 These instructions are fully implemented. They store/load three words
49 Conversions, read/write status/control register instructions
62 RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and
66 Compare instructions
95 equivalent to the MUF/DVF/RDV instructions. This is acceptable according
|
| /linux/tools/arch/x86/kcpuid/ |
| H A D | cpuid.csv | 57 0x1, 0, ecx, 25, aes , AES instructions
58 0x1, 0, ecx, 26, xsave , XSAVE (and related instructions) support
59 0x1, 0, ecx, 27, osxsave , XSAVE (and related instructions) are enabled by OS
60 0x1, 0, ecx, 28, avx , AVX instructions support
85 0x1, 0, edx, 23, mmx , MMX instructions
86 0x1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions
87 0x1, 0, edx, 25, sse , SSE instructions
88 0x1, 0, edx, 26, sse2 , SSE2 instructions
137 # MONITOR/MWAIT instructions enumeration
205 0x7, 0, ebx, 16, avx512f , AVX-512 foundation instructions
[all...] |
| /linux/arch/openrisc/ |
| H A D | Kconfig | 134 This config enables gcc to generate l.cmov instructions when compiling
147 This config enables gcc to generate l.ror instructions when compiling
160 This config enables gcc to generate l.rori instructions when compiling
170 bool "Have instructions l.ext* for sign extension"
173 This config enables gcc to generate l.ext* instructions when compiling
178 l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | special-register-buffer-data-sampling.rst | 13 When RDRAND, RDSEED and EGETKEY instructions are used, the data is moved
65 EGETKEY instructions to overwrite secret special register data in the shared
69 During execution of the RDRAND, RDSEED, or EGETKEY instructions, off-core
76 #. RDRAND, RDSEED, or EGETKEY instructions have higher latency.
87 the mitigation for RDRAND and RDSEED instructions executed outside of Intel
|