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Searched refs:gpu_addr (Results 1 – 25 of 118) sorted by relevance

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/linux/drivers/gpu/drm/radeon/
H A Dr600_dma.c143 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
145 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_dma_resume()
150 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
236 u64 gpu_addr; in r600_dma_ring_test() local
243 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ring_test()
254 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
255 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
290 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
317 u64 addr = semaphore->gpu_addr; in r600_dma_semaphore_ring_emit()
343 u64 gpu_addr; in r600_dma_ib_test() local
[all …]
H A Duvd_v4_2.c47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume()
49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
H A Dcik_sdma.c154 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_ib_execute()
155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
232 u64 addr = semaphore->gpu_addr; in cik_sdma_semaphore_ring_emit()
400 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
402 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cik_sdma_gfx_resume()
407 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
408 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
651 u64 gpu_addr; in cik_sdma_ring_test() local
658 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ring_test()
[all …]
H A Duvd_v2_2.c43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit()
113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
H A Dradeon_semaphore.c51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create()
69 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_emit_signal()
86 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_emit_wait()
H A Dvce_v1_0.c218 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume()
300 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); in vce_v1_0_start()
301 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
307 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); in vce_v1_0_start()
308 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
H A Dradeon_trace.h177 __field(uint64_t, gpu_addr)
183 __entry->gpu_addr = sem->gpu_addr;
187 __entry->waiters, __entry->gpu_addr)
H A Devergreen_dma.c44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
88 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in evergreen_dma_ring_ib_execute()
89 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_userqueue.c87 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); in mes_userq_create_wptr_mapping()
136 queue_input.process_context_addr = ctx->gpu_addr; in mes_userq_map()
137 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; in mes_userq_map()
143 queue_input.mqd_addr = queue->mqd.gpu_addr; in mes_userq_map()
148 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; in mes_userq_map()
172 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; in mes_userq_unmap()
197 &ctx->obj, &ctx->gpu_addr, in mes_userq_create_ctx_space()
280 &queue->mqd.obj, &queue->mqd.gpu_addr, in mes_userq_mqd_create()
295 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; in mes_userq_mqd_create()
298 userq_props->fence_address = queue->fence_drv->gpu_addr; in mes_userq_mqd_create()
[all …]
H A Damdgpu_isp.c180 u64 gpu_addr; in isp_user_buffer_alloc() local
204 AMDGPU_GEM_DOMAIN_GTT, &bo, &gpu_addr); in isp_user_buffer_alloc()
211 *buf_addr = gpu_addr; in isp_user_buffer_alloc()
251 void **buf_obj, u64 *gpu_addr, void **cpu_addr) in isp_kernel_buffer_alloc() argument
266 if (WARN_ON(!gpu_addr)) in isp_kernel_buffer_alloc()
290 gpu_addr, in isp_kernel_buffer_alloc()
313 void isp_kernel_buffer_free(void **buf_obj, u64 *gpu_addr, void **cpu_addr) in isp_kernel_buffer_free() argument
317 amdgpu_bo_free_kernel(bo, gpu_addr, cpu_addr); in isp_kernel_buffer_free()
H A Dvcn_v2_0.c400 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
402 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
412 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
414 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
420 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
422 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
428 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
430 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
468 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
471 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
[all …]
H A Damdgpu_seq64.c174 u64 *gpu_addr, u64 **cpu_addr) in amdgpu_seq64_alloc() argument
190 if (gpu_addr) in amdgpu_seq64_alloc()
191 *gpu_addr = bit_pos * sizeof(u64) + adev->seq64.gpu_addr; in amdgpu_seq64_alloc()
253 &adev->seq64.sbo, &adev->seq64.gpu_addr, in amdgpu_seq64_init()
H A Dvcn_v2_5.c609 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
611 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
620 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
622 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
628 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
630 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
636 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
638 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
675 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
678 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
[all …]
H A Dvcn_v5_0_2.c338 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_2_mc_resume()
340 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_2_mc_resume()
349 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_2_mc_resume()
351 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_2_mc_resume()
357 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_2_mc_resume()
359 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_2_mc_resume()
365 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_2_mc_resume()
367 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_2_mc_resume()
417 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
420 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
[all …]
H A Dvcn_v5_0_1.c441 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_1_mc_resume()
443 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_1_mc_resume()
452 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_1_mc_resume()
454 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_1_mc_resume()
460 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_1_mc_resume()
462 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_1_mc_resume()
468 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_1_mc_resume()
470 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_1_mc_resume()
520 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
523 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
[all …]
H A Dvcn_v3_0.c537 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
539 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
548 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
550 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
556 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
558 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
564 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
566 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
603 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
606 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
[all …]
H A Damdgpu_sa.c54 &sa_manager->bo, &sa_manager->gpu_addr, in amdgpu_sa_bo_manager_init()
76 amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr); in amdgpu_sa_bo_manager_fini()
113 drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr); in amdgpu_sa_bo_dump_debug_info()
H A Dvcn_v4_0.c467 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
469 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
477 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
479 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
485 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
487 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
493 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_mc_resume()
495 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_mc_resume()
542 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
545 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
[all …]
H A Dvcn_v5_0_0.c382 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_0_mc_resume()
384 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_0_mc_resume()
392 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_0_mc_resume()
394 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_0_mc_resume()
400 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_0_mc_resume()
402 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_0_mc_resume()
408 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_0_mc_resume()
410 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_0_mc_resume()
458 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
461 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
[all …]
H A Dvce_v3_0.c283 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); in vce_v3_0_start()
284 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
290 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); in vce_v3_0_start()
291 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
297 WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); in vce_v3_0_start()
298 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
571 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
572 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
573 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
575 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
[all …]
H A Dvcn_v4_0_3.c494 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); in vcn_v4_0_3_mc_resume()
497 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); in vcn_v4_0_3_mc_resume()
506 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); in vcn_v4_0_3_mc_resume()
508 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); in vcn_v4_0_3_mc_resume()
515 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + in vcn_v4_0_3_mc_resume()
518 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + in vcn_v4_0_3_mc_resume()
527 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); in vcn_v4_0_3_mc_resume()
530 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); in vcn_v4_0_3_mc_resume()
581 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
584 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
[all …]
H A Damdgpu_object.h260 u64 *gpu_addr, void **cpu_addr);
264 u64 *gpu_addr, void **cpu_addr);
268 u64 *gpu_addr);
278 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
326 return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr + in amdgpu_sa_bo_gpu_addr()
H A Dvcn_v4_0_5.c418 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_5_mc_resume()
420 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_5_mc_resume()
428 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_5_mc_resume()
430 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_5_mc_resume()
436 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_5_mc_resume()
438 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_5_mc_resume()
444 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_5_mc_resume()
446 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_5_mc_resume()
496 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
499 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager.c59 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; in allocate_hiq_mqd()
86 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in allocate_sdma_mqd()
287 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in kfd_get_hiq_xcc_mqd()
/linux/include/drm/amd/
H A Disp.h47 void **buf_obj, u64 *gpu_addr, void **cpu_addr);
49 void isp_kernel_buffer_free(void **buf_obj, u64 *gpu_addr, void **cpu_addr);

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