xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c (revision 03c11eb3b16dc0058589751dfd91f254be2be613)
1d38ceaf9SAlex Deucher /*
2d38ceaf9SAlex Deucher  * Copyright 2011 Red Hat Inc.
3d38ceaf9SAlex Deucher  * All Rights Reserved.
4d38ceaf9SAlex Deucher  *
5d38ceaf9SAlex Deucher  * Permission is hereby granted, free of charge, to any person obtaining a
6d38ceaf9SAlex Deucher  * copy of this software and associated documentation files (the
7d38ceaf9SAlex Deucher  * "Software"), to deal in the Software without restriction, including
8d38ceaf9SAlex Deucher  * without limitation the rights to use, copy, modify, merge, publish,
9d38ceaf9SAlex Deucher  * distribute, sub license, and/or sell copies of the Software, and to
10d38ceaf9SAlex Deucher  * permit persons to whom the Software is furnished to do so, subject to
11d38ceaf9SAlex Deucher  * the following conditions:
12d38ceaf9SAlex Deucher  *
13d38ceaf9SAlex Deucher  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14d38ceaf9SAlex Deucher  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15d38ceaf9SAlex Deucher  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16d38ceaf9SAlex Deucher  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17d38ceaf9SAlex Deucher  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18d38ceaf9SAlex Deucher  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19d38ceaf9SAlex Deucher  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20d38ceaf9SAlex Deucher  *
21d38ceaf9SAlex Deucher  * The above copyright notice and this permission notice (including the
22d38ceaf9SAlex Deucher  * next paragraph) shall be included in all copies or substantial portions
23d38ceaf9SAlex Deucher  * of the Software.
24d38ceaf9SAlex Deucher  *
25d38ceaf9SAlex Deucher  */
26d38ceaf9SAlex Deucher /*
27d38ceaf9SAlex Deucher  * Authors:
28d38ceaf9SAlex Deucher  *    Jerome Glisse <glisse@freedesktop.org>
29d38ceaf9SAlex Deucher  */
30d38ceaf9SAlex Deucher /* Algorithm:
31d38ceaf9SAlex Deucher  *
32d38ceaf9SAlex Deucher  * We store the last allocated bo in "hole", we always try to allocate
33d38ceaf9SAlex Deucher  * after the last allocated bo. Principle is that in a linear GPU ring
34d38ceaf9SAlex Deucher  * progression was is after last is the oldest bo we allocated and thus
35d38ceaf9SAlex Deucher  * the first one that should no longer be in use by the GPU.
36d38ceaf9SAlex Deucher  *
37d38ceaf9SAlex Deucher  * If it's not the case we skip over the bo after last to the closest
38d38ceaf9SAlex Deucher  * done bo if such one exist. If none exist and we are not asked to
39d38ceaf9SAlex Deucher  * block we report failure to allocate.
40d38ceaf9SAlex Deucher  *
41d38ceaf9SAlex Deucher  * If we are asked to block we wait on all the oldest fence of all
42d38ceaf9SAlex Deucher  * rings. We just wait for any of those fence to complete.
43d38ceaf9SAlex Deucher  */
44fdf2f6c5SSam Ravnborg 
45d38ceaf9SAlex Deucher #include "amdgpu.h"
46d38ceaf9SAlex Deucher 
amdgpu_sa_bo_manager_init(struct amdgpu_device * adev,struct amdgpu_sa_manager * sa_manager,unsigned int size,u32 suballoc_align,u32 domain)47d38ceaf9SAlex Deucher int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
48d38ceaf9SAlex Deucher 			      struct amdgpu_sa_manager *sa_manager,
49c103a23fSMaarten Lankhorst 			      unsigned int size, u32 suballoc_align, u32 domain)
50d38ceaf9SAlex Deucher {
51c103a23fSMaarten Lankhorst 	int r;
52d38ceaf9SAlex Deucher 
53c103a23fSMaarten Lankhorst 	r = amdgpu_bo_create_kernel(adev, size, AMDGPU_GPU_PAGE_SIZE, domain,
54c103a23fSMaarten Lankhorst 				    &sa_manager->bo, &sa_manager->gpu_addr,
55c103a23fSMaarten Lankhorst 				    &sa_manager->cpu_ptr);
56d38ceaf9SAlex Deucher 	if (r) {
57d38ceaf9SAlex Deucher 		dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
58d38ceaf9SAlex Deucher 		return r;
59d38ceaf9SAlex Deucher 	}
60d38ceaf9SAlex Deucher 
61c103a23fSMaarten Lankhorst 	memset(sa_manager->cpu_ptr, 0, size);
62c103a23fSMaarten Lankhorst 	drm_suballoc_manager_init(&sa_manager->base, size, suballoc_align);
63d38ceaf9SAlex Deucher 	return r;
64d38ceaf9SAlex Deucher }
65d38ceaf9SAlex Deucher 
amdgpu_sa_bo_manager_fini(struct amdgpu_device * adev,struct amdgpu_sa_manager * sa_manager)66d38ceaf9SAlex Deucher void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
67d38ceaf9SAlex Deucher 			       struct amdgpu_sa_manager *sa_manager)
68d38ceaf9SAlex Deucher {
69bffe07b8SMonk Liu 	if (sa_manager->bo == NULL) {
70bffe07b8SMonk Liu 		dev_err(adev->dev, "no bo for sa manager\n");
71bffe07b8SMonk Liu 		return;
72bffe07b8SMonk Liu 	}
73bffe07b8SMonk Liu 
74c103a23fSMaarten Lankhorst 	drm_suballoc_manager_fini(&sa_manager->base);
75bffe07b8SMonk Liu 
76bffe07b8SMonk Liu 	amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr);
77d38ceaf9SAlex Deucher }
78d38ceaf9SAlex Deucher 
amdgpu_sa_bo_new(struct amdgpu_sa_manager * sa_manager,struct drm_suballoc ** sa_bo,unsigned int size)79bbf0b345SJunwei Zhang int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
80c103a23fSMaarten Lankhorst 		     struct drm_suballoc **sa_bo,
81c103a23fSMaarten Lankhorst 		     unsigned int size)
82d38ceaf9SAlex Deucher {
83c103a23fSMaarten Lankhorst 	struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size,
84*e2884fe8SSimon Pilkington 						   GFP_KERNEL, false, 0);
85d38ceaf9SAlex Deucher 
86c103a23fSMaarten Lankhorst 	if (IS_ERR(sa)) {
87c103a23fSMaarten Lankhorst 		*sa_bo = NULL;
88fe6b2ad9SChristian König 
89c103a23fSMaarten Lankhorst 		return PTR_ERR(sa);
90c103a23fSMaarten Lankhorst 	}
91d38ceaf9SAlex Deucher 
92c103a23fSMaarten Lankhorst 	*sa_bo = sa;
93d38ceaf9SAlex Deucher 	return 0;
94d38ceaf9SAlex Deucher }
95d38ceaf9SAlex Deucher 
amdgpu_sa_bo_free(struct amdgpu_device * adev,struct drm_suballoc ** sa_bo,struct dma_fence * fence)96c103a23fSMaarten Lankhorst void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct drm_suballoc **sa_bo,
97f54d1867SChris Wilson 		       struct dma_fence *fence)
98d38ceaf9SAlex Deucher {
99d38ceaf9SAlex Deucher 	if (sa_bo == NULL || *sa_bo == NULL) {
100d38ceaf9SAlex Deucher 		return;
101d38ceaf9SAlex Deucher 	}
102d38ceaf9SAlex Deucher 
103c103a23fSMaarten Lankhorst 	drm_suballoc_free(*sa_bo, fence);
104d38ceaf9SAlex Deucher 	*sa_bo = NULL;
105d38ceaf9SAlex Deucher }
106d38ceaf9SAlex Deucher 
107d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS)
1084f839a24SChristian König 
amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager * sa_manager,struct seq_file * m)109d38ceaf9SAlex Deucher void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
110d38ceaf9SAlex Deucher 				  struct seq_file *m)
111d38ceaf9SAlex Deucher {
112c103a23fSMaarten Lankhorst 	struct drm_printer p = drm_seq_file_printer(m);
113d38ceaf9SAlex Deucher 
114c103a23fSMaarten Lankhorst 	drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr);
115d38ceaf9SAlex Deucher }
116d38ceaf9SAlex Deucher #endif
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