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Searched refs:gate (Results 1 – 25 of 301) sorted by relevance

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/linux/drivers/clk/tegra/
H A Dclk-periph-gate.c19 #define read_enb(gate) \ argument
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
21 #define write_enb_set(val, gate) \ argument
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
23 #define write_enb_clr(val, gate) \ argument
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
26 #define read_rst(gate) \ argument
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
28 #define write_rst_clr(val, gate) \ argument
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
[all …]
/linux/drivers/clk/imx/
H A Dclk-gate-93.c49 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); in imx93_clk_gate_do_hardware() local
52 val = readl(gate->reg + AUTHEN_OFFSET); in imx93_clk_gate_do_hardware()
55 writel(val, gate->reg + LPM_CUR_OFFSET); in imx93_clk_gate_do_hardware()
57 val = readl(gate->reg + DIRECT_OFFSET); in imx93_clk_gate_do_hardware()
58 val &= ~(gate->mask << gate->bit_idx); in imx93_clk_gate_do_hardware()
60 val |= (gate->val & gate->mask) << gate->bit_idx; in imx93_clk_gate_do_hardware()
61 writel(val, gate->reg + DIRECT_OFFSET); in imx93_clk_gate_do_hardware()
67 struct imx93_clk_gate *gate = to_imx93_clk_gate(hw); in imx93_clk_gate_enable() local
70 spin_lock_irqsave(gate->lock, flags); in imx93_clk_gate_enable()
72 if (gate->share_count && (*gate->share_count)++ > 0) in imx93_clk_gate_enable()
[all …]
H A Dclk-gate2.c43 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_do_shared_clks() local
46 reg = readl(gate->reg); in clk_gate2_do_shared_clks()
47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
50 writel(reg, gate->reg); in clk_gate2_do_shared_clks()
55 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_enable() local
58 spin_lock_irqsave(gate->lock, flags); in clk_gate2_enable()
60 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
65 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_enable()
72 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_disable() local
[all …]
H A Dclk-composite-7ulp.c31 struct clk_gate *gate = to_clk_gate(hw); in pcc_gate_enable() local
43 spin_lock_irqsave(gate->lock, flags); in pcc_gate_enable()
48 val = readl(gate->reg); in pcc_gate_enable()
50 writel(val, gate->reg); in pcc_gate_enable()
52 spin_unlock_irqrestore(gate->lock, flags); in pcc_gate_enable()
60 readl(gate->reg); in pcc_gate_enable()
90 struct clk_gate *gate = NULL; in imx_ulp_clk_hw_composite() local
131 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in imx_ulp_clk_hw_composite()
132 if (!gate) { in imx_ulp_clk_hw_composite()
137 gate_hw = &gate->hw; in imx_ulp_clk_hw_composite()
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-gate-grf.c29 struct rockchip_gate_grf *gate = to_gate_grf(hw); in rockchip_gate_grf_enable() local
30 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0; in rockchip_gate_grf_enable()
31 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_enable()
34 ret = regmap_update_bits(gate->regmap, gate->reg, in rockchip_gate_grf_enable()
35 hiword | BIT(gate->shift), hiword | val); in rockchip_gate_grf_enable()
42 struct rockchip_gate_grf *gate = to_gate_grf(hw); in rockchip_gate_grf_disable() local
43 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shift); in rockchip_gate_grf_disable()
44 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_disable()
46 regmap_update_bits(gate->regmap, gate->reg, in rockchip_gate_grf_disable()
47 hiword | BIT(gate->shift), hiword | val); in rockchip_gate_grf_disable()
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_power.c75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
94 gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
96 sm750_set_current_gate(gate); in sm750_enable_2d_engine()
101 u32 gate; in sm750_enable_dma() local
104 gate = peek32(CURRENT_GATE); in sm750_enable_dma()
[all …]
/linux/drivers/clk/visconti/
H A Dclkc.c30 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); in visconti_gate_clk_is_enabled() local
31 u32 clk = BIT(gate->ck_idx); in visconti_gate_clk_is_enabled()
34 regmap_read(gate->regmap, gate->ckon_offset, &val); in visconti_gate_clk_is_enabled()
40 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); in visconti_gate_clk_disable() local
41 u32 clk = BIT(gate->ck_idx); in visconti_gate_clk_disable()
44 spin_lock_irqsave(gate->lock, flags); in visconti_gate_clk_disable()
47 spin_unlock_irqrestore(gate->lock, flags); in visconti_gate_clk_disable()
51 regmap_update_bits(gate->regmap, gate->ckoff_offset, clk, clk); in visconti_gate_clk_disable()
52 spin_unlock_irqrestore(gate->lock, flags); in visconti_gate_clk_disable()
57 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); in visconti_gate_clk_enable() local
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-gate.c23 const struct mtk_gate *gate; member
36 regmap_read(cg->regmap, cg->gate->regs->sta_ofs, &val); in mtk_get_clockgating()
38 return val & BIT(cg->gate->shift); in mtk_get_clockgating()
55 regmap_write(cg->regmap, cg->gate->regs->set_ofs, BIT(cg->gate->shift)); in mtk_cg_set_bit()
62 regmap_write(cg->regmap, cg->gate->regs->clr_ofs, BIT(cg->gate->shift)); in mtk_cg_clr_bit()
69 regmap_set_bits(cg->regmap, cg->gate->regs->sta_ofs, in mtk_cg_set_bit_no_setclr()
70 BIT(cg->gate->shift)); in mtk_cg_set_bit_no_setclr()
77 regmap_clear_bits(cg->regmap, cg->gate->regs->sta_ofs, in mtk_cg_clr_bit_no_setclr()
78 BIT(cg->gate->shift)); in mtk_cg_clr_bit_no_setclr()
111 enable ? cg->gate->hwv_regs->set_ofs : in mtk_cg_hwv_set_en()
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-gate.c25 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); in uniphier_clk_gate_endisable() local
27 return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), in uniphier_clk_gate_endisable()
28 enable ? BIT(gate->bit) : 0); in uniphier_clk_gate_endisable()
44 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); in uniphier_clk_gate_is_enabled() local
47 if (regmap_read(gate->regmap, gate->reg, &val) < 0) in uniphier_clk_gate_is_enabled()
50 return !!(val & BIT(gate->bit)); in uniphier_clk_gate_is_enabled()
64 struct uniphier_clk_gate *gate; in uniphier_clk_register_gate() local
68 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); in uniphier_clk_register_gate()
69 if (!gate) in uniphier_clk_register_gate()
78 gate->regmap = regmap; in uniphier_clk_register_gate()
[all …]
/linux/drivers/clk/ingenic/
H A Djz4755-cgu.c144 .gate = { CGU_REG_CLKGR, 10 },
151 .gate = { CGU_REG_CLKGR, 9 },
171 .gate = { CGU_REG_CLKGR, 4 },
178 .gate = { CGU_REG_CLKGR, 18 },
185 .gate = { CGU_REG_CLKGR, 2 },
192 .gate = { CGU_REG_CLKGR, 8 },
200 .gate = { CGU_REG_CLKGR, 0 },
206 .gate = { CGU_REG_CLKGR, 14 },
212 .gate = { CGU_REG_CLKGR, 15 },
218 .gate = { CGU_REG_CLKGR, 7 },
[all …]
H A Djz4770-cgu.c178 .gate = { CGU_REG_CLKGR1, 7 },
195 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
213 .gate = { CGU_REG_MSC0CDR, 31 },
220 .gate = { CGU_REG_MSC1CDR, 31 },
227 .gate = { CGU_REG_MSC2CDR, 31 },
234 .gate = { CGU_REG_CLKGR0, 26 },
241 .gate = { CGU_REG_CLKGR0, 24 },
248 .gate = { CGU_REG_CLKGR1, 9 },
255 .gate = { CGU_REG_CLKGR0, 1 },
262 .gate = { CGU_REG_CLKGR0, 28 },
[all …]
H A Djz4780-cgu.c409 .gate = { CGU_REG_CLKGR1, 2 },
451 .gate = { CGU_REG_CLKGR0, 3 },
458 .gate = { CGU_REG_CLKGR0, 11 },
465 .gate = { CGU_REG_CLKGR0, 12 },
474 .gate = { CGU_REG_CLKGR0, 24 },
509 .gate = { CGU_REG_CLKGR1, 3 },
518 .gate = { CGU_REG_CLKGR1, 4 },
527 .gate = { CGU_REG_CLKGR1, 9 },
536 .gate = { CGU_REG_CLKGR0, 1 },
556 .gate = { CGU_REG_CLKGR0, 0 },
[all …]
H A Djz4760-cgu.c219 .gate = { CGU_REG_CLKGR0, 24 },
226 .gate = { CGU_REG_CLKGR1, 9 },
238 .gate = { CGU_REG_CLKGR0, 27 },
244 .gate = { CGU_REG_CLKGR0, 28 },
251 .gate = { CGU_REG_CLKGR0, 22 },
262 .gate = { CGU_REG_CLKGR1, 8 },
277 .gate = { CGU_REG_CLKGR0, 2 },
299 .gate = { CGU_REG_CLKGR0, 26 },
307 .gate = { CGU_REG_CLKGR0, 4 },
312 .gate = { CGU_REG_CLKGR0, 19 },
[all …]
H A Dx1830-cgu.c231 .gate = { CGU_REG_CLKGR1, 15 },
268 .gate = { CGU_REG_CLKGR1, 14 },
281 .gate = { CGU_REG_CLKGR0, 31 },
290 .gate = { CGU_REG_CLKGR1, 4 },
299 .gate = { CGU_REG_CLKGR1, 9 },
313 .gate = { CGU_REG_CLKGR0, 4 },
320 .gate = { CGU_REG_CLKGR0, 5 },
353 .gate = { CGU_REG_CLKGR0, 29 },
361 .gate = { CGU_REG_CLKGR0, 0 },
367 .gate = { CGU_REG_CLKGR0, 1 },
[all …]
H A Djz4740-cgu.c156 .gate = { CGU_REG_CLKGR, 10 },
170 .gate = { CGU_REG_CLKGR, 6 },
178 .gate = { CGU_REG_CLKGR, 4 },
185 .gate = { CGU_REG_CLKGR, 7 },
192 .gate = { CGU_REG_CLKGR, 14 },
200 .gate = { CGU_REG_SCR, 6, true },
208 .gate = { CGU_REG_CLKGR, 0 },
214 .gate = { CGU_REG_CLKGR, 15 },
220 .gate = { CGU_REG_CLKGR, 12 },
226 .gate = { CGU_REG_CLKGR, 13 },
[all …]
H A Dx1000-cgu.c295 .gate = { CGU_REG_CLKGR, 30 },
332 .gate = { CGU_REG_CLKGR, 28 },
345 .gate = { CGU_REG_CLKGR, 31 },
353 .gate = { CGU_REG_CLKGR, 25 },
392 .gate = { CGU_REG_CLKGR, 23 },
405 .gate = { CGU_REG_CLKGR, 4 },
412 .gate = { CGU_REG_CLKGR, 5 },
420 .gate = { CGU_REG_CLKGR, 3 },
452 .gate = { CGU_REG_CLKGR, 27 },
460 .gate = { CGU_REG_CLKGR, 0 },
[all …]
H A Djz4725b-cgu.c141 .gate = { CGU_REG_CLKGR, 13 },
148 .gate = { CGU_REG_CLKGR, 9 },
163 .gate = { CGU_REG_CLKGR, 4 },
184 .gate = { CGU_REG_CLKGR, 0 },
190 .gate = { CGU_REG_CLKGR, 12 },
196 .gate = { CGU_REG_CLKGR, 7 },
202 .gate = { CGU_REG_CLKGR, 3 },
208 .gate = { CGU_REG_CLKGR, 5 },
214 .gate = { CGU_REG_CLKGR, 6 },
220 .gate = { CGU_REG_CLKGR, 16 },
[all …]
/linux/drivers/clk/zynqmp/
H A Dclk-gate-zynqmp.c36 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_enable() local
38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable()
56 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_disable() local
58 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable()
76 struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); in zynqmp_clk_gate_is_enabled() local
78 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled()
112 struct zynqmp_clk_gate *gate; in zynqmp_clk_register_gate() local
118 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in zynqmp_clk_register_gate()
119 if (!gate) in zynqmp_clk_register_gate()
131 gate->flags = nodes->type_flag; in zynqmp_clk_register_gate()
[all …]
/linux/drivers/clk/bcm/
H A Dclk-kona.c333 __is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __is_clk_gate_enabled() argument
339 if (!gate_exists(gate)) in __is_clk_gate_enabled()
342 bit_mask = 1 << gate->status_bit; in __is_clk_gate_enabled()
343 reg_val = __ccu_read(ccu, gate->offset); in __is_clk_gate_enabled()
350 is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in is_clk_gate_enabled() argument
356 if (!gate_exists(gate)) in is_clk_gate_enabled()
360 ret = __is_clk_gate_enabled(ccu, gate); in is_clk_gate_enabled()
371 __gate_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __gate_commit() argument
377 BUG_ON(!gate_exists(gate)); in __gate_commit()
378 if (!gate_is_sw_controllable(gate)) in __gate_commit()
[all …]
H A Dclk-bcm281xx.c16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
34 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
43 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
76 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
95 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
107 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
119 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
131 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
143 .gate = HW_SW_GATE(0x0354, 18, 2, 3),
154 .gate = HW_SW_GATE(0x0370, 18, 2, 3),
[all …]
H A Dclk-bcm21664.c16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
33 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
58 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
70 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
82 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
94 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
107 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
112 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
117 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
122 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
[all …]
/linux/drivers/clk/
H A Dclk-aspeed.c186 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_clk_is_enabled() local
187 u32 clk = BIT(gate->clock_idx); in aspeed_clk_is_enabled()
188 u32 rst = BIT(gate->reset_idx); in aspeed_clk_is_enabled()
189 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; in aspeed_clk_is_enabled()
198 if (gate->reset_idx >= 0) { in aspeed_clk_is_enabled()
199 regmap_read(gate->map, ASPEED_RESET_CTRL, &reg); in aspeed_clk_is_enabled()
204 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg); in aspeed_clk_is_enabled()
211 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_clk_enable() local
213 u32 clk = BIT(gate->clock_idx); in aspeed_clk_enable()
214 u32 rst = BIT(gate->reset_idx); in aspeed_clk_enable()
[all …]
/linux/drivers/clk/stm32/
H A Dclk-stm32-core.c137 const struct stm32_gate_cfg *gate = &data->gates[gate_id]; in stm32_gate_endisable() local
138 void __iomem *addr = base + gate->offset; in stm32_gate_endisable()
144 if (gate->set_clr != 0) in stm32_gate_endisable()
145 writel(BIT(gate->bit_idx), addr); in stm32_gate_endisable()
147 writel(readl(addr) | BIT(gate->bit_idx), addr); in stm32_gate_endisable()
152 if (gate->set_clr != 0) in stm32_gate_endisable()
153 writel(BIT(gate->bit_idx), addr + gate->set_clr); in stm32_gate_endisable()
155 writel(readl(addr) & ~BIT(gate->bit_idx), addr); in stm32_gate_endisable()
163 const struct stm32_gate_cfg *gate = &data->gates[gate_id]; in stm32_gate_disable_unused() local
164 void __iomem *addr = base + gate->offset; in stm32_gate_disable_unused()
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi302 compatible = "altr,socfpga-gate-clk";
304 clk-gate = <0x60 0>;
316 compatible = "altr,socfpga-gate-clk";
319 clk-gate = <0x60 1>;
324 compatible = "altr,socfpga-gate-clk";
331 compatible = "altr,socfpga-gate-clk";
334 clk-gate = <0x60 2>;
339 compatible = "altr,socfpga-gate-clk";
342 clk-gate = <0x60 3>;
347 compatible = "altr,socfpga-gate-clk";
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-a10-mod1.c25 struct clk_gate *gate; in sun4i_mod1_clk_setup() local
39 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sun4i_mod1_clk_setup()
40 if (!gate) in sun4i_mod1_clk_setup()
46 gate->reg = reg; in sun4i_mod1_clk_setup()
47 gate->bit_idx = SUN4I_MOD1_ENABLE; in sun4i_mod1_clk_setup()
48 gate->lock = &mod1_lock; in sun4i_mod1_clk_setup()
57 &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT); in sun4i_mod1_clk_setup()
66 kfree(gate); in sun4i_mod1_clk_setup()

12345678910>>...13