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Searched refs:feature_mask (Results 1 – 25 of 45) sorted by relevance

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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr.c102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
123 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init()
136 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
170 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
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H A Dvega20_hwmgr.c103 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) in vega20_set_default_registry_data()
106 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) in vega20_set_default_registry_data()
109 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) in vega20_set_default_registry_data()
112 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) in vega20_set_default_registry_data()
115 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK)) in vega20_set_default_registry_data()
118 if (!(hwmgr->feature_mask & PP_ULV_MASK)) in vega20_set_default_registry_data()
121 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)) in vega20_set_default_registry_data()
173 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); in vega20_set_default_registry_data()
1820 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) in vega20_upload_dpm_min_level() argument
1828 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in vega20_upload_dpm_min_level()
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H A Dvega10_hwmgr.c120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
126 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in vega10_set_default_registry_data()
129 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
131 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { in vega10_set_default_registry_data()
138 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; in vega10_set_default_registry_data()
141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data()
144 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; in vega10_set_default_registry_data()
153 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; in vega10_set_default_registry_data()
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/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c767 struct smu_feature_bits *feature_mask) in smu_cmn_get_enabled_mask() argument
772 if (!feature_mask) in smu_cmn_get_enabled_mask()
797 smu_feature_bits_from_arr32(feature_mask, features, in smu_cmn_get_enabled_mask()
817 uint64_t feature_mask, in smu_cmn_feature_update_enable_state() argument
825 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
831 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
836 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
842 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
884 struct smu_feature_bits feature_mask; in smu_cmn_get_pp_feature_mask() local
890 if (__smu_get_enabled_features(smu, &feature_mask)) in smu_cmn_get_pp_feature_mask()
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H A Dsmu_cmn.h144 struct smu_feature_bits *feature_mask);
151 uint64_t feature_mask,
/linux/drivers/net/
H A Dtap.c864 netdev_features_t feature_mask = 0; in set_offload() local
873 feature_mask = NETIF_F_HW_CSUM; in set_offload()
877 feature_mask |= NETIF_F_TSO_ECN; in set_offload()
879 feature_mask |= NETIF_F_TSO; in set_offload()
881 feature_mask |= NETIF_F_TSO6; in set_offload()
897 if (feature_mask & (NETIF_F_TSO | NETIF_F_TSO6) || in set_offload()
898 (feature_mask & (TUN_F_USO4 | TUN_F_USO6)) == (TUN_F_USO4 | TUN_F_USO6)) in set_offload()
906 tap->tap_features = feature_mask; in set_offload()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega10_smumgr.h46 bool enable, uint32_t feature_mask);
H A Dvega12_smumgr.h52 bool enable, uint64_t feature_mask);
H A Dvega20_smumgr.h51 bool enable, uint64_t feature_mask);
H A Dvega12_smumgr.c126 bool enable, uint64_t feature_mask) in vega12_enable_smc_features() argument
130 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega12_enable_smc_features()
131 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega12_enable_smc_features()
H A Dvega20_smumgr.c318 bool enable, uint64_t feature_mask) in vega20_enable_smc_features() argument
323 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega20_enable_smc_features()
324 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega20_enable_smc_features()
H A Dvega10_smumgr.c112 bool enable, uint32_t feature_mask) in vega10_enable_smc_features() argument
126 msg, feature_mask, NULL); in vega10_enable_smc_features()
/linux/drivers/accel/amdxdna/
H A Daie2_pci.h122 unsigned long feature_mask; member
193 unsigned long feature_mask; member
246 #define AIE2_FEATURE_ON(ndev, feature) test_bit(feature, &(ndev)->feature_mask)
H A Daie2_pci.c75 ndev->feature_mask |= feature->features; in aie2_check_protocol()
174 if (cfg->feature_mask && in aie2_runtime_cfg()
175 bitmap_subset(&cfg->feature_mask, &ndev->feature_mask, AIE2_FEATURE_MAX)) in aie2_runtime_cfg()
/linux/net/smc/
H A Dsmc_clc.c459 fce_v2x->feature_mask = htons(ini->feature_mask); in smc_clc_fill_fce_v2x()
942 v2_ext->feature_mask = htons(SMC_FEATURE_MASK); in smc_clc_send_proposal()
1263 ini->feature_mask = SMC_FEATURE_MASK; in smc_clc_srv_v2x_features_validate()
1308 ini->feature_mask = ntohs(fce_v2x->feature_mask) & SMC_FEATURE_MASK; in smc_clc_clnt_v2x_features_validate()
1338 ini->feature_mask = ntohs(fce_v2x->feature_mask); in smc_clc_v2x_features_confirm_check()
H A Dsmc_clc.h143 __be16 feature_mask;
267 __be16 feature_mask; member
/linux/include/sound/sof/
H A Dext_manifest4.h74 uint32_t feature_mask; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c573 struct smu_feature_bits *feature_mask) in cyan_skillfish_get_enabled_mask() argument
575 if (!feature_mask) in cyan_skillfish_get_enabled_mask()
577 smu_feature_bits_fill(feature_mask); in cyan_skillfish_get_enabled_mask()
H A Darcturus_ppt.c884 uint32_t feature_mask, in arcturus_upload_dpm_level() argument
893 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in arcturus_upload_dpm_level()
907 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in arcturus_upload_dpm_level()
921 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { in arcturus_upload_dpm_level()
1747 uint32_t feature_mask; member
1775 if (throttler_status & logging_label[throttler_idx].feature_mask) { in arcturus_log_thermal_throttling_event()
/linux/include/linux/mfd/
H A Dkempld.h91 u32 feature_mask; member
/linux/drivers/pci/msi/
H A Dmsi.h109 bool pci_msi_domain_supports(struct pci_dev *dev, unsigned int feature_mask, enum support_mode mode…
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Daldebaran_ppt.c859 uint32_t feature_mask, in aldebaran_upload_dpm_level() argument
868 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { in aldebaran_upload_dpm_level()
882 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { in aldebaran_upload_dpm_level()
896 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { in aldebaran_upload_dpm_level()
1580 uint32_t feature_mask; member
1606 if (throttler_status & logging_label[throttler_idx].feature_mask) { in aldebaran_log_thermal_throttling_event()
H A Dsmu_v13_0_12_ppt.c205 struct smu_feature_bits *feature_mask) in smu_v13_0_12_get_enabled_mask() argument
209 ret = smu_cmn_get_enabled_mask(smu, feature_mask); in smu_v13_0_12_get_enabled_mask()
212 smu_feature_bits_clearall(feature_mask); in smu_v13_0_12_get_enabled_mask()
/linux/tools/power/x86/turbostat/
H A Dturbostat.c1461 int feature_mask; /* Mask for testing if the counter is supported on host */ member
1476 .feature_mask = RAPL_PKG,
1489 .feature_mask = RAPL_PKG,
1502 .feature_mask = RAPL_AMD_F17H,
1515 .feature_mask = RAPL_AMD_F17H,
1528 .feature_mask = RAPL_CORE_ENERGY_STATUS,
1541 .feature_mask = RAPL_CORE_ENERGY_STATUS,
1554 .feature_mask = RAPL_DRAM,
1567 .feature_mask = RAPL_DRAM,
1580 .feature_mask = RAPL_GFX,
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0.c715 uint32_t feature_mask[2]; in smu_v15_0_set_allowed_mask() local
721 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); in smu_v15_0_set_allowed_mask()
724 feature_mask[1], NULL); in smu_v15_0_set_allowed_mask()
730 feature_mask[0], in smu_v15_0_set_allowed_mask()

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