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Searched refs:feature_mask (Results 1 – 25 of 48) sorted by relevance

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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr.c102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
123 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init()
136 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
170 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
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H A Dvega20_hwmgr.c103 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) in vega20_set_default_registry_data()
106 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) in vega20_set_default_registry_data()
109 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) in vega20_set_default_registry_data()
112 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) in vega20_set_default_registry_data()
115 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK)) in vega20_set_default_registry_data()
118 if (!(hwmgr->feature_mask & PP_ULV_MASK)) in vega20_set_default_registry_data()
121 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)) in vega20_set_default_registry_data()
173 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); in vega20_set_default_registry_data()
1820 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) in vega20_upload_dpm_min_level() argument
1828 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in vega20_upload_dpm_min_level()
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H A Dvega10_hwmgr.c120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
126 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in vega10_set_default_registry_data()
129 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
131 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { in vega10_set_default_registry_data()
138 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; in vega10_set_default_registry_data()
141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data()
144 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; in vega10_set_default_registry_data()
153 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; in vega10_set_default_registry_data()
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/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c675 uint64_t *feature_mask) in smu_cmn_get_enabled_mask() argument
681 if (!feature_mask) in smu_cmn_get_enabled_mask()
684 feature_mask_low = &((uint32_t *)feature_mask)[0]; in smu_cmn_get_enabled_mask()
685 feature_mask_high = &((uint32_t *)feature_mask)[1]; in smu_cmn_get_enabled_mask()
731 uint64_t feature_mask, in smu_cmn_feature_update_enable_state() argument
739 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
745 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
750 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
756 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
798 uint64_t feature_mask; in smu_cmn_get_pp_feature_mask() local
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H A Dsmu_cmn.h85 uint64_t *feature_mask);
92 uint64_t feature_mask,
/linux/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_device.c382 kernel_ulong_t feature_mask) in proc_thermal_mmio_add() argument
386 proc_priv->mmio_feature_mask = feature_mask; in proc_thermal_mmio_add()
388 if (feature_mask) { in proc_thermal_mmio_add()
394 if (feature_mask & PROC_THERMAL_FEATURE_RAPL) { in proc_thermal_mmio_add()
402 if (feature_mask & PROC_THERMAL_FEATURE_FIVR || in proc_thermal_mmio_add()
403 feature_mask & PROC_THERMAL_FEATURE_DVFS || in proc_thermal_mmio_add()
404 feature_mask & PROC_THERMAL_FEATURE_DLVR) { in proc_thermal_mmio_add()
412 if (feature_mask & PROC_THERMAL_FEATURE_WT_REQ) { in proc_thermal_mmio_add()
418 } else if (feature_mask & PROC_THERMAL_FEATURE_WT_HINT) { in proc_thermal_mmio_add()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c269 uint32_t *feature_mask, uint32_t num) in smu_v13_0_7_get_allowed_feature_mask() argument
276 memset(feature_mask, 0, sizeof(uint32_t) * num); in smu_v13_0_7_get_allowed_feature_mask()
278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); in smu_v13_0_7_get_allowed_feature_mask()
281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v13_0_7_get_allowed_feature_mask()
283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); in smu_v13_0_7_get_allowed_feature_mask()
287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_7_get_allowed_feature_mask()
290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); in smu_v13_0_7_get_allowed_feature_mask()
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H A Dsmu_v13_0_0_ppt.c300 uint32_t *feature_mask, uint32_t num) in smu_v13_0_0_get_allowed_feature_mask() argument
307 memset(feature_mask, 0xff, sizeof(uint32_t) * num); in smu_v13_0_0_get_allowed_feature_mask()
310 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
311 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v13_0_0_get_allowed_feature_mask()
316 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); in smu_v13_0_0_get_allowed_feature_mask()
319 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
324 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_0_get_allowed_feature_mask()
327 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
328 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); in smu_v13_0_0_get_allowed_feature_mask()
329 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); in smu_v13_0_0_get_allowed_feature_mask()
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/linux/drivers/mfd/
H A Dkempld-core.c70 pld->feature_mask = kempld_read16(pld, KEMPLD_FEATURE); in kempld_get_info_generic()
72 pld->feature_mask = 0; in kempld_get_info_generic()
100 if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C) in kempld_register_cells_generic()
103 if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG) in kempld_register_cells_generic()
106 if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO) in kempld_register_cells_generic()
109 if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART) in kempld_register_cells_generic()
/linux/drivers/pci/msi/
H A Dirqdomain.c344 bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask, in pci_msi_domain_supports() argument
378 return (supported & feature_mask) == feature_mask; in pci_msi_domain_supports()
H A Dmsi.h109 bool pci_msi_domain_supports(struct pci_dev *dev, unsigned int feature_mask, enum support_mode mode…
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c566 uint64_t *feature_mask) in cyan_skillfish_get_enabled_mask() argument
568 if (!feature_mask) in cyan_skillfish_get_enabled_mask()
570 memset(feature_mask, 0xff, sizeof(*feature_mask)); in cyan_skillfish_get_enabled_mask()
H A Dsienna_cichlid_ppt.c280 uint32_t *feature_mask, uint32_t num) in sienna_cichlid_get_allowed_feature_mask() argument
287 memset(feature_mask, 0, sizeof(uint32_t) * num); in sienna_cichlid_get_allowed_feature_mask()
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) in sienna_cichlid_get_allowed_feature_mask()
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in sienna_cichlid_get_allowed_feature_mask()
312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); in sienna_cichlid_get_allowed_feature_mask()
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); in sienna_cichlid_get_allowed_feature_mask()
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) in sienna_cichlid_get_allowed_feature_mask()
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); in sienna_cichlid_get_allowed_feature_mask()
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); in sienna_cichlid_get_allowed_feature_mask()
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); in sienna_cichlid_get_allowed_feature_mask()
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H A Dnavi10_ppt.c279 uint32_t *feature_mask, uint32_t num) in navi10_get_allowed_feature_mask() argument
286 memset(feature_mask, 0, sizeof(uint32_t) * num); in navi10_get_allowed_feature_mask()
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) in navi10_get_allowed_feature_mask()
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in navi10_get_allowed_feature_mask()
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); in navi10_get_allowed_feature_mask()
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); in navi10_get_allowed_feature_mask()
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); in navi10_get_allowed_feature_mask()
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); in navi10_get_allowed_feature_mask()
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in navi10_get_allowed_feature_mask()
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); in navi10_get_allowed_feature_mask()
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H A Darcturus_ppt.c350 uint32_t *feature_mask, uint32_t num) in arcturus_get_allowed_feature_mask() argument
356 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in arcturus_get_allowed_feature_mask()
949 uint32_t feature_mask, in arcturus_upload_dpm_level() argument
958 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in arcturus_upload_dpm_level()
972 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in arcturus_upload_dpm_level()
986 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { in arcturus_upload_dpm_level()
1823 uint32_t feature_mask; member
1851 if (throttler_status & logging_label[throttler_idx].feature_mask) { in arcturus_log_thermal_throttling_event()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega10_smumgr.h46 bool enable, uint32_t feature_mask);
H A Dvega12_smumgr.h52 bool enable, uint64_t feature_mask);
H A Dvega20_smumgr.h51 bool enable, uint64_t feature_mask);
H A Dvega20_smumgr.c318 bool enable, uint64_t feature_mask) in vega20_enable_smc_features() argument
323 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega20_enable_smc_features()
324 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega20_enable_smc_features()
H A Dvega10_smumgr.c112 bool enable, uint32_t feature_mask) in vega10_enable_smc_features() argument
126 msg, feature_mask, NULL); in vega10_enable_smc_features()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_2_ppt.c268 uint32_t *feature_mask, uint32_t num) in smu_v14_0_2_get_allowed_feature_mask() argument
276 memset(feature_mask, 0xff, sizeof(uint32_t) * num); in smu_v14_0_2_get_allowed_feature_mask()
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v14_0_2_get_allowed_feature_mask()
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v14_0_2_get_allowed_feature_mask()
285 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); in smu_v14_0_2_get_allowed_feature_mask()
288 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); in smu_v14_0_2_get_allowed_feature_mask()
294 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v14_0_2_get_allowed_feature_mask()
297 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v14_0_2_get_allowed_feature_mask()
298 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); in smu_v14_0_2_get_allowed_feature_mask()
299 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); in smu_v14_0_2_get_allowed_feature_mask()
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/linux/net/smc/
H A Dsmc_clc.c461 fce_v2x->feature_mask = htons(ini->feature_mask); in smc_clc_fill_fce_v2x()
940 v2_ext->feature_mask = htons(SMC_FEATURE_MASK); in smc_clc_send_proposal()
1261 ini->feature_mask = SMC_FEATURE_MASK; in smc_clc_srv_v2x_features_validate()
1306 ini->feature_mask = ntohs(fce_v2x->feature_mask) & SMC_FEATURE_MASK; in smc_clc_clnt_v2x_features_validate()
1336 ini->feature_mask = ntohs(fce_v2x->feature_mask); in smc_clc_v2x_features_confirm_check()
H A Dsmc_clc.h143 __be16 feature_mask;
267 __be16 feature_mask; member
/linux/include/sound/sof/
H A Dext_manifest4.h74 uint32_t feature_mask; member
/linux/include/linux/mfd/
H A Dkempld.h91 u32 feature_mask; member

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