1*e098bc96SEvan Quan /* 2*e098bc96SEvan Quan * Copyright 2016 Advanced Micro Devices, Inc. 3*e098bc96SEvan Quan * 4*e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6*e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7*e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10*e098bc96SEvan Quan * 11*e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12*e098bc96SEvan Quan * all copies or substantial portions of the Software. 13*e098bc96SEvan Quan * 14*e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*e098bc96SEvan Quan * 22*e098bc96SEvan Quan */ 23*e098bc96SEvan Quan #ifndef _VEGA10_SMUMANAGER_H_ 24*e098bc96SEvan Quan #define _VEGA10_SMUMANAGER_H_ 25*e098bc96SEvan Quan 26*e098bc96SEvan Quan #define MAX_SMU_TABLE 5 27*e098bc96SEvan Quan 28*e098bc96SEvan Quan struct smu_table_entry { 29*e098bc96SEvan Quan uint32_t version; 30*e098bc96SEvan Quan uint32_t size; 31*e098bc96SEvan Quan uint32_t table_id; 32*e098bc96SEvan Quan uint64_t mc_addr; 33*e098bc96SEvan Quan void *table; 34*e098bc96SEvan Quan struct amdgpu_bo *handle; 35*e098bc96SEvan Quan }; 36*e098bc96SEvan Quan 37*e098bc96SEvan Quan struct smu_table_array { 38*e098bc96SEvan Quan struct smu_table_entry entry[MAX_SMU_TABLE]; 39*e098bc96SEvan Quan }; 40*e098bc96SEvan Quan 41*e098bc96SEvan Quan struct vega10_smumgr { 42*e098bc96SEvan Quan struct smu_table_array smu_tables; 43*e098bc96SEvan Quan }; 44*e098bc96SEvan Quan 45*e098bc96SEvan Quan int vega10_enable_smc_features(struct pp_hwmgr *hwmgr, 46*e098bc96SEvan Quan bool enable, uint32_t feature_mask); 47*e098bc96SEvan Quan int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr, 48*e098bc96SEvan Quan uint64_t *features_enabled); 49*e098bc96SEvan Quan 50*e098bc96SEvan Quan #endif 51*e098bc96SEvan Quan 52