| /linux/drivers/media/platform/ti/vpe/ |
| H A D | vpdma_priv.h | 302 static inline int dtd_get_data_type(struct vpdma_dtd *dtd) in dtd_get_data_type() argument
304 return dtd->type_ctl_stride >> DTD_DATA_TYPE_SHFT; in dtd_get_data_type()
307 static inline bool dtd_get_notify(struct vpdma_dtd *dtd) in dtd_get_notify() argument
309 return (dtd->type_ctl_stride >> DTD_NOTIFY_SHFT) & DTD_NOTIFY_MASK; in dtd_get_notify()
312 static inline int dtd_get_field(struct vpdma_dtd *dtd) in dtd_get_field() argument
314 return (dtd->type_ctl_stride >> DTD_FIELD_SHFT) & DTD_FIELD_MASK; in dtd_get_field()
317 static inline bool dtd_get_1d(struct vpdma_dtd *dtd) in dtd_get_1d() argument
319 return (dtd->type_ctl_stride >> DTD_1D_SHFT) & DTD_1D_MASK; in dtd_get_1d()
322 static inline bool dtd_get_even_line_skip(struct vpdma_dtd *dtd) in dtd_get_even_line_skip() argument
324 return (dtd->type_ctl_stride >> DTD_EVEN_LINE_SKIP_SHFT) in dtd_get_even_line_skip()
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | psb_intel_sdvo.c | 693 struct psb_intel_sdvo_dtd *dtd) in psb_intel_sdvo_set_timing() argument
695 return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && in psb_intel_sdvo_set_timing()
696 psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); in psb_intel_sdvo_set_timing()
700 struct psb_intel_sdvo_dtd *dtd) in psb_intel_sdvo_set_input_timing() argument
703 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); in psb_intel_sdvo_set_input_timing()
707 struct psb_intel_sdvo_dtd *dtd) in psb_intel_sdvo_set_output_timing() argument
710 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); in psb_intel_sdvo_set_output_timing()
738 struct psb_intel_sdvo_dtd *dtd) in psb_intel_sdvo_get_preferred_input_timing() argument
740 BUILD_BUG_ON(sizeof(dtd->part1) != 8); in psb_intel_sdvo_get_preferred_input_timing()
741 BUILD_BUG_ON(sizeof(dtd->part2) != 8); in psb_intel_sdvo_get_preferred_input_timing()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_sdvo.c | 751 struct intel_sdvo_dtd *dtd) in intel_sdvo_set_timing() argument
753 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && in intel_sdvo_set_timing()
754 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); in intel_sdvo_set_timing()
758 struct intel_sdvo_dtd *dtd) in intel_sdvo_get_timing() argument
760 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && in intel_sdvo_get_timing()
761 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); in intel_sdvo_get_timing()
765 struct intel_sdvo_dtd *dtd) in intel_sdvo_set_input_timing() argument
768 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); in intel_sdvo_set_input_timing()
772 struct intel_sdvo_dtd *dtd) in intel_sdvo_set_output_timing() argument
775 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); in intel_sdvo_set_output_timing()
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| H A D | intel_bios.c | 929 const struct generic_dtd_entry *dtd; in parse_generic_dtd() local
968 dtd = &generic_dtd->dtd[panel->vbt.panel_type]; in parse_generic_dtd()
974 panel_fixed_mode->hdisplay = dtd->hactive; in parse_generic_dtd()
976 panel_fixed_mode->hdisplay + dtd->hfront_porch; in parse_generic_dtd()
978 panel_fixed_mode->hsync_start + dtd->hsync; in parse_generic_dtd()
980 panel_fixed_mode->hdisplay + dtd->hblank; in parse_generic_dtd()
982 panel_fixed_mode->vdisplay = dtd->vactive; in parse_generic_dtd()
984 panel_fixed_mode->vdisplay + dtd->vfront_porch; in parse_generic_dtd()
986 panel_fixed_mode->vsync_start + dtd->vsync; in parse_generic_dtd()
988 panel_fixed_mode->vdisplay + dtd->vblank; in parse_generic_dtd()
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| /linux/lib/zstd/decompress/ |
| H A D | huf_decompress.c | 142 DTableDesc dtd; in HUF_getDTableDesc() local
143 ZSTD_memcpy(&dtd, table, sizeof(dtd)); in HUF_getDTableDesc()
144 return dtd; in HUF_getDTableDesc()
402 { DTableDesc dtd = HUF_getDTableDesc(DTable); in HUF_readDTableX1_wksp() local
403 U32 const maxTableLog = dtd.maxTableLog + 1; in HUF_readDTableX1_wksp()
406 …if (tableLog > (U32)(dtd.maxTableLog+1)) return ERROR(tableLog_tooLarge); /* DTable too small, H… in HUF_readDTableX1_wksp()
407 dtd.tableType = 0; in HUF_readDTableX1_wksp()
408 dtd.tableLog = (BYTE)tableLog; in HUF_readDTableX1_wksp()
409 ZSTD_memcpy(DTable, &dtd, sizeof(dtd)); in HUF_readDTableX1_wksp()
582 DTableDesc const dtd = HUF_getDTableDesc(DTable); in HUF_decompress1X1_usingDTable_internal_body() local
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| /linux/drivers/usb/gadget/udc/ |
| H A D | fsl_udc_core.c | 778 struct ep_td_struct *dtd; in fsl_build_dtd() local
784 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma); in fsl_build_dtd()
785 if (dtd == NULL) in fsl_build_dtd()
786 return dtd; in fsl_build_dtd()
788 dtd->td_dma = *dma; in fsl_build_dtd()
790 swap_temp = hc32_to_cpu(dtd->size_ioc_sts); in fsl_build_dtd()
792 dtd->size_ioc_sts = cpu_to_hc32(swap_temp); in fsl_build_dtd()
796 dtd->buff_ptr0 = cpu_to_hc32(swap_temp); in fsl_build_dtd()
797 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000); in fsl_build_dtd()
798 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000); in fsl_build_dtd()
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| /linux/drivers/media/cec/usb/extron-da-hd-4k-plus/ |
| H A D | extron-da-hd-4k-plus.c | 267 const u8 *dtd = edid + 0x36 + i * 18; in extron_parse_edid() local
272 if (!dtd[0] && !dtd[1]) in extron_parse_edid()
274 w = dtd[2] + ((dtd[4] & 0xf0) << 4); in extron_parse_edid()
275 h = dtd[5] + ((dtd[7] & 0xf0) << 4); in extron_parse_edid()
279 w += dtd[3] + ((dtd[4] & 0x0f) << 8); in extron_parse_edid()
280 h += dtd[6] + ((dtd[7] & 0x0f) << 8); in extron_parse_edid()
281 pclk = dtd[0] + (dtd[1] << 8); in extron_parse_edid()
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra20-trimslice.dts | 98 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
205 "dtb", "dtc", "dtd", "gmb", "gme",
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| H A D | tegra20-tamonten.dtsi | 88 nvidia,pins = "dta", "dtd";
213 nvidia,pins = "ddc", "dta", "dtd", "kbca",
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| H A D | tegra20-ventana.dts | 104 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
236 nvidia,pins = "dta", "dtb", "dtc", "dtd";
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| H A D | tegra20-paz00.dts | 101 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
236 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
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| H A D | tegra20-harmony.dts | 106 nvidia,pins = "dta", "dtd";
230 nvidia,pins = "ddc", "dta", "dtd", "kbca",
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| H A D | tegra20-seaboard.dts | 102 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
235 nvidia,pins = "dta", "dtb", "dtc", "dtd";
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| H A D | tegra20-acer-a500-picasso.dts | 145 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
278 nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
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| H A D | tegra20-colibri.dtsi | 263 nvidia,pins = "dtb", "dtc", "dtd";
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| /linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra20.c | 2063 MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
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