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Searched refs:dpm_levels (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c628 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
629 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
662 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
675 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega12_setup_default_dpm_tables()
688 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; in vega12_setup_default_dpm_tables()
701 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; in vega12_setup_default_dpm_tables()
714 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; in vega12_setup_default_dpm_tables()
727 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; in vega12_setup_default_dpm_tables()
740 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; in vega12_setup_default_dpm_tables()
805 dpm_table->dpm_levels[min_level].value;
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H A Dvega20_hwmgr.c586 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
587 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
608 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega20_setup_gfxclk_dpm_table()
629 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; in vega20_setup_memclk_dpm_table()
661 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega20_setup_default_dpm_tables()
688 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; in vega20_setup_default_dpm_tables()
701 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; in vega20_setup_default_dpm_tables()
714 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; in vega20_setup_default_dpm_tables()
727 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; in vega20_setup_default_dpm_tables()
773 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100; in vega20_setup_default_dpm_tables()
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H A Dvega12_hwmgr.h109 struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
H A Dvega10_hwmgr.h136 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
H A Dvega20_hwmgr.h162 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
/linux/drivers/gpu/drm/radeon/
H A Dci_dpm.c2515 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2516 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2574 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()
2592 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
2594 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
3249 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3296 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3299 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3342 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()
3348 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()
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H A Dci_dpm.h65 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c610 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_7_set_default_dpm_table()
611 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
625 (dpm_table->dpm_levels[dpm_table->count - 1].value > in smu_v13_0_7_set_default_dpm_table()
627 dpm_table->dpm_levels[dpm_table->count - 1].value = in smu_v13_0_7_set_default_dpm_table()
632 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v13_0_7_set_default_dpm_table()
633 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
647 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_7_set_default_dpm_table()
648 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
662 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in smu_v13_0_7_set_default_dpm_table()
663 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_7_set_default_dpm_table()
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H A Daldebaran_ppt.h49 struct aldebaran_dpm_level dpm_levels[MAX_DPM_NUMBER]; member
H A Dsmu_v13_0_0_ppt.c582 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_0_set_default_dpm_table()
583 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
606 (dpm_table->dpm_levels[dpm_table->count - 1].value > in smu_v13_0_0_set_default_dpm_table()
608 dpm_table->dpm_levels[dpm_table->count - 1].value = in smu_v13_0_0_set_default_dpm_table()
613 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v13_0_0_set_default_dpm_table()
614 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
628 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_0_set_default_dpm_table()
629 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
643 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in smu_v13_0_0_set_default_dpm_table()
644 dpm_table->dpm_levels[0].enabled = true; in smu_v13_0_0_set_default_dpm_table()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Darcturus_ppt.h49 struct arcturus_dpm_level dpm_levels[MAX_DPM_NUMBER]; member
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c838 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in fiji_populate_smc_link_level()
840 dpm_table->pcie_speed_table.dpm_levels[i].param1); in fiji_populate_smc_link_level()
1024 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1235 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1239 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1316 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1374 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1395 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1535 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
1536 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
H A Dpolaris10_smumgr.c827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
829 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1084 dpm_table->sclk_table.dpm_levels[0].value, in polaris10_populate_all_graphic_levels()
1091 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ? in polaris10_populate_all_graphic_levels()
1224 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1228 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1340 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1501 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1502 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
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H A Diceland_smumgr.c774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1625 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1764 data->dpm_table.mclk_table.dpm_levels[i].value, in iceland_convert_mc_reg_table_to_smc()
H A Dvegam_smumgr.c581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
583 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
1050 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1054 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1290 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1291 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
H A Dtonga_smumgr.c517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1113 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
1501 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
2143 data->dpm_table.mclk_table.dpm_levels[i].value, in tonga_convert_mc_reg_table_to_smc()
H A Dci_smumgr.c488 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
1006 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
1008 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
1316 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1318 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1671 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1672 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1807 data->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()