1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2015 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan *
22e098bc96SEvan Quan */
23e098bc96SEvan Quan #include "pp_debug.h"
24e098bc96SEvan Quan #include <linux/types.h>
25e098bc96SEvan Quan #include <linux/kernel.h>
26e098bc96SEvan Quan #include <linux/pci.h>
27e098bc96SEvan Quan #include <linux/slab.h>
28e098bc96SEvan Quan #include <linux/gfp.h>
29e098bc96SEvan Quan
30e098bc96SEvan Quan #include "smumgr.h"
31e098bc96SEvan Quan #include "tonga_smumgr.h"
32e098bc96SEvan Quan #include "smu_ucode_xfer_vi.h"
33e098bc96SEvan Quan #include "tonga_ppsmc.h"
34e098bc96SEvan Quan #include "smu/smu_7_1_2_d.h"
35e098bc96SEvan Quan #include "smu/smu_7_1_2_sh_mask.h"
36e098bc96SEvan Quan #include "cgs_common.h"
37e098bc96SEvan Quan #include "smu7_smumgr.h"
38e098bc96SEvan Quan
39e098bc96SEvan Quan #include "smu7_dyn_defaults.h"
40e098bc96SEvan Quan
41e098bc96SEvan Quan #include "smu7_hwmgr.h"
42e098bc96SEvan Quan #include "hardwaremanager.h"
43e098bc96SEvan Quan #include "ppatomctrl.h"
44e098bc96SEvan Quan
45e098bc96SEvan Quan #include "atombios.h"
46e098bc96SEvan Quan
47e098bc96SEvan Quan #include "pppcielanes.h"
48e098bc96SEvan Quan #include "pp_endian.h"
49e098bc96SEvan Quan
50e098bc96SEvan Quan #include "gmc/gmc_8_1_d.h"
51e098bc96SEvan Quan #include "gmc/gmc_8_1_sh_mask.h"
52e098bc96SEvan Quan
53e098bc96SEvan Quan #include "bif/bif_5_0_d.h"
54e098bc96SEvan Quan #include "bif/bif_5_0_sh_mask.h"
55e098bc96SEvan Quan
56e098bc96SEvan Quan #include "dce/dce_10_0_d.h"
57e098bc96SEvan Quan #include "dce/dce_10_0_sh_mask.h"
58e098bc96SEvan Quan
59e098bc96SEvan Quan #define POWERTUNE_DEFAULT_SET_MAX 1
60e098bc96SEvan Quan #define MC_CG_ARB_FREQ_F1 0x0b
61e098bc96SEvan Quan #define VDDC_VDDCI_DELTA 200
62e098bc96SEvan Quan
63e098bc96SEvan Quan
64e098bc96SEvan Quan static const struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
65e098bc96SEvan Quan /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
66e098bc96SEvan Quan * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
67e098bc96SEvan Quan */
68e098bc96SEvan Quan {1, 0xF, 0xFD, 0x19,
69e098bc96SEvan Quan 5, 45, 0, 0xB0000,
70e098bc96SEvan Quan {0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8,
71e098bc96SEvan Quan 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
72e098bc96SEvan Quan {0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203,
73e098bc96SEvan Quan 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4}
74e098bc96SEvan Quan },
75e098bc96SEvan Quan };
76e098bc96SEvan Quan
77e098bc96SEvan Quan /* [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
78e098bc96SEvan Quan static const uint16_t tonga_clock_stretcher_lookup_table[2][4] = {
79e098bc96SEvan Quan {600, 1050, 3, 0},
80e098bc96SEvan Quan {600, 1050, 6, 1}
81e098bc96SEvan Quan };
82e098bc96SEvan Quan
83e098bc96SEvan Quan /* [FF, SS] type, [] 4 voltage ranges,
84e098bc96SEvan Quan * and [Floor Freq, Boundary Freq, VID min , VID max]
85e098bc96SEvan Quan */
86e098bc96SEvan Quan static const uint32_t tonga_clock_stretcher_ddt_table[2][4][4] = {
87e098bc96SEvan Quan { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
88e098bc96SEvan Quan { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} }
89e098bc96SEvan Quan };
90e098bc96SEvan Quan
91e098bc96SEvan Quan /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] */
92e098bc96SEvan Quan static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = {
93e098bc96SEvan Quan {0, 1, 3, 2, 4, 5},
94e098bc96SEvan Quan {0, 2, 4, 5, 6, 5}
95e098bc96SEvan Quan };
96e098bc96SEvan Quan
tonga_start_in_protection_mode(struct pp_hwmgr * hwmgr)97e098bc96SEvan Quan static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
98e098bc96SEvan Quan {
99e098bc96SEvan Quan int result;
100e098bc96SEvan Quan
101e098bc96SEvan Quan /* Assert reset */
102e098bc96SEvan Quan PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
103e098bc96SEvan Quan SMC_SYSCON_RESET_CNTL, rst_reg, 1);
104e098bc96SEvan Quan
105e098bc96SEvan Quan result = smu7_upload_smu_firmware_image(hwmgr);
106e098bc96SEvan Quan if (result)
107e098bc96SEvan Quan return result;
108e098bc96SEvan Quan
109e098bc96SEvan Quan /* Clear status */
110e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
111e098bc96SEvan Quan ixSMU_STATUS, 0);
112e098bc96SEvan Quan
113e098bc96SEvan Quan /* Enable clock */
114e098bc96SEvan Quan PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
115e098bc96SEvan Quan SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
116e098bc96SEvan Quan
117e098bc96SEvan Quan /* De-assert reset */
118e098bc96SEvan Quan PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
119e098bc96SEvan Quan SMC_SYSCON_RESET_CNTL, rst_reg, 0);
120e098bc96SEvan Quan
121e098bc96SEvan Quan /* Set SMU Auto Start */
122e098bc96SEvan Quan PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
123e098bc96SEvan Quan SMU_INPUT_DATA, AUTO_START, 1);
124e098bc96SEvan Quan
125e098bc96SEvan Quan /* Clear firmware interrupt enable flag */
126e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
127e098bc96SEvan Quan ixFIRMWARE_FLAGS, 0);
128e098bc96SEvan Quan
129e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
130e098bc96SEvan Quan RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
131e098bc96SEvan Quan
132e098bc96SEvan Quan /**
133e098bc96SEvan Quan * Call Test SMU message with 0x20000 offset to trigger SMU start
134e098bc96SEvan Quan */
135e098bc96SEvan Quan smu7_send_msg_to_smc_offset(hwmgr);
136e098bc96SEvan Quan
137e098bc96SEvan Quan /* Wait for done bit to be set */
138e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
139e098bc96SEvan Quan SMU_STATUS, SMU_DONE, 0);
140e098bc96SEvan Quan
141e098bc96SEvan Quan /* Check pass/failed indicator */
142e098bc96SEvan Quan if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
143e098bc96SEvan Quan CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
144e098bc96SEvan Quan pr_err("SMU Firmware start failed\n");
145e098bc96SEvan Quan return -EINVAL;
146e098bc96SEvan Quan }
147e098bc96SEvan Quan
148e098bc96SEvan Quan /* Wait for firmware to initialize */
149e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
150e098bc96SEvan Quan FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
151e098bc96SEvan Quan
152e098bc96SEvan Quan return 0;
153e098bc96SEvan Quan }
154e098bc96SEvan Quan
tonga_start_in_non_protection_mode(struct pp_hwmgr * hwmgr)155e098bc96SEvan Quan static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
156e098bc96SEvan Quan {
157e098bc96SEvan Quan int result = 0;
158e098bc96SEvan Quan
159e098bc96SEvan Quan /* wait for smc boot up */
160e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
161e098bc96SEvan Quan RCU_UC_EVENTS, boot_seq_done, 0);
162e098bc96SEvan Quan
163e098bc96SEvan Quan /*Clear firmware interrupt enable flag*/
164e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
165e098bc96SEvan Quan ixFIRMWARE_FLAGS, 0);
166e098bc96SEvan Quan
167e098bc96SEvan Quan
168e098bc96SEvan Quan PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
169e098bc96SEvan Quan SMC_SYSCON_RESET_CNTL, rst_reg, 1);
170e098bc96SEvan Quan
171e098bc96SEvan Quan result = smu7_upload_smu_firmware_image(hwmgr);
172e098bc96SEvan Quan
173e098bc96SEvan Quan if (result != 0)
174e098bc96SEvan Quan return result;
175e098bc96SEvan Quan
176e098bc96SEvan Quan /* Set smc instruct start point at 0x0 */
177e098bc96SEvan Quan smu7_program_jump_on_start(hwmgr);
178e098bc96SEvan Quan
179e098bc96SEvan Quan
180e098bc96SEvan Quan PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
181e098bc96SEvan Quan SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
182e098bc96SEvan Quan
183e098bc96SEvan Quan /*De-assert reset*/
184e098bc96SEvan Quan PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
185e098bc96SEvan Quan SMC_SYSCON_RESET_CNTL, rst_reg, 0);
186e098bc96SEvan Quan
187e098bc96SEvan Quan /* Wait for firmware to initialize */
188e098bc96SEvan Quan PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
189e098bc96SEvan Quan FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
190e098bc96SEvan Quan
191e098bc96SEvan Quan return result;
192e098bc96SEvan Quan }
193e098bc96SEvan Quan
tonga_start_smu(struct pp_hwmgr * hwmgr)194e098bc96SEvan Quan static int tonga_start_smu(struct pp_hwmgr *hwmgr)
195e098bc96SEvan Quan {
196e098bc96SEvan Quan struct tonga_smumgr *priv = hwmgr->smu_backend;
197e098bc96SEvan Quan int result;
198e098bc96SEvan Quan
199e098bc96SEvan Quan /* Only start SMC if SMC RAM is not running */
200e098bc96SEvan Quan if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
201e098bc96SEvan Quan /*Check if SMU is running in protected mode*/
202e098bc96SEvan Quan if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
203e098bc96SEvan Quan SMU_FIRMWARE, SMU_MODE)) {
204e098bc96SEvan Quan result = tonga_start_in_non_protection_mode(hwmgr);
205e098bc96SEvan Quan if (result)
206e098bc96SEvan Quan return result;
207e098bc96SEvan Quan } else {
208e098bc96SEvan Quan result = tonga_start_in_protection_mode(hwmgr);
209e098bc96SEvan Quan if (result)
210e098bc96SEvan Quan return result;
211e098bc96SEvan Quan }
212e098bc96SEvan Quan }
213e098bc96SEvan Quan
214e098bc96SEvan Quan /* Setup SoftRegsStart here to visit the register UcodeLoadStatus
215e098bc96SEvan Quan * to check fw loading state
216e098bc96SEvan Quan */
217e098bc96SEvan Quan smu7_read_smc_sram_dword(hwmgr,
218e098bc96SEvan Quan SMU72_FIRMWARE_HEADER_LOCATION +
219e098bc96SEvan Quan offsetof(SMU72_Firmware_Header, SoftRegisters),
220e098bc96SEvan Quan &(priv->smu7_data.soft_regs_start), 0x40000);
221e098bc96SEvan Quan
222e098bc96SEvan Quan result = smu7_request_smu_load_fw(hwmgr);
223e098bc96SEvan Quan
224e098bc96SEvan Quan return result;
225e098bc96SEvan Quan }
226e098bc96SEvan Quan
tonga_smu_init(struct pp_hwmgr * hwmgr)227e098bc96SEvan Quan static int tonga_smu_init(struct pp_hwmgr *hwmgr)
228e098bc96SEvan Quan {
229*6f8e98b9SRuan Jinjie struct tonga_smumgr *tonga_priv;
230e098bc96SEvan Quan
231e098bc96SEvan Quan tonga_priv = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
232e098bc96SEvan Quan if (tonga_priv == NULL)
233e098bc96SEvan Quan return -ENOMEM;
234e098bc96SEvan Quan
235e098bc96SEvan Quan hwmgr->smu_backend = tonga_priv;
236e098bc96SEvan Quan
237e098bc96SEvan Quan if (smu7_init(hwmgr)) {
238e098bc96SEvan Quan kfree(tonga_priv);
239e098bc96SEvan Quan return -EINVAL;
240e098bc96SEvan Quan }
241e098bc96SEvan Quan
242e098bc96SEvan Quan return 0;
243e098bc96SEvan Quan }
244e098bc96SEvan Quan
245e098bc96SEvan Quan
tonga_get_dependency_volt_by_clk(struct pp_hwmgr * hwmgr,phm_ppt_v1_clock_voltage_dependency_table * allowed_clock_voltage_table,uint32_t clock,SMU_VoltageLevel * voltage,uint32_t * mvdd)246e098bc96SEvan Quan static int tonga_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
247e098bc96SEvan Quan phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
248e098bc96SEvan Quan uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
249e098bc96SEvan Quan {
250e098bc96SEvan Quan uint32_t i = 0;
251e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
252e098bc96SEvan Quan struct phm_ppt_v1_information *pptable_info =
253e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
254e098bc96SEvan Quan
255e098bc96SEvan Quan /* clock - voltage dependency table is empty table */
256e098bc96SEvan Quan if (allowed_clock_voltage_table->count == 0)
257e098bc96SEvan Quan return -EINVAL;
258e098bc96SEvan Quan
259e098bc96SEvan Quan for (i = 0; i < allowed_clock_voltage_table->count; i++) {
260e098bc96SEvan Quan /* find first sclk bigger than request */
261e098bc96SEvan Quan if (allowed_clock_voltage_table->entries[i].clk >= clock) {
262e098bc96SEvan Quan voltage->VddGfx = phm_get_voltage_index(
263e098bc96SEvan Quan pptable_info->vddgfx_lookup_table,
264e098bc96SEvan Quan allowed_clock_voltage_table->entries[i].vddgfx);
265e098bc96SEvan Quan voltage->Vddc = phm_get_voltage_index(
266e098bc96SEvan Quan pptable_info->vddc_lookup_table,
267e098bc96SEvan Quan allowed_clock_voltage_table->entries[i].vddc);
268e098bc96SEvan Quan
269e098bc96SEvan Quan if (allowed_clock_voltage_table->entries[i].vddci)
270e098bc96SEvan Quan voltage->Vddci =
271e098bc96SEvan Quan phm_get_voltage_id(&data->vddci_voltage_table, allowed_clock_voltage_table->entries[i].vddci);
272e098bc96SEvan Quan else
273e098bc96SEvan Quan voltage->Vddci =
274e098bc96SEvan Quan phm_get_voltage_id(&data->vddci_voltage_table,
275e098bc96SEvan Quan allowed_clock_voltage_table->entries[i].vddc - VDDC_VDDCI_DELTA);
276e098bc96SEvan Quan
277e098bc96SEvan Quan
278e098bc96SEvan Quan if (allowed_clock_voltage_table->entries[i].mvdd)
279e098bc96SEvan Quan *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
280e098bc96SEvan Quan
281e098bc96SEvan Quan voltage->Phases = 1;
282e098bc96SEvan Quan return 0;
283e098bc96SEvan Quan }
284e098bc96SEvan Quan }
285e098bc96SEvan Quan
286e098bc96SEvan Quan /* sclk is bigger than max sclk in the dependence table */
287e098bc96SEvan Quan voltage->VddGfx = phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
288e098bc96SEvan Quan allowed_clock_voltage_table->entries[i-1].vddgfx);
289e098bc96SEvan Quan voltage->Vddc = phm_get_voltage_index(pptable_info->vddc_lookup_table,
290e098bc96SEvan Quan allowed_clock_voltage_table->entries[i-1].vddc);
291e098bc96SEvan Quan
292e098bc96SEvan Quan if (allowed_clock_voltage_table->entries[i-1].vddci)
293e098bc96SEvan Quan voltage->Vddci = phm_get_voltage_id(&data->vddci_voltage_table,
294e098bc96SEvan Quan allowed_clock_voltage_table->entries[i-1].vddci);
295e098bc96SEvan Quan
296e098bc96SEvan Quan if (allowed_clock_voltage_table->entries[i-1].mvdd)
297e098bc96SEvan Quan *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
298e098bc96SEvan Quan
299e098bc96SEvan Quan return 0;
300e098bc96SEvan Quan }
301e098bc96SEvan Quan
tonga_populate_smc_vddc_table(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)302e098bc96SEvan Quan static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
303e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
304e098bc96SEvan Quan {
305e098bc96SEvan Quan unsigned int count;
306e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
307e098bc96SEvan Quan
308e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
309e098bc96SEvan Quan table->VddcLevelCount = data->vddc_voltage_table.count;
310e098bc96SEvan Quan for (count = 0; count < table->VddcLevelCount; count++) {
311e098bc96SEvan Quan table->VddcTable[count] =
312e098bc96SEvan Quan PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
313e098bc96SEvan Quan }
314e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
315e098bc96SEvan Quan }
316e098bc96SEvan Quan return 0;
317e098bc96SEvan Quan }
318e098bc96SEvan Quan
tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)319e098bc96SEvan Quan static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
320e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
321e098bc96SEvan Quan {
322e098bc96SEvan Quan unsigned int count;
323e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
324e098bc96SEvan Quan
325e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
326e098bc96SEvan Quan table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
327e098bc96SEvan Quan for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
328e098bc96SEvan Quan table->VddGfxTable[count] =
329e098bc96SEvan Quan PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
330e098bc96SEvan Quan }
331e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
332e098bc96SEvan Quan }
333e098bc96SEvan Quan return 0;
334e098bc96SEvan Quan }
335e098bc96SEvan Quan
tonga_populate_smc_vdd_ci_table(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)336e098bc96SEvan Quan static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
337e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
338e098bc96SEvan Quan {
339e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
340e098bc96SEvan Quan uint32_t count;
341e098bc96SEvan Quan
342e098bc96SEvan Quan table->VddciLevelCount = data->vddci_voltage_table.count;
343e098bc96SEvan Quan for (count = 0; count < table->VddciLevelCount; count++) {
344e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
345e098bc96SEvan Quan table->VddciTable[count] =
346e098bc96SEvan Quan PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
347e098bc96SEvan Quan } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
348e098bc96SEvan Quan table->SmioTable1.Pattern[count].Voltage =
349e098bc96SEvan Quan PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
350e098bc96SEvan Quan /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
351e098bc96SEvan Quan table->SmioTable1.Pattern[count].Smio =
352e098bc96SEvan Quan (uint8_t) count;
353e098bc96SEvan Quan table->Smio[count] |=
354e098bc96SEvan Quan data->vddci_voltage_table.entries[count].smio_low;
355e098bc96SEvan Quan table->VddciTable[count] =
356e098bc96SEvan Quan PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
357e098bc96SEvan Quan }
358e098bc96SEvan Quan }
359e098bc96SEvan Quan
360e098bc96SEvan Quan table->SmioMask1 = data->vddci_voltage_table.mask_low;
361e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
362e098bc96SEvan Quan
363e098bc96SEvan Quan return 0;
364e098bc96SEvan Quan }
365e098bc96SEvan Quan
tonga_populate_smc_mvdd_table(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)366e098bc96SEvan Quan static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
367e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
368e098bc96SEvan Quan {
369e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
370e098bc96SEvan Quan uint32_t count;
371e098bc96SEvan Quan
372e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
373e098bc96SEvan Quan table->MvddLevelCount = data->mvdd_voltage_table.count;
374e098bc96SEvan Quan for (count = 0; count < table->MvddLevelCount; count++) {
375e098bc96SEvan Quan table->SmioTable2.Pattern[count].Voltage =
376e098bc96SEvan Quan PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
377e098bc96SEvan Quan /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
378e098bc96SEvan Quan table->SmioTable2.Pattern[count].Smio =
379e098bc96SEvan Quan (uint8_t) count;
380e098bc96SEvan Quan table->Smio[count] |=
381e098bc96SEvan Quan data->mvdd_voltage_table.entries[count].smio_low;
382e098bc96SEvan Quan }
383e098bc96SEvan Quan table->SmioMask2 = data->mvdd_voltage_table.mask_low;
384e098bc96SEvan Quan
385e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
386e098bc96SEvan Quan }
387e098bc96SEvan Quan
388e098bc96SEvan Quan return 0;
389e098bc96SEvan Quan }
390e098bc96SEvan Quan
tonga_populate_cac_tables(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)391e098bc96SEvan Quan static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
392e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
393e098bc96SEvan Quan {
394e098bc96SEvan Quan uint32_t count;
395e098bc96SEvan Quan uint8_t index = 0;
396e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
397e098bc96SEvan Quan struct phm_ppt_v1_information *pptable_info =
398e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
399e098bc96SEvan Quan struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table =
400e098bc96SEvan Quan pptable_info->vddgfx_lookup_table;
401e098bc96SEvan Quan struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table =
402e098bc96SEvan Quan pptable_info->vddc_lookup_table;
403e098bc96SEvan Quan
404e098bc96SEvan Quan /* table is already swapped, so in order to use the value from it
405e098bc96SEvan Quan * we need to swap it back.
406e098bc96SEvan Quan */
407e098bc96SEvan Quan uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
408e098bc96SEvan Quan uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
409e098bc96SEvan Quan
410e098bc96SEvan Quan for (count = 0; count < vddc_level_count; count++) {
411e098bc96SEvan Quan /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
412e098bc96SEvan Quan index = phm_get_voltage_index(vddc_lookup_table,
413e098bc96SEvan Quan data->vddc_voltage_table.entries[count].value);
414e098bc96SEvan Quan table->BapmVddcVidLoSidd[count] =
415e098bc96SEvan Quan convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
416e098bc96SEvan Quan table->BapmVddcVidHiSidd[count] =
417e098bc96SEvan Quan convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
418e098bc96SEvan Quan table->BapmVddcVidHiSidd2[count] =
419e098bc96SEvan Quan convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
420e098bc96SEvan Quan }
421e098bc96SEvan Quan
422e098bc96SEvan Quan if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
423e098bc96SEvan Quan /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
424e098bc96SEvan Quan for (count = 0; count < vddgfx_level_count; count++) {
425e098bc96SEvan Quan index = phm_get_voltage_index(vddgfx_lookup_table,
426e098bc96SEvan Quan convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid));
427e098bc96SEvan Quan table->BapmVddGfxVidHiSidd2[count] =
428e098bc96SEvan Quan convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
429e098bc96SEvan Quan }
430e098bc96SEvan Quan } else {
431e098bc96SEvan Quan for (count = 0; count < vddc_level_count; count++) {
432e098bc96SEvan Quan index = phm_get_voltage_index(vddc_lookup_table,
433e098bc96SEvan Quan data->vddc_voltage_table.entries[count].value);
434e098bc96SEvan Quan table->BapmVddGfxVidLoSidd[count] =
435e098bc96SEvan Quan convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
436e098bc96SEvan Quan table->BapmVddGfxVidHiSidd[count] =
437e098bc96SEvan Quan convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
438e098bc96SEvan Quan table->BapmVddGfxVidHiSidd2[count] =
439e098bc96SEvan Quan convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
440e098bc96SEvan Quan }
441e098bc96SEvan Quan }
442e098bc96SEvan Quan
443e098bc96SEvan Quan return 0;
444e098bc96SEvan Quan }
445e098bc96SEvan Quan
tonga_populate_smc_voltage_tables(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)446e098bc96SEvan Quan static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
447e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
448e098bc96SEvan Quan {
449e098bc96SEvan Quan int result;
450e098bc96SEvan Quan
451e098bc96SEvan Quan result = tonga_populate_smc_vddc_table(hwmgr, table);
452e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
453e098bc96SEvan Quan "can not populate VDDC voltage table to SMC",
454e098bc96SEvan Quan return -EINVAL);
455e098bc96SEvan Quan
456e098bc96SEvan Quan result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
457e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
458e098bc96SEvan Quan "can not populate VDDCI voltage table to SMC",
459e098bc96SEvan Quan return -EINVAL);
460e098bc96SEvan Quan
461e098bc96SEvan Quan result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
462e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
463e098bc96SEvan Quan "can not populate VDDGFX voltage table to SMC",
464e098bc96SEvan Quan return -EINVAL);
465e098bc96SEvan Quan
466e098bc96SEvan Quan result = tonga_populate_smc_mvdd_table(hwmgr, table);
467e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
468e098bc96SEvan Quan "can not populate MVDD voltage table to SMC",
469e098bc96SEvan Quan return -EINVAL);
470e098bc96SEvan Quan
471e098bc96SEvan Quan result = tonga_populate_cac_tables(hwmgr, table);
472e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
473e098bc96SEvan Quan "can not populate CAC voltage tables to SMC",
474e098bc96SEvan Quan return -EINVAL);
475e098bc96SEvan Quan
476e098bc96SEvan Quan return 0;
477e098bc96SEvan Quan }
478e098bc96SEvan Quan
tonga_populate_ulv_level(struct pp_hwmgr * hwmgr,struct SMU72_Discrete_Ulv * state)479e098bc96SEvan Quan static int tonga_populate_ulv_level(struct pp_hwmgr *hwmgr,
480e098bc96SEvan Quan struct SMU72_Discrete_Ulv *state)
481e098bc96SEvan Quan {
482e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
483e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
484e098bc96SEvan Quan
485e098bc96SEvan Quan state->CcPwrDynRm = 0;
486e098bc96SEvan Quan state->CcPwrDynRm1 = 0;
487e098bc96SEvan Quan
488e098bc96SEvan Quan state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
489e098bc96SEvan Quan state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
490e098bc96SEvan Quan VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
491e098bc96SEvan Quan
492e098bc96SEvan Quan state->VddcPhase = 1;
493e098bc96SEvan Quan
494e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
495e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
496e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
497e098bc96SEvan Quan
498e098bc96SEvan Quan return 0;
499e098bc96SEvan Quan }
500e098bc96SEvan Quan
tonga_populate_ulv_state(struct pp_hwmgr * hwmgr,struct SMU72_Discrete_DpmTable * table)501e098bc96SEvan Quan static int tonga_populate_ulv_state(struct pp_hwmgr *hwmgr,
502e098bc96SEvan Quan struct SMU72_Discrete_DpmTable *table)
503e098bc96SEvan Quan {
504e098bc96SEvan Quan return tonga_populate_ulv_level(hwmgr, &table->Ulv);
505e098bc96SEvan Quan }
506e098bc96SEvan Quan
tonga_populate_smc_link_level(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)507e098bc96SEvan Quan static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
508e098bc96SEvan Quan {
509e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
510e098bc96SEvan Quan struct smu7_dpm_table *dpm_table = &data->dpm_table;
511e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
512e098bc96SEvan Quan uint32_t i;
513e098bc96SEvan Quan
514e098bc96SEvan Quan /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
515e098bc96SEvan Quan for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
516e098bc96SEvan Quan table->LinkLevel[i].PcieGenSpeed =
517e098bc96SEvan Quan (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
518e098bc96SEvan Quan table->LinkLevel[i].PcieLaneCount =
519e098bc96SEvan Quan (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
520e098bc96SEvan Quan table->LinkLevel[i].EnabledForActivity =
521e098bc96SEvan Quan 1;
522e098bc96SEvan Quan table->LinkLevel[i].SPC =
523e098bc96SEvan Quan (uint8_t)(data->pcie_spc_cap & 0xff);
524e098bc96SEvan Quan table->LinkLevel[i].DownThreshold =
525e098bc96SEvan Quan PP_HOST_TO_SMC_UL(5);
526e098bc96SEvan Quan table->LinkLevel[i].UpThreshold =
527e098bc96SEvan Quan PP_HOST_TO_SMC_UL(30);
528e098bc96SEvan Quan }
529e098bc96SEvan Quan
530e098bc96SEvan Quan smu_data->smc_state_table.LinkLevelCount =
531e098bc96SEvan Quan (uint8_t)dpm_table->pcie_speed_table.count;
532e098bc96SEvan Quan data->dpm_level_enable_mask.pcie_dpm_enable_mask =
533e098bc96SEvan Quan phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
534e098bc96SEvan Quan
535e098bc96SEvan Quan return 0;
536e098bc96SEvan Quan }
537e098bc96SEvan Quan
tonga_calculate_sclk_params(struct pp_hwmgr * hwmgr,uint32_t engine_clock,SMU72_Discrete_GraphicsLevel * sclk)538e098bc96SEvan Quan static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
539e098bc96SEvan Quan uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
540e098bc96SEvan Quan {
541e098bc96SEvan Quan const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
542e098bc96SEvan Quan pp_atomctrl_clock_dividers_vi dividers;
543e098bc96SEvan Quan uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
544e098bc96SEvan Quan uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
545e098bc96SEvan Quan uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
546e098bc96SEvan Quan uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
547e098bc96SEvan Quan uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
548e098bc96SEvan Quan uint32_t reference_clock;
549e098bc96SEvan Quan uint32_t reference_divider;
550e098bc96SEvan Quan uint32_t fbdiv;
551e098bc96SEvan Quan int result;
552e098bc96SEvan Quan
553e098bc96SEvan Quan /* get the engine clock dividers for this clock value*/
554e098bc96SEvan Quan result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
555e098bc96SEvan Quan
556e098bc96SEvan Quan PP_ASSERT_WITH_CODE(result == 0,
557e098bc96SEvan Quan "Error retrieving Engine Clock dividers from VBIOS.", return result);
558e098bc96SEvan Quan
559e098bc96SEvan Quan /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
560e098bc96SEvan Quan reference_clock = atomctrl_get_reference_clock(hwmgr);
561e098bc96SEvan Quan
562e098bc96SEvan Quan reference_divider = 1 + dividers.uc_pll_ref_div;
563e098bc96SEvan Quan
564e098bc96SEvan Quan /* low 14 bits is fraction and high 12 bits is divider*/
565e098bc96SEvan Quan fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
566e098bc96SEvan Quan
567e098bc96SEvan Quan /* SPLL_FUNC_CNTL setup*/
568e098bc96SEvan Quan spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
569e098bc96SEvan Quan CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
570e098bc96SEvan Quan spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
571e098bc96SEvan Quan CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
572e098bc96SEvan Quan
573e098bc96SEvan Quan /* SPLL_FUNC_CNTL_3 setup*/
574e098bc96SEvan Quan spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
575e098bc96SEvan Quan CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
576e098bc96SEvan Quan
577e098bc96SEvan Quan /* set to use fractional accumulation*/
578e098bc96SEvan Quan spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
579e098bc96SEvan Quan CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
580e098bc96SEvan Quan
581e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
582e098bc96SEvan Quan PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
583e098bc96SEvan Quan pp_atomctrl_internal_ss_info ss_info;
584e098bc96SEvan Quan
585e098bc96SEvan Quan uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
586e098bc96SEvan Quan if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
587e098bc96SEvan Quan /*
588e098bc96SEvan Quan * ss_info.speed_spectrum_percentage -- in unit of 0.01%
589e098bc96SEvan Quan * ss_info.speed_spectrum_rate -- in unit of khz
590e098bc96SEvan Quan */
591e098bc96SEvan Quan /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
592e098bc96SEvan Quan uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
593e098bc96SEvan Quan
594e098bc96SEvan Quan /* clkv = 2 * D * fbdiv / NS */
595e098bc96SEvan Quan uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
596e098bc96SEvan Quan
597e098bc96SEvan Quan cg_spll_spread_spectrum =
598e098bc96SEvan Quan PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
599e098bc96SEvan Quan cg_spll_spread_spectrum =
600e098bc96SEvan Quan PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
601e098bc96SEvan Quan cg_spll_spread_spectrum_2 =
602e098bc96SEvan Quan PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
603e098bc96SEvan Quan }
604e098bc96SEvan Quan }
605e098bc96SEvan Quan
606e098bc96SEvan Quan sclk->SclkFrequency = engine_clock;
607e098bc96SEvan Quan sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
608e098bc96SEvan Quan sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
609e098bc96SEvan Quan sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
610e098bc96SEvan Quan sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
611e098bc96SEvan Quan sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
612e098bc96SEvan Quan
613e098bc96SEvan Quan return 0;
614e098bc96SEvan Quan }
615e098bc96SEvan Quan
tonga_populate_single_graphic_level(struct pp_hwmgr * hwmgr,uint32_t engine_clock,SMU72_Discrete_GraphicsLevel * graphic_level)616e098bc96SEvan Quan static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
617e098bc96SEvan Quan uint32_t engine_clock,
618e098bc96SEvan Quan SMU72_Discrete_GraphicsLevel *graphic_level)
619e098bc96SEvan Quan {
620e098bc96SEvan Quan int result;
621e098bc96SEvan Quan uint32_t mvdd;
622e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
623e098bc96SEvan Quan struct phm_ppt_v1_information *pptable_info =
624e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
625e098bc96SEvan Quan phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
626e098bc96SEvan Quan
627e098bc96SEvan Quan result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
628e098bc96SEvan Quan
629e098bc96SEvan Quan if (hwmgr->od_enabled)
630e098bc96SEvan Quan vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
631e098bc96SEvan Quan else
632e098bc96SEvan Quan vdd_dep_table = pptable_info->vdd_dep_on_sclk;
633e098bc96SEvan Quan
634e098bc96SEvan Quan /* populate graphics levels*/
635e098bc96SEvan Quan result = tonga_get_dependency_volt_by_clk(hwmgr,
636e098bc96SEvan Quan vdd_dep_table, engine_clock,
637e098bc96SEvan Quan &graphic_level->MinVoltage, &mvdd);
638e098bc96SEvan Quan PP_ASSERT_WITH_CODE((!result),
639e098bc96SEvan Quan "can not find VDDC voltage value for VDDC "
640e098bc96SEvan Quan "engine clock dependency table", return result);
641e098bc96SEvan Quan
642e098bc96SEvan Quan /* SCLK frequency in units of 10KHz*/
643e098bc96SEvan Quan graphic_level->SclkFrequency = engine_clock;
644e098bc96SEvan Quan /* Indicates maximum activity level for this performance level. 50% for now*/
645e098bc96SEvan Quan graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity;
646e098bc96SEvan Quan
647e098bc96SEvan Quan graphic_level->CcPwrDynRm = 0;
648e098bc96SEvan Quan graphic_level->CcPwrDynRm1 = 0;
649e098bc96SEvan Quan /* this level can be used if activity is high enough.*/
650e098bc96SEvan Quan graphic_level->EnabledForActivity = 0;
651e098bc96SEvan Quan /* this level can be used for throttling.*/
652e098bc96SEvan Quan graphic_level->EnabledForThrottle = 1;
653e098bc96SEvan Quan graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst;
654e098bc96SEvan Quan graphic_level->DownHyst = data->current_profile_setting.sclk_down_hyst;
655e098bc96SEvan Quan graphic_level->VoltageDownHyst = 0;
656e098bc96SEvan Quan graphic_level->PowerThrottle = 0;
657e098bc96SEvan Quan
658e098bc96SEvan Quan data->display_timing.min_clock_in_sr =
659e098bc96SEvan Quan hwmgr->display_config->min_core_set_clock_in_sr;
660e098bc96SEvan Quan
661e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
662e098bc96SEvan Quan PHM_PlatformCaps_SclkDeepSleep))
663e098bc96SEvan Quan graphic_level->DeepSleepDivId =
664e098bc96SEvan Quan smu7_get_sleep_divider_id_from_clock(engine_clock,
665e098bc96SEvan Quan data->display_timing.min_clock_in_sr);
666e098bc96SEvan Quan
667e098bc96SEvan Quan /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
668e098bc96SEvan Quan graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
669e098bc96SEvan Quan
670e098bc96SEvan Quan if (!result) {
671e098bc96SEvan Quan /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
672e098bc96SEvan Quan /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
673e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
674e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
675e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
676e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
677e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
678e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
679e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
680e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
681e098bc96SEvan Quan }
682e098bc96SEvan Quan
683e098bc96SEvan Quan return result;
684e098bc96SEvan Quan }
685e098bc96SEvan Quan
tonga_populate_all_graphic_levels(struct pp_hwmgr * hwmgr)686e098bc96SEvan Quan static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
687e098bc96SEvan Quan {
688e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
689e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
690e098bc96SEvan Quan struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
691e098bc96SEvan Quan struct smu7_dpm_table *dpm_table = &data->dpm_table;
692e098bc96SEvan Quan struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
693e098bc96SEvan Quan uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
694e098bc96SEvan Quan uint32_t level_array_address = smu_data->smu7_data.dpm_table_start +
695e098bc96SEvan Quan offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
696e098bc96SEvan Quan
697e098bc96SEvan Quan uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
698e098bc96SEvan Quan SMU72_MAX_LEVELS_GRAPHICS;
699e098bc96SEvan Quan
700e098bc96SEvan Quan SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
701e098bc96SEvan Quan
702e098bc96SEvan Quan uint32_t i, max_entry;
703e098bc96SEvan Quan uint8_t highest_pcie_level_enabled = 0;
704e098bc96SEvan Quan uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
705e098bc96SEvan Quan uint8_t count = 0;
706e098bc96SEvan Quan int result = 0;
707e098bc96SEvan Quan
708e098bc96SEvan Quan memset(levels, 0x00, level_array_size);
709e098bc96SEvan Quan
710e098bc96SEvan Quan for (i = 0; i < dpm_table->sclk_table.count; i++) {
711e098bc96SEvan Quan result = tonga_populate_single_graphic_level(hwmgr,
712e098bc96SEvan Quan dpm_table->sclk_table.dpm_levels[i].value,
713e098bc96SEvan Quan &(smu_data->smc_state_table.GraphicsLevel[i]));
714e098bc96SEvan Quan if (result != 0)
715e098bc96SEvan Quan return result;
716e098bc96SEvan Quan
717e098bc96SEvan Quan /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
718e098bc96SEvan Quan if (i > 1)
719e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
720e098bc96SEvan Quan }
721e098bc96SEvan Quan
722e098bc96SEvan Quan /* Only enable level 0 for now. */
723e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
724e098bc96SEvan Quan
725e098bc96SEvan Quan /* set highest level watermark to high */
726e098bc96SEvan Quan if (dpm_table->sclk_table.count > 1)
727e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
728e098bc96SEvan Quan PPSMC_DISPLAY_WATERMARK_HIGH;
729e098bc96SEvan Quan
730e098bc96SEvan Quan smu_data->smc_state_table.GraphicsDpmLevelCount =
731e098bc96SEvan Quan (uint8_t)dpm_table->sclk_table.count;
732e098bc96SEvan Quan data->dpm_level_enable_mask.sclk_dpm_enable_mask =
733e098bc96SEvan Quan phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
734e098bc96SEvan Quan
735e098bc96SEvan Quan if (pcie_table != NULL) {
736e098bc96SEvan Quan PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
737e098bc96SEvan Quan "There must be 1 or more PCIE levels defined in PPTable.",
738e098bc96SEvan Quan return -EINVAL);
739e098bc96SEvan Quan max_entry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
740e098bc96SEvan Quan for (i = 0; i < dpm_table->sclk_table.count; i++) {
741e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
742e098bc96SEvan Quan (uint8_t) ((i < max_entry) ? i : max_entry);
743e098bc96SEvan Quan }
744e098bc96SEvan Quan } else {
745e098bc96SEvan Quan if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
746e098bc96SEvan Quan pr_err("Pcie Dpm Enablemask is 0 !");
747e098bc96SEvan Quan
748e098bc96SEvan Quan while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
749e098bc96SEvan Quan ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
750e098bc96SEvan Quan (1<<(highest_pcie_level_enabled+1))) != 0)) {
751e098bc96SEvan Quan highest_pcie_level_enabled++;
752e098bc96SEvan Quan }
753e098bc96SEvan Quan
754e098bc96SEvan Quan while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
755e098bc96SEvan Quan ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
756e098bc96SEvan Quan (1<<lowest_pcie_level_enabled)) == 0)) {
757e098bc96SEvan Quan lowest_pcie_level_enabled++;
758e098bc96SEvan Quan }
759e098bc96SEvan Quan
760e098bc96SEvan Quan while ((count < highest_pcie_level_enabled) &&
761e098bc96SEvan Quan ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
762e098bc96SEvan Quan (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
763e098bc96SEvan Quan count++;
764e098bc96SEvan Quan }
765e098bc96SEvan Quan mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
766e098bc96SEvan Quan (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
767e098bc96SEvan Quan
768e098bc96SEvan Quan
769e098bc96SEvan Quan /* set pcieDpmLevel to highest_pcie_level_enabled*/
770e098bc96SEvan Quan for (i = 2; i < dpm_table->sclk_table.count; i++)
771e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
772e098bc96SEvan Quan
773e098bc96SEvan Quan /* set pcieDpmLevel to lowest_pcie_level_enabled*/
774e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
775e098bc96SEvan Quan
776e098bc96SEvan Quan /* set pcieDpmLevel to mid_pcie_level_enabled*/
777e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
778e098bc96SEvan Quan }
779e098bc96SEvan Quan /* level count will send to smc once at init smc table and never change*/
780e098bc96SEvan Quan result = smu7_copy_bytes_to_smc(hwmgr, level_array_address,
781e098bc96SEvan Quan (uint8_t *)levels, (uint32_t)level_array_size,
782e098bc96SEvan Quan SMC_RAM_END);
783e098bc96SEvan Quan
784e098bc96SEvan Quan return result;
785e098bc96SEvan Quan }
786e098bc96SEvan Quan
tonga_calculate_mclk_params(struct pp_hwmgr * hwmgr,uint32_t memory_clock,SMU72_Discrete_MemoryLevel * mclk,bool strobe_mode,bool dllStateOn)787e098bc96SEvan Quan static int tonga_calculate_mclk_params(
788e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
789e098bc96SEvan Quan uint32_t memory_clock,
790e098bc96SEvan Quan SMU72_Discrete_MemoryLevel *mclk,
791e098bc96SEvan Quan bool strobe_mode,
792e098bc96SEvan Quan bool dllStateOn
793e098bc96SEvan Quan )
794e098bc96SEvan Quan {
795e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
796e098bc96SEvan Quan
797e098bc96SEvan Quan uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
798e098bc96SEvan Quan uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
799e098bc96SEvan Quan uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
800e098bc96SEvan Quan uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
801e098bc96SEvan Quan uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
802e098bc96SEvan Quan uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
803e098bc96SEvan Quan uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
804e098bc96SEvan Quan uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
805e098bc96SEvan Quan uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
806e098bc96SEvan Quan
807e098bc96SEvan Quan pp_atomctrl_memory_clock_param mpll_param;
808e098bc96SEvan Quan int result;
809e098bc96SEvan Quan
810e098bc96SEvan Quan result = atomctrl_get_memory_pll_dividers_si(hwmgr,
811e098bc96SEvan Quan memory_clock, &mpll_param, strobe_mode);
812e098bc96SEvan Quan PP_ASSERT_WITH_CODE(
813e098bc96SEvan Quan !result,
814e098bc96SEvan Quan "Error retrieving Memory Clock Parameters from VBIOS.",
815e098bc96SEvan Quan return result);
816e098bc96SEvan Quan
817e098bc96SEvan Quan /* MPLL_FUNC_CNTL setup*/
818e098bc96SEvan Quan mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL,
819e098bc96SEvan Quan mpll_param.bw_ctrl);
820e098bc96SEvan Quan
821e098bc96SEvan Quan /* MPLL_FUNC_CNTL_1 setup*/
822e098bc96SEvan Quan mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
823e098bc96SEvan Quan MPLL_FUNC_CNTL_1, CLKF,
824e098bc96SEvan Quan mpll_param.mpll_fb_divider.cl_kf);
825e098bc96SEvan Quan mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
826e098bc96SEvan Quan MPLL_FUNC_CNTL_1, CLKFRAC,
827e098bc96SEvan Quan mpll_param.mpll_fb_divider.clk_frac);
828e098bc96SEvan Quan mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
829e098bc96SEvan Quan MPLL_FUNC_CNTL_1, VCO_MODE,
830e098bc96SEvan Quan mpll_param.vco_mode);
831e098bc96SEvan Quan
832e098bc96SEvan Quan /* MPLL_AD_FUNC_CNTL setup*/
833e098bc96SEvan Quan mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
834e098bc96SEvan Quan MPLL_AD_FUNC_CNTL, YCLK_POST_DIV,
835e098bc96SEvan Quan mpll_param.mpll_post_divider);
836e098bc96SEvan Quan
837e098bc96SEvan Quan if (data->is_memory_gddr5) {
838e098bc96SEvan Quan /* MPLL_DQ_FUNC_CNTL setup*/
839e098bc96SEvan Quan mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
840e098bc96SEvan Quan MPLL_DQ_FUNC_CNTL, YCLK_SEL,
841e098bc96SEvan Quan mpll_param.yclk_sel);
842e098bc96SEvan Quan mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
843e098bc96SEvan Quan MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV,
844e098bc96SEvan Quan mpll_param.mpll_post_divider);
845e098bc96SEvan Quan }
846e098bc96SEvan Quan
847e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
848e098bc96SEvan Quan PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
849e098bc96SEvan Quan /*
850e098bc96SEvan Quan ************************************
851e098bc96SEvan Quan Fref = Reference Frequency
852e098bc96SEvan Quan NF = Feedback divider ratio
853e098bc96SEvan Quan NR = Reference divider ratio
854e098bc96SEvan Quan Fnom = Nominal VCO output frequency = Fref * NF / NR
855e098bc96SEvan Quan Fs = Spreading Rate
856e098bc96SEvan Quan D = Percentage down-spread / 2
857e098bc96SEvan Quan Fint = Reference input frequency to PFD = Fref / NR
858e098bc96SEvan Quan NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
859e098bc96SEvan Quan CLKS = NS - 1 = ISS_STEP_NUM[11:0]
860e098bc96SEvan Quan NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
861e098bc96SEvan Quan CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
862e098bc96SEvan Quan *************************************
863e098bc96SEvan Quan */
864e098bc96SEvan Quan pp_atomctrl_internal_ss_info ss_info;
865e098bc96SEvan Quan uint32_t freq_nom;
866e098bc96SEvan Quan uint32_t tmp;
867e098bc96SEvan Quan uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
868e098bc96SEvan Quan
869e098bc96SEvan Quan /* for GDDR5 for all modes and DDR3 */
870e098bc96SEvan Quan if (1 == mpll_param.qdr)
871e098bc96SEvan Quan freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
872e098bc96SEvan Quan else
873e098bc96SEvan Quan freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
874e098bc96SEvan Quan
875e098bc96SEvan Quan /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
876e098bc96SEvan Quan tmp = (freq_nom / reference_clock);
877e098bc96SEvan Quan tmp = tmp * tmp;
878e098bc96SEvan Quan
879e098bc96SEvan Quan if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
880e098bc96SEvan Quan /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
881e098bc96SEvan Quan /* ss.Info.speed_spectrum_rate -- in unit of khz */
882e098bc96SEvan Quan /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
883e098bc96SEvan Quan /* = reference_clock * 5 / speed_spectrum_rate */
884e098bc96SEvan Quan uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
885e098bc96SEvan Quan
886e098bc96SEvan Quan /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
887e098bc96SEvan Quan /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
888e098bc96SEvan Quan uint32_t clkv =
889e098bc96SEvan Quan (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
890e098bc96SEvan Quan ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
891e098bc96SEvan Quan
892e098bc96SEvan Quan mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
893e098bc96SEvan Quan mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
894e098bc96SEvan Quan }
895e098bc96SEvan Quan }
896e098bc96SEvan Quan
897e098bc96SEvan Quan /* MCLK_PWRMGT_CNTL setup */
898e098bc96SEvan Quan mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
899e098bc96SEvan Quan MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
900e098bc96SEvan Quan mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
901e098bc96SEvan Quan MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
902e098bc96SEvan Quan mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
903e098bc96SEvan Quan MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
904e098bc96SEvan Quan
905e098bc96SEvan Quan /* Save the result data to outpupt memory level structure */
906e098bc96SEvan Quan mclk->MclkFrequency = memory_clock;
907e098bc96SEvan Quan mclk->MpllFuncCntl = mpll_func_cntl;
908e098bc96SEvan Quan mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
909e098bc96SEvan Quan mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
910e098bc96SEvan Quan mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
911e098bc96SEvan Quan mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
912e098bc96SEvan Quan mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
913e098bc96SEvan Quan mclk->DllCntl = dll_cntl;
914e098bc96SEvan Quan mclk->MpllSs1 = mpll_ss1;
915e098bc96SEvan Quan mclk->MpllSs2 = mpll_ss2;
916e098bc96SEvan Quan
917e098bc96SEvan Quan return 0;
918e098bc96SEvan Quan }
919e098bc96SEvan Quan
tonga_get_mclk_frequency_ratio(uint32_t memory_clock,bool strobe_mode)920e098bc96SEvan Quan static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
921e098bc96SEvan Quan bool strobe_mode)
922e098bc96SEvan Quan {
923e098bc96SEvan Quan uint8_t mc_para_index;
924e098bc96SEvan Quan
925e098bc96SEvan Quan if (strobe_mode) {
926e098bc96SEvan Quan if (memory_clock < 12500)
927e098bc96SEvan Quan mc_para_index = 0x00;
928e098bc96SEvan Quan else if (memory_clock > 47500)
929e098bc96SEvan Quan mc_para_index = 0x0f;
930e098bc96SEvan Quan else
931e098bc96SEvan Quan mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
932e098bc96SEvan Quan } else {
933e098bc96SEvan Quan if (memory_clock < 65000)
934e098bc96SEvan Quan mc_para_index = 0x00;
935e098bc96SEvan Quan else if (memory_clock > 135000)
936e098bc96SEvan Quan mc_para_index = 0x0f;
937e098bc96SEvan Quan else
938e098bc96SEvan Quan mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
939e098bc96SEvan Quan }
940e098bc96SEvan Quan
941e098bc96SEvan Quan return mc_para_index;
942e098bc96SEvan Quan }
943e098bc96SEvan Quan
tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)944e098bc96SEvan Quan static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
945e098bc96SEvan Quan {
946e098bc96SEvan Quan uint8_t mc_para_index;
947e098bc96SEvan Quan
948e098bc96SEvan Quan if (memory_clock < 10000)
949e098bc96SEvan Quan mc_para_index = 0;
950e098bc96SEvan Quan else if (memory_clock >= 80000)
951e098bc96SEvan Quan mc_para_index = 0x0f;
952e098bc96SEvan Quan else
953e098bc96SEvan Quan mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
954e098bc96SEvan Quan
955e098bc96SEvan Quan return mc_para_index;
956e098bc96SEvan Quan }
957e098bc96SEvan Quan
958e098bc96SEvan Quan
tonga_populate_single_memory_level(struct pp_hwmgr * hwmgr,uint32_t memory_clock,SMU72_Discrete_MemoryLevel * memory_level)959e098bc96SEvan Quan static int tonga_populate_single_memory_level(
960e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
961e098bc96SEvan Quan uint32_t memory_clock,
962e098bc96SEvan Quan SMU72_Discrete_MemoryLevel *memory_level
963e098bc96SEvan Quan )
964e098bc96SEvan Quan {
965e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
966e098bc96SEvan Quan struct phm_ppt_v1_information *pptable_info =
967e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
968e098bc96SEvan Quan uint32_t mclk_edc_wr_enable_threshold = 40000;
969e098bc96SEvan Quan uint32_t mclk_stutter_mode_threshold = 30000;
970e098bc96SEvan Quan uint32_t mclk_edc_enable_threshold = 40000;
971e098bc96SEvan Quan uint32_t mclk_strobe_mode_threshold = 40000;
972e098bc96SEvan Quan phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
973e098bc96SEvan Quan int result = 0;
974e098bc96SEvan Quan bool dll_state_on;
975e098bc96SEvan Quan uint32_t mvdd = 0;
976e098bc96SEvan Quan
977e098bc96SEvan Quan if (hwmgr->od_enabled)
978e098bc96SEvan Quan vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
979e098bc96SEvan Quan else
980e098bc96SEvan Quan vdd_dep_table = pptable_info->vdd_dep_on_mclk;
981e098bc96SEvan Quan
982e098bc96SEvan Quan if (NULL != vdd_dep_table) {
983e098bc96SEvan Quan result = tonga_get_dependency_volt_by_clk(hwmgr,
984e098bc96SEvan Quan vdd_dep_table,
985e098bc96SEvan Quan memory_clock,
986e098bc96SEvan Quan &memory_level->MinVoltage, &mvdd);
987e098bc96SEvan Quan PP_ASSERT_WITH_CODE(
988e098bc96SEvan Quan !result,
989e098bc96SEvan Quan "can not find MinVddc voltage value from memory VDDC "
990e098bc96SEvan Quan "voltage dependency table",
991e098bc96SEvan Quan return result);
992e098bc96SEvan Quan }
993e098bc96SEvan Quan
994e098bc96SEvan Quan if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
995e098bc96SEvan Quan memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
996e098bc96SEvan Quan else
997e098bc96SEvan Quan memory_level->MinMvdd = mvdd;
998e098bc96SEvan Quan
999e098bc96SEvan Quan memory_level->EnabledForThrottle = 1;
1000e098bc96SEvan Quan memory_level->EnabledForActivity = 0;
1001e098bc96SEvan Quan memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1002e098bc96SEvan Quan memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1003e098bc96SEvan Quan memory_level->VoltageDownHyst = 0;
1004e098bc96SEvan Quan
1005e098bc96SEvan Quan /* Indicates maximum activity level for this performance level.*/
1006e098bc96SEvan Quan memory_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1007e098bc96SEvan Quan memory_level->StutterEnable = 0;
1008e098bc96SEvan Quan memory_level->StrobeEnable = 0;
1009e098bc96SEvan Quan memory_level->EdcReadEnable = 0;
1010e098bc96SEvan Quan memory_level->EdcWriteEnable = 0;
1011e098bc96SEvan Quan memory_level->RttEnable = 0;
1012e098bc96SEvan Quan
1013e098bc96SEvan Quan /* default set to low watermark. Highest level will be set to high later.*/
1014e098bc96SEvan Quan memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1015e098bc96SEvan Quan
1016e098bc96SEvan Quan data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1017e098bc96SEvan Quan data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1018e098bc96SEvan Quan
1019e098bc96SEvan Quan if ((mclk_stutter_mode_threshold != 0) &&
1020e098bc96SEvan Quan (memory_clock <= mclk_stutter_mode_threshold) &&
1021e098bc96SEvan Quan (!data->is_uvd_enabled)
1022e098bc96SEvan Quan && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
1023e098bc96SEvan Quan && (data->display_timing.num_existing_displays <= 2)
1024e098bc96SEvan Quan && (data->display_timing.num_existing_displays != 0))
1025e098bc96SEvan Quan memory_level->StutterEnable = 1;
1026e098bc96SEvan Quan
1027e098bc96SEvan Quan /* decide strobe mode*/
1028e098bc96SEvan Quan memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
1029e098bc96SEvan Quan (memory_clock <= mclk_strobe_mode_threshold);
1030e098bc96SEvan Quan
1031e098bc96SEvan Quan /* decide EDC mode and memory clock ratio*/
1032e098bc96SEvan Quan if (data->is_memory_gddr5) {
1033e098bc96SEvan Quan memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
1034e098bc96SEvan Quan memory_level->StrobeEnable);
1035e098bc96SEvan Quan
1036e098bc96SEvan Quan if ((mclk_edc_enable_threshold != 0) &&
1037e098bc96SEvan Quan (memory_clock > mclk_edc_enable_threshold)) {
1038e098bc96SEvan Quan memory_level->EdcReadEnable = 1;
1039e098bc96SEvan Quan }
1040e098bc96SEvan Quan
1041e098bc96SEvan Quan if ((mclk_edc_wr_enable_threshold != 0) &&
1042e098bc96SEvan Quan (memory_clock > mclk_edc_wr_enable_threshold)) {
1043e098bc96SEvan Quan memory_level->EdcWriteEnable = 1;
1044e098bc96SEvan Quan }
1045e098bc96SEvan Quan
1046e098bc96SEvan Quan if (memory_level->StrobeEnable) {
1047e098bc96SEvan Quan if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
1048e098bc96SEvan Quan ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
1049e098bc96SEvan Quan dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1050e098bc96SEvan Quan } else {
1051e098bc96SEvan Quan dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
1052e098bc96SEvan Quan }
1053e098bc96SEvan Quan
1054e098bc96SEvan Quan } else {
1055e098bc96SEvan Quan dll_state_on = data->dll_default_on;
1056e098bc96SEvan Quan }
1057e098bc96SEvan Quan } else {
1058e098bc96SEvan Quan memory_level->StrobeRatio =
1059e098bc96SEvan Quan tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
1060e098bc96SEvan Quan dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1061e098bc96SEvan Quan }
1062e098bc96SEvan Quan
1063e098bc96SEvan Quan result = tonga_calculate_mclk_params(hwmgr,
1064e098bc96SEvan Quan memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
1065e098bc96SEvan Quan
1066e098bc96SEvan Quan if (!result) {
1067e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
1068e098bc96SEvan Quan /* MCLK frequency in units of 10KHz*/
1069e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
1070e098bc96SEvan Quan /* Indicates maximum activity level for this performance level.*/
1071e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
1072e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
1073e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
1074e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
1075e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
1076e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
1077e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
1078e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
1079e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
1080e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
1081e098bc96SEvan Quan }
1082e098bc96SEvan Quan
1083e098bc96SEvan Quan return result;
1084e098bc96SEvan Quan }
1085e098bc96SEvan Quan
tonga_populate_all_memory_levels(struct pp_hwmgr * hwmgr)1086e098bc96SEvan Quan static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1087e098bc96SEvan Quan {
1088e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1089e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1090e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1091e098bc96SEvan Quan struct smu7_dpm_table *dpm_table = &data->dpm_table;
1092e098bc96SEvan Quan int result;
1093e098bc96SEvan Quan
1094e098bc96SEvan Quan /* populate MCLK dpm table to SMU7 */
1095e098bc96SEvan Quan uint32_t level_array_address =
1096e098bc96SEvan Quan smu_data->smu7_data.dpm_table_start +
1097e098bc96SEvan Quan offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
1098e098bc96SEvan Quan uint32_t level_array_size =
1099e098bc96SEvan Quan sizeof(SMU72_Discrete_MemoryLevel) *
1100e098bc96SEvan Quan SMU72_MAX_LEVELS_MEMORY;
1101e098bc96SEvan Quan SMU72_Discrete_MemoryLevel *levels =
1102e098bc96SEvan Quan smu_data->smc_state_table.MemoryLevel;
1103e098bc96SEvan Quan uint32_t i;
1104e098bc96SEvan Quan
1105e098bc96SEvan Quan memset(levels, 0x00, level_array_size);
1106e098bc96SEvan Quan
1107e098bc96SEvan Quan for (i = 0; i < dpm_table->mclk_table.count; i++) {
1108e098bc96SEvan Quan PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1109e098bc96SEvan Quan "can not populate memory level as memory clock is zero",
1110e098bc96SEvan Quan return -EINVAL);
1111e098bc96SEvan Quan result = tonga_populate_single_memory_level(
1112e098bc96SEvan Quan hwmgr,
1113e098bc96SEvan Quan dpm_table->mclk_table.dpm_levels[i].value,
1114e098bc96SEvan Quan &(smu_data->smc_state_table.MemoryLevel[i]));
1115e098bc96SEvan Quan if (result)
1116e098bc96SEvan Quan return result;
1117e098bc96SEvan Quan }
1118e098bc96SEvan Quan
1119e098bc96SEvan Quan /* Only enable level 0 for now.*/
1120e098bc96SEvan Quan smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1121e098bc96SEvan Quan
1122e098bc96SEvan Quan /*
1123e098bc96SEvan Quan * in order to prevent MC activity from stutter mode to push DPM up.
1124e098bc96SEvan Quan * the UVD change complements this by putting the MCLK in a higher state
1125e098bc96SEvan Quan * by default such that we are not effected by up threshold or and MCLK DPM latency.
1126e098bc96SEvan Quan */
1127e098bc96SEvan Quan smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1128e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1129e098bc96SEvan Quan
1130e098bc96SEvan Quan smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1131e098bc96SEvan Quan data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1132e098bc96SEvan Quan /* set highest level watermark to high*/
1133e098bc96SEvan Quan smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1134e098bc96SEvan Quan
1135e098bc96SEvan Quan /* level count will send to smc once at init smc table and never change*/
1136e098bc96SEvan Quan result = smu7_copy_bytes_to_smc(hwmgr,
1137e098bc96SEvan Quan level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
1138e098bc96SEvan Quan SMC_RAM_END);
1139e098bc96SEvan Quan
1140e098bc96SEvan Quan return result;
1141e098bc96SEvan Quan }
1142e098bc96SEvan Quan
tonga_populate_mvdd_value(struct pp_hwmgr * hwmgr,uint32_t mclk,SMIO_Pattern * smio_pattern)1143e098bc96SEvan Quan static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1144e098bc96SEvan Quan uint32_t mclk, SMIO_Pattern *smio_pattern)
1145e098bc96SEvan Quan {
1146e098bc96SEvan Quan const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1147e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
1148e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
1149e098bc96SEvan Quan uint32_t i = 0;
1150e098bc96SEvan Quan
1151e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1152e098bc96SEvan Quan /* find mvdd value which clock is more than request */
1153e098bc96SEvan Quan for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1154e098bc96SEvan Quan if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1155e098bc96SEvan Quan /* Always round to higher voltage. */
1156e098bc96SEvan Quan smio_pattern->Voltage =
1157e098bc96SEvan Quan data->mvdd_voltage_table.entries[i].value;
1158e098bc96SEvan Quan break;
1159e098bc96SEvan Quan }
1160e098bc96SEvan Quan }
1161e098bc96SEvan Quan
1162e098bc96SEvan Quan PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1163e098bc96SEvan Quan "MVDD Voltage is outside the supported range.",
1164e098bc96SEvan Quan return -EINVAL);
1165e098bc96SEvan Quan } else {
1166e098bc96SEvan Quan return -EINVAL;
1167e098bc96SEvan Quan }
1168e098bc96SEvan Quan
1169e098bc96SEvan Quan return 0;
1170e098bc96SEvan Quan }
1171e098bc96SEvan Quan
1172e098bc96SEvan Quan
tonga_populate_smc_acpi_level(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)1173e098bc96SEvan Quan static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1174e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
1175e098bc96SEvan Quan {
1176e098bc96SEvan Quan int result = 0;
1177e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1178e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1179e098bc96SEvan Quan const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1180e098bc96SEvan Quan struct pp_atomctrl_clock_dividers_vi dividers;
1181e098bc96SEvan Quan
1182e098bc96SEvan Quan SMIO_Pattern voltage_level;
1183e098bc96SEvan Quan uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1184e098bc96SEvan Quan uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1185e098bc96SEvan Quan uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1186e098bc96SEvan Quan uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1187e098bc96SEvan Quan
1188e098bc96SEvan Quan /* The ACPI state should not do DPM on DC (or ever).*/
1189e098bc96SEvan Quan table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1190e098bc96SEvan Quan
1191e098bc96SEvan Quan table->ACPILevel.MinVoltage =
1192e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[0].MinVoltage;
1193e098bc96SEvan Quan
1194e098bc96SEvan Quan /* assign zero for now*/
1195e098bc96SEvan Quan table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1196e098bc96SEvan Quan
1197e098bc96SEvan Quan /* get the engine clock dividers for this clock value*/
1198e098bc96SEvan Quan result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1199e098bc96SEvan Quan table->ACPILevel.SclkFrequency, ÷rs);
1200e098bc96SEvan Quan
1201e098bc96SEvan Quan PP_ASSERT_WITH_CODE(result == 0,
1202e098bc96SEvan Quan "Error retrieving Engine Clock dividers from VBIOS.",
1203e098bc96SEvan Quan return result);
1204e098bc96SEvan Quan
1205e098bc96SEvan Quan /* divider ID for required SCLK*/
1206e098bc96SEvan Quan table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1207e098bc96SEvan Quan table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1208e098bc96SEvan Quan table->ACPILevel.DeepSleepDivId = 0;
1209e098bc96SEvan Quan
1210e098bc96SEvan Quan spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1211e098bc96SEvan Quan SPLL_PWRON, 0);
1212e098bc96SEvan Quan spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1213e098bc96SEvan Quan SPLL_RESET, 1);
1214e098bc96SEvan Quan spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
1215e098bc96SEvan Quan SCLK_MUX_SEL, 4);
1216e098bc96SEvan Quan
1217e098bc96SEvan Quan table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1218e098bc96SEvan Quan table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1219e098bc96SEvan Quan table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1220e098bc96SEvan Quan table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1221e098bc96SEvan Quan table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1222e098bc96SEvan Quan table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1223e098bc96SEvan Quan table->ACPILevel.CcPwrDynRm = 0;
1224e098bc96SEvan Quan table->ACPILevel.CcPwrDynRm1 = 0;
1225e098bc96SEvan Quan
1226e098bc96SEvan Quan
1227e098bc96SEvan Quan /* For various features to be enabled/disabled while this level is active.*/
1228e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1229e098bc96SEvan Quan /* SCLK frequency in units of 10KHz*/
1230e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1231e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1232e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1233e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1234e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1235e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1236e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1237e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1238e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1239e098bc96SEvan Quan
1240e098bc96SEvan Quan /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1241e098bc96SEvan Quan table->MemoryACPILevel.MinVoltage =
1242e098bc96SEvan Quan smu_data->smc_state_table.MemoryLevel[0].MinVoltage;
1243e098bc96SEvan Quan
1244e098bc96SEvan Quan /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
1245e098bc96SEvan Quan
1246e098bc96SEvan Quan if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
1247e098bc96SEvan Quan table->MemoryACPILevel.MinMvdd =
1248e098bc96SEvan Quan PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
1249e098bc96SEvan Quan else
1250e098bc96SEvan Quan table->MemoryACPILevel.MinMvdd = 0;
1251e098bc96SEvan Quan
1252e098bc96SEvan Quan /* Force reset on DLL*/
1253e098bc96SEvan Quan mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1254e098bc96SEvan Quan MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1255e098bc96SEvan Quan mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1256e098bc96SEvan Quan MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1257e098bc96SEvan Quan
1258e098bc96SEvan Quan /* Disable DLL in ACPIState*/
1259e098bc96SEvan Quan mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1260e098bc96SEvan Quan MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1261e098bc96SEvan Quan mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1262e098bc96SEvan Quan MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
1263e098bc96SEvan Quan
1264e098bc96SEvan Quan /* Enable DLL bypass signal*/
1265e098bc96SEvan Quan dll_cntl = PHM_SET_FIELD(dll_cntl,
1266e098bc96SEvan Quan DLL_CNTL, MRDCK0_BYPASS, 0);
1267e098bc96SEvan Quan dll_cntl = PHM_SET_FIELD(dll_cntl,
1268e098bc96SEvan Quan DLL_CNTL, MRDCK1_BYPASS, 0);
1269e098bc96SEvan Quan
1270e098bc96SEvan Quan table->MemoryACPILevel.DllCntl =
1271e098bc96SEvan Quan PP_HOST_TO_SMC_UL(dll_cntl);
1272e098bc96SEvan Quan table->MemoryACPILevel.MclkPwrmgtCntl =
1273e098bc96SEvan Quan PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
1274e098bc96SEvan Quan table->MemoryACPILevel.MpllAdFuncCntl =
1275e098bc96SEvan Quan PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
1276e098bc96SEvan Quan table->MemoryACPILevel.MpllDqFuncCntl =
1277e098bc96SEvan Quan PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
1278e098bc96SEvan Quan table->MemoryACPILevel.MpllFuncCntl =
1279e098bc96SEvan Quan PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
1280e098bc96SEvan Quan table->MemoryACPILevel.MpllFuncCntl_1 =
1281e098bc96SEvan Quan PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
1282e098bc96SEvan Quan table->MemoryACPILevel.MpllFuncCntl_2 =
1283e098bc96SEvan Quan PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
1284e098bc96SEvan Quan table->MemoryACPILevel.MpllSs1 =
1285e098bc96SEvan Quan PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
1286e098bc96SEvan Quan table->MemoryACPILevel.MpllSs2 =
1287e098bc96SEvan Quan PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
1288e098bc96SEvan Quan
1289e098bc96SEvan Quan table->MemoryACPILevel.EnabledForThrottle = 0;
1290e098bc96SEvan Quan table->MemoryACPILevel.EnabledForActivity = 0;
1291e098bc96SEvan Quan table->MemoryACPILevel.UpHyst = 0;
1292e098bc96SEvan Quan table->MemoryACPILevel.DownHyst = 100;
1293e098bc96SEvan Quan table->MemoryACPILevel.VoltageDownHyst = 0;
1294e098bc96SEvan Quan /* Indicates maximum activity level for this performance level.*/
1295e098bc96SEvan Quan table->MemoryACPILevel.ActivityLevel =
1296e098bc96SEvan Quan PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1297e098bc96SEvan Quan
1298e098bc96SEvan Quan table->MemoryACPILevel.StutterEnable = 0;
1299e098bc96SEvan Quan table->MemoryACPILevel.StrobeEnable = 0;
1300e098bc96SEvan Quan table->MemoryACPILevel.EdcReadEnable = 0;
1301e098bc96SEvan Quan table->MemoryACPILevel.EdcWriteEnable = 0;
1302e098bc96SEvan Quan table->MemoryACPILevel.RttEnable = 0;
1303e098bc96SEvan Quan
1304e098bc96SEvan Quan return result;
1305e098bc96SEvan Quan }
1306e098bc96SEvan Quan
tonga_populate_smc_uvd_level(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)1307e098bc96SEvan Quan static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1308e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
1309e098bc96SEvan Quan {
1310e098bc96SEvan Quan int result = 0;
1311e098bc96SEvan Quan
1312e098bc96SEvan Quan uint8_t count;
1313e098bc96SEvan Quan pp_atomctrl_clock_dividers_vi dividers;
1314e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1315e098bc96SEvan Quan struct phm_ppt_v1_information *pptable_info =
1316e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
1317e098bc96SEvan Quan phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1318e098bc96SEvan Quan pptable_info->mm_dep_table;
1319e098bc96SEvan Quan
1320e098bc96SEvan Quan table->UvdLevelCount = (uint8_t) (mm_table->count);
1321e098bc96SEvan Quan table->UvdBootLevel = 0;
1322e098bc96SEvan Quan
1323e098bc96SEvan Quan for (count = 0; count < table->UvdLevelCount; count++) {
1324e098bc96SEvan Quan table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1325e098bc96SEvan Quan table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1326e098bc96SEvan Quan table->UvdLevel[count].MinVoltage.Vddc =
1327e098bc96SEvan Quan phm_get_voltage_index(pptable_info->vddc_lookup_table,
1328e098bc96SEvan Quan mm_table->entries[count].vddc);
1329e098bc96SEvan Quan table->UvdLevel[count].MinVoltage.VddGfx =
1330e098bc96SEvan Quan (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
1331e098bc96SEvan Quan phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
1332e098bc96SEvan Quan mm_table->entries[count].vddgfx) : 0;
1333e098bc96SEvan Quan table->UvdLevel[count].MinVoltage.Vddci =
1334e098bc96SEvan Quan phm_get_voltage_id(&data->vddci_voltage_table,
1335e098bc96SEvan Quan mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1336e098bc96SEvan Quan table->UvdLevel[count].MinVoltage.Phases = 1;
1337e098bc96SEvan Quan
1338e098bc96SEvan Quan /* retrieve divider value for VBIOS */
1339e098bc96SEvan Quan result = atomctrl_get_dfs_pll_dividers_vi(
1340e098bc96SEvan Quan hwmgr,
1341e098bc96SEvan Quan table->UvdLevel[count].VclkFrequency,
1342e098bc96SEvan Quan ÷rs);
1343e098bc96SEvan Quan
1344e098bc96SEvan Quan PP_ASSERT_WITH_CODE((!result),
1345e098bc96SEvan Quan "can not find divide id for Vclk clock",
1346e098bc96SEvan Quan return result);
1347e098bc96SEvan Quan
1348e098bc96SEvan Quan table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1349e098bc96SEvan Quan
1350e098bc96SEvan Quan result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1351e098bc96SEvan Quan table->UvdLevel[count].DclkFrequency, ÷rs);
1352e098bc96SEvan Quan PP_ASSERT_WITH_CODE((!result),
1353e098bc96SEvan Quan "can not find divide id for Dclk clock",
1354e098bc96SEvan Quan return result);
1355e098bc96SEvan Quan
1356e098bc96SEvan Quan table->UvdLevel[count].DclkDivider =
1357e098bc96SEvan Quan (uint8_t)dividers.pll_post_divider;
1358e098bc96SEvan Quan
1359e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1360e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1361e098bc96SEvan Quan }
1362e098bc96SEvan Quan
1363e098bc96SEvan Quan return result;
1364e098bc96SEvan Quan
1365e098bc96SEvan Quan }
1366e098bc96SEvan Quan
tonga_populate_smc_vce_level(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)1367e098bc96SEvan Quan static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1368e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
1369e098bc96SEvan Quan {
1370e098bc96SEvan Quan int result = 0;
1371e098bc96SEvan Quan
1372e098bc96SEvan Quan uint8_t count;
1373e098bc96SEvan Quan pp_atomctrl_clock_dividers_vi dividers;
1374e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1375e098bc96SEvan Quan struct phm_ppt_v1_information *pptable_info =
1376e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
1377e098bc96SEvan Quan phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1378e098bc96SEvan Quan pptable_info->mm_dep_table;
1379e098bc96SEvan Quan
1380e098bc96SEvan Quan table->VceLevelCount = (uint8_t) (mm_table->count);
1381e098bc96SEvan Quan table->VceBootLevel = 0;
1382e098bc96SEvan Quan
1383e098bc96SEvan Quan for (count = 0; count < table->VceLevelCount; count++) {
1384e098bc96SEvan Quan table->VceLevel[count].Frequency =
1385e098bc96SEvan Quan mm_table->entries[count].eclk;
1386e098bc96SEvan Quan table->VceLevel[count].MinVoltage.Vddc =
1387e098bc96SEvan Quan phm_get_voltage_index(pptable_info->vddc_lookup_table,
1388e098bc96SEvan Quan mm_table->entries[count].vddc);
1389e098bc96SEvan Quan table->VceLevel[count].MinVoltage.VddGfx =
1390e098bc96SEvan Quan (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
1391e098bc96SEvan Quan phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
1392e098bc96SEvan Quan mm_table->entries[count].vddgfx) : 0;
1393e098bc96SEvan Quan table->VceLevel[count].MinVoltage.Vddci =
1394e098bc96SEvan Quan phm_get_voltage_id(&data->vddci_voltage_table,
1395e098bc96SEvan Quan mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1396e098bc96SEvan Quan table->VceLevel[count].MinVoltage.Phases = 1;
1397e098bc96SEvan Quan
1398e098bc96SEvan Quan /* retrieve divider value for VBIOS */
1399e098bc96SEvan Quan result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1400e098bc96SEvan Quan table->VceLevel[count].Frequency, ÷rs);
1401e098bc96SEvan Quan PP_ASSERT_WITH_CODE((!result),
1402e098bc96SEvan Quan "can not find divide id for VCE engine clock",
1403e098bc96SEvan Quan return result);
1404e098bc96SEvan Quan
1405e098bc96SEvan Quan table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1406e098bc96SEvan Quan
1407e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1408e098bc96SEvan Quan }
1409e098bc96SEvan Quan
1410e098bc96SEvan Quan return result;
1411e098bc96SEvan Quan }
1412e098bc96SEvan Quan
tonga_populate_smc_acp_level(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)1413e098bc96SEvan Quan static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1414e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
1415e098bc96SEvan Quan {
1416e098bc96SEvan Quan int result = 0;
1417e098bc96SEvan Quan uint8_t count;
1418e098bc96SEvan Quan pp_atomctrl_clock_dividers_vi dividers;
1419e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1420e098bc96SEvan Quan struct phm_ppt_v1_information *pptable_info =
1421e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
1422e098bc96SEvan Quan phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1423e098bc96SEvan Quan pptable_info->mm_dep_table;
1424e098bc96SEvan Quan
1425e098bc96SEvan Quan table->AcpLevelCount = (uint8_t) (mm_table->count);
1426e098bc96SEvan Quan table->AcpBootLevel = 0;
1427e098bc96SEvan Quan
1428e098bc96SEvan Quan for (count = 0; count < table->AcpLevelCount; count++) {
1429e098bc96SEvan Quan table->AcpLevel[count].Frequency =
1430e098bc96SEvan Quan pptable_info->mm_dep_table->entries[count].aclk;
1431e098bc96SEvan Quan table->AcpLevel[count].MinVoltage.Vddc =
1432e098bc96SEvan Quan phm_get_voltage_index(pptable_info->vddc_lookup_table,
1433e098bc96SEvan Quan mm_table->entries[count].vddc);
1434e098bc96SEvan Quan table->AcpLevel[count].MinVoltage.VddGfx =
1435e098bc96SEvan Quan (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
1436e098bc96SEvan Quan phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
1437e098bc96SEvan Quan mm_table->entries[count].vddgfx) : 0;
1438e098bc96SEvan Quan table->AcpLevel[count].MinVoltage.Vddci =
1439e098bc96SEvan Quan phm_get_voltage_id(&data->vddci_voltage_table,
1440e098bc96SEvan Quan mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1441e098bc96SEvan Quan table->AcpLevel[count].MinVoltage.Phases = 1;
1442e098bc96SEvan Quan
1443e098bc96SEvan Quan /* retrieve divider value for VBIOS */
1444e098bc96SEvan Quan result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1445e098bc96SEvan Quan table->AcpLevel[count].Frequency, ÷rs);
1446e098bc96SEvan Quan PP_ASSERT_WITH_CODE((!result),
1447e098bc96SEvan Quan "can not find divide id for engine clock", return result);
1448e098bc96SEvan Quan
1449e098bc96SEvan Quan table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1450e098bc96SEvan Quan
1451e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1452e098bc96SEvan Quan }
1453e098bc96SEvan Quan
1454e098bc96SEvan Quan return result;
1455e098bc96SEvan Quan }
1456e098bc96SEvan Quan
tonga_populate_memory_timing_parameters(struct pp_hwmgr * hwmgr,uint32_t engine_clock,uint32_t memory_clock,struct SMU72_Discrete_MCArbDramTimingTableEntry * arb_regs)1457e098bc96SEvan Quan static int tonga_populate_memory_timing_parameters(
1458e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
1459e098bc96SEvan Quan uint32_t engine_clock,
1460e098bc96SEvan Quan uint32_t memory_clock,
1461e098bc96SEvan Quan struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1462e098bc96SEvan Quan )
1463e098bc96SEvan Quan {
1464e098bc96SEvan Quan uint32_t dramTiming;
1465e098bc96SEvan Quan uint32_t dramTiming2;
1466e098bc96SEvan Quan uint32_t burstTime;
1467e098bc96SEvan Quan int result;
1468e098bc96SEvan Quan
1469e098bc96SEvan Quan result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1470e098bc96SEvan Quan engine_clock, memory_clock);
1471e098bc96SEvan Quan
1472e098bc96SEvan Quan PP_ASSERT_WITH_CODE(result == 0,
1473e098bc96SEvan Quan "Error calling VBIOS to set DRAM_TIMING.", return result);
1474e098bc96SEvan Quan
1475e098bc96SEvan Quan dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1476e098bc96SEvan Quan dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1477e098bc96SEvan Quan burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1478e098bc96SEvan Quan
1479e098bc96SEvan Quan arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1480e098bc96SEvan Quan arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1481e098bc96SEvan Quan arb_regs->McArbBurstTime = (uint8_t)burstTime;
1482e098bc96SEvan Quan
1483e098bc96SEvan Quan return 0;
1484e098bc96SEvan Quan }
1485e098bc96SEvan Quan
tonga_program_memory_timing_parameters(struct pp_hwmgr * hwmgr)1486e098bc96SEvan Quan static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1487e098bc96SEvan Quan {
1488e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1489e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1490e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1491e098bc96SEvan Quan int result = 0;
1492e098bc96SEvan Quan SMU72_Discrete_MCArbDramTimingTable arb_regs;
1493e098bc96SEvan Quan uint32_t i, j;
1494e098bc96SEvan Quan
1495e098bc96SEvan Quan memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1496e098bc96SEvan Quan
1497e098bc96SEvan Quan for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1498e098bc96SEvan Quan for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1499e098bc96SEvan Quan result = tonga_populate_memory_timing_parameters
1500e098bc96SEvan Quan (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1501e098bc96SEvan Quan data->dpm_table.mclk_table.dpm_levels[j].value,
1502e098bc96SEvan Quan &arb_regs.entries[i][j]);
1503e098bc96SEvan Quan
1504e098bc96SEvan Quan if (result)
1505e098bc96SEvan Quan break;
1506e098bc96SEvan Quan }
1507e098bc96SEvan Quan }
1508e098bc96SEvan Quan
1509e098bc96SEvan Quan if (!result) {
1510e098bc96SEvan Quan result = smu7_copy_bytes_to_smc(
1511e098bc96SEvan Quan hwmgr,
1512e098bc96SEvan Quan smu_data->smu7_data.arb_table_start,
1513e098bc96SEvan Quan (uint8_t *)&arb_regs,
1514e098bc96SEvan Quan sizeof(SMU72_Discrete_MCArbDramTimingTable),
1515e098bc96SEvan Quan SMC_RAM_END
1516e098bc96SEvan Quan );
1517e098bc96SEvan Quan }
1518e098bc96SEvan Quan
1519e098bc96SEvan Quan return result;
1520e098bc96SEvan Quan }
1521e098bc96SEvan Quan
tonga_populate_smc_boot_level(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)1522e098bc96SEvan Quan static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1523e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
1524e098bc96SEvan Quan {
1525e098bc96SEvan Quan int result = 0;
1526e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1527e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1528e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1529e098bc96SEvan Quan table->GraphicsBootLevel = 0;
1530e098bc96SEvan Quan table->MemoryBootLevel = 0;
1531e098bc96SEvan Quan
1532e098bc96SEvan Quan /* find boot level from dpm table*/
1533e098bc96SEvan Quan result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1534e098bc96SEvan Quan data->vbios_boot_state.sclk_bootup_value,
1535e098bc96SEvan Quan (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
1536e098bc96SEvan Quan
1537e098bc96SEvan Quan if (result != 0) {
1538e098bc96SEvan Quan smu_data->smc_state_table.GraphicsBootLevel = 0;
1539e098bc96SEvan Quan pr_err("[powerplay] VBIOS did not find boot engine "
1540e098bc96SEvan Quan "clock value in dependency table. "
1541e098bc96SEvan Quan "Using Graphics DPM level 0 !");
1542e098bc96SEvan Quan result = 0;
1543e098bc96SEvan Quan }
1544e098bc96SEvan Quan
1545e098bc96SEvan Quan result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1546e098bc96SEvan Quan data->vbios_boot_state.mclk_bootup_value,
1547e098bc96SEvan Quan (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
1548e098bc96SEvan Quan
1549e098bc96SEvan Quan if (result != 0) {
1550e098bc96SEvan Quan smu_data->smc_state_table.MemoryBootLevel = 0;
1551e098bc96SEvan Quan pr_err("[powerplay] VBIOS did not find boot "
1552e098bc96SEvan Quan "engine clock value in dependency table."
1553e098bc96SEvan Quan "Using Memory DPM level 0 !");
1554e098bc96SEvan Quan result = 0;
1555e098bc96SEvan Quan }
1556e098bc96SEvan Quan
1557e098bc96SEvan Quan table->BootVoltage.Vddc =
1558e098bc96SEvan Quan phm_get_voltage_id(&(data->vddc_voltage_table),
1559e098bc96SEvan Quan data->vbios_boot_state.vddc_bootup_value);
1560e098bc96SEvan Quan table->BootVoltage.VddGfx =
1561e098bc96SEvan Quan phm_get_voltage_id(&(data->vddgfx_voltage_table),
1562e098bc96SEvan Quan data->vbios_boot_state.vddgfx_bootup_value);
1563e098bc96SEvan Quan table->BootVoltage.Vddci =
1564e098bc96SEvan Quan phm_get_voltage_id(&(data->vddci_voltage_table),
1565e098bc96SEvan Quan data->vbios_boot_state.vddci_bootup_value);
1566e098bc96SEvan Quan table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1567e098bc96SEvan Quan
1568e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1569e098bc96SEvan Quan
1570e098bc96SEvan Quan return result;
1571e098bc96SEvan Quan }
1572e098bc96SEvan Quan
tonga_populate_clock_stretcher_data_table(struct pp_hwmgr * hwmgr)1573e098bc96SEvan Quan static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1574e098bc96SEvan Quan {
1575e098bc96SEvan Quan uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1576e098bc96SEvan Quan volt_with_cks, value;
1577e098bc96SEvan Quan uint16_t clock_freq_u16;
1578e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1579e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1580e098bc96SEvan Quan uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1581e098bc96SEvan Quan volt_offset = 0;
1582e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
1583e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
1584e098bc96SEvan Quan struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1585e098bc96SEvan Quan table_info->vdd_dep_on_sclk;
1586e098bc96SEvan Quan uint32_t hw_revision, dev_id;
1587e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
1588e098bc96SEvan Quan
1589e098bc96SEvan Quan stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1590e098bc96SEvan Quan
1591e098bc96SEvan Quan hw_revision = adev->pdev->revision;
1592e098bc96SEvan Quan dev_id = adev->pdev->device;
1593e098bc96SEvan Quan
1594e098bc96SEvan Quan /* Read SMU_Eefuse to read and calculate RO and determine
1595e098bc96SEvan Quan * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1596e098bc96SEvan Quan */
1597e098bc96SEvan Quan efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1598e098bc96SEvan Quan ixSMU_EFUSE_0 + (146 * 4));
1599e098bc96SEvan Quan efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1600e098bc96SEvan Quan ixSMU_EFUSE_0 + (148 * 4));
1601e098bc96SEvan Quan efuse &= 0xFF000000;
1602e098bc96SEvan Quan efuse = efuse >> 24;
1603e098bc96SEvan Quan efuse2 &= 0xF;
1604e098bc96SEvan Quan
1605e098bc96SEvan Quan if (efuse2 == 1)
1606e098bc96SEvan Quan ro = (2300 - 1350) * efuse / 255 + 1350;
1607e098bc96SEvan Quan else
1608e098bc96SEvan Quan ro = (2500 - 1000) * efuse / 255 + 1000;
1609e098bc96SEvan Quan
1610e098bc96SEvan Quan if (ro >= 1660)
1611e098bc96SEvan Quan type = 0;
1612e098bc96SEvan Quan else
1613e098bc96SEvan Quan type = 1;
1614e098bc96SEvan Quan
1615e098bc96SEvan Quan /* Populate Stretch amount */
1616e098bc96SEvan Quan smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
1617e098bc96SEvan Quan
1618e098bc96SEvan Quan
1619e098bc96SEvan Quan /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1620e098bc96SEvan Quan for (i = 0; i < sclk_table->count; i++) {
1621e098bc96SEvan Quan smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1622e098bc96SEvan Quan sclk_table->entries[i].cks_enable << i;
1623e098bc96SEvan Quan if (ASICID_IS_TONGA_P(dev_id, hw_revision)) {
1624e098bc96SEvan Quan volt_without_cks = (uint32_t)((7732 + 60 - ro - 20838 *
1625e098bc96SEvan Quan (sclk_table->entries[i].clk/100) / 10000) * 1000 /
1626e098bc96SEvan Quan (8730 - (5301 * (sclk_table->entries[i].clk/100) / 1000)));
1627e098bc96SEvan Quan volt_with_cks = (uint32_t)((5250 + 51 - ro - 2404 *
1628e098bc96SEvan Quan (sclk_table->entries[i].clk/100) / 100000) * 1000 /
1629e098bc96SEvan Quan (6146 - (3193 * (sclk_table->entries[i].clk/100) / 1000)));
1630e098bc96SEvan Quan } else {
1631e098bc96SEvan Quan volt_without_cks = (uint32_t)((14041 *
1632e098bc96SEvan Quan (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1633e098bc96SEvan Quan (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1634e098bc96SEvan Quan volt_with_cks = (uint32_t)((13946 *
1635e098bc96SEvan Quan (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1636e098bc96SEvan Quan (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1637e098bc96SEvan Quan }
1638e098bc96SEvan Quan if (volt_without_cks >= volt_with_cks)
1639e098bc96SEvan Quan volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1640e098bc96SEvan Quan sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1641e098bc96SEvan Quan smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1642e098bc96SEvan Quan }
1643e098bc96SEvan Quan
1644e098bc96SEvan Quan PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1645e098bc96SEvan Quan STRETCH_ENABLE, 0x0);
1646e098bc96SEvan Quan PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1647e098bc96SEvan Quan masterReset, 0x1);
1648e098bc96SEvan Quan PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1649e098bc96SEvan Quan staticEnable, 0x1);
1650e098bc96SEvan Quan PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1651e098bc96SEvan Quan masterReset, 0x0);
1652e098bc96SEvan Quan
1653e098bc96SEvan Quan /* Populate CKS Lookup Table */
1654e098bc96SEvan Quan if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1655e098bc96SEvan Quan stretch_amount2 = 0;
1656e098bc96SEvan Quan else if (stretch_amount == 3 || stretch_amount == 4)
1657e098bc96SEvan Quan stretch_amount2 = 1;
1658e098bc96SEvan Quan else {
1659e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1660e098bc96SEvan Quan PHM_PlatformCaps_ClockStretcher);
1661e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
1662e098bc96SEvan Quan "Stretch Amount in PPTable not supported",
1663e098bc96SEvan Quan return -EINVAL);
1664e098bc96SEvan Quan }
1665e098bc96SEvan Quan
1666e098bc96SEvan Quan value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1667e098bc96SEvan Quan ixPWR_CKS_CNTL);
1668e098bc96SEvan Quan value &= 0xFFC2FF87;
1669e098bc96SEvan Quan smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1670e098bc96SEvan Quan tonga_clock_stretcher_lookup_table[stretch_amount2][0];
1671e098bc96SEvan Quan smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1672e098bc96SEvan Quan tonga_clock_stretcher_lookup_table[stretch_amount2][1];
1673e098bc96SEvan Quan clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
1674e098bc96SEvan Quan GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
1675e098bc96SEvan Quan SclkFrequency) / 100);
1676e098bc96SEvan Quan if (tonga_clock_stretcher_lookup_table[stretch_amount2][0] <
1677e098bc96SEvan Quan clock_freq_u16 &&
1678e098bc96SEvan Quan tonga_clock_stretcher_lookup_table[stretch_amount2][1] >
1679e098bc96SEvan Quan clock_freq_u16) {
1680e098bc96SEvan Quan /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1681e098bc96SEvan Quan value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1682e098bc96SEvan Quan /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1683e098bc96SEvan Quan value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1684e098bc96SEvan Quan /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1685e098bc96SEvan Quan value |= (tonga_clock_stretch_amount_conversion
1686e098bc96SEvan Quan [tonga_clock_stretcher_lookup_table[stretch_amount2][3]]
1687e098bc96SEvan Quan [stretch_amount]) << 3;
1688e098bc96SEvan Quan }
1689e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1690e098bc96SEvan Quan CKS_LOOKUPTableEntry[0].minFreq);
1691e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1692e098bc96SEvan Quan CKS_LOOKUPTableEntry[0].maxFreq);
1693e098bc96SEvan Quan smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1694e098bc96SEvan Quan tonga_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1695e098bc96SEvan Quan smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1696e098bc96SEvan Quan (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1697e098bc96SEvan Quan
1698e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1699e098bc96SEvan Quan ixPWR_CKS_CNTL, value);
1700e098bc96SEvan Quan
1701e098bc96SEvan Quan /* Populate DDT Lookup Table */
1702e098bc96SEvan Quan for (i = 0; i < 4; i++) {
1703e098bc96SEvan Quan /* Assign the minimum and maximum VID stored
1704e098bc96SEvan Quan * in the last row of Clock Stretcher Voltage Table.
1705e098bc96SEvan Quan */
1706e098bc96SEvan Quan smu_data->smc_state_table.ClockStretcherDataTable.
1707e098bc96SEvan Quan ClockStretcherDataTableEntry[i].minVID =
1708e098bc96SEvan Quan (uint8_t) tonga_clock_stretcher_ddt_table[type][i][2];
1709e098bc96SEvan Quan smu_data->smc_state_table.ClockStretcherDataTable.
1710e098bc96SEvan Quan ClockStretcherDataTableEntry[i].maxVID =
1711e098bc96SEvan Quan (uint8_t) tonga_clock_stretcher_ddt_table[type][i][3];
1712e098bc96SEvan Quan /* Loop through each SCLK and check the frequency
1713e098bc96SEvan Quan * to see if it lies within the frequency for clock stretcher.
1714e098bc96SEvan Quan */
1715e098bc96SEvan Quan for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
1716e098bc96SEvan Quan cks_setting = 0;
1717e098bc96SEvan Quan clock_freq = PP_SMC_TO_HOST_UL(
1718e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
1719e098bc96SEvan Quan /* Check the allowed frequency against the sclk level[j].
1720e098bc96SEvan Quan * Sclk's endianness has already been converted,
1721e098bc96SEvan Quan * and it's in 10Khz unit,
1722e098bc96SEvan Quan * as opposed to Data table, which is in Mhz unit.
1723e098bc96SEvan Quan */
1724e098bc96SEvan Quan if (clock_freq >= tonga_clock_stretcher_ddt_table[type][i][0] * 100) {
1725e098bc96SEvan Quan cks_setting |= 0x2;
1726e098bc96SEvan Quan if (clock_freq < tonga_clock_stretcher_ddt_table[type][i][1] * 100)
1727e098bc96SEvan Quan cks_setting |= 0x1;
1728e098bc96SEvan Quan }
1729e098bc96SEvan Quan smu_data->smc_state_table.ClockStretcherDataTable.
1730e098bc96SEvan Quan ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
1731e098bc96SEvan Quan }
1732e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
1733e098bc96SEvan Quan ClockStretcherDataTable.
1734e098bc96SEvan Quan ClockStretcherDataTableEntry[i].setting);
1735e098bc96SEvan Quan }
1736e098bc96SEvan Quan
1737e098bc96SEvan Quan value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1738e098bc96SEvan Quan ixPWR_CKS_CNTL);
1739e098bc96SEvan Quan value &= 0xFFFFFFFE;
1740e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1741e098bc96SEvan Quan ixPWR_CKS_CNTL, value);
1742e098bc96SEvan Quan
1743e098bc96SEvan Quan return 0;
1744e098bc96SEvan Quan }
1745e098bc96SEvan Quan
tonga_populate_vr_config(struct pp_hwmgr * hwmgr,SMU72_Discrete_DpmTable * table)1746e098bc96SEvan Quan static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1747e098bc96SEvan Quan SMU72_Discrete_DpmTable *table)
1748e098bc96SEvan Quan {
1749e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1750e098bc96SEvan Quan uint16_t config;
1751e098bc96SEvan Quan
1752e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1753e098bc96SEvan Quan /* Splitted mode */
1754e098bc96SEvan Quan config = VR_SVI2_PLANE_1;
1755e098bc96SEvan Quan table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1756e098bc96SEvan Quan
1757e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1758e098bc96SEvan Quan config = VR_SVI2_PLANE_2;
1759e098bc96SEvan Quan table->VRConfig |= config;
1760e098bc96SEvan Quan } else {
1761e098bc96SEvan Quan pr_err("VDDC and VDDGFX should "
1762e098bc96SEvan Quan "be both on SVI2 control in splitted mode !\n");
1763e098bc96SEvan Quan }
1764e098bc96SEvan Quan } else {
1765e098bc96SEvan Quan /* Merged mode */
1766e098bc96SEvan Quan config = VR_MERGED_WITH_VDDC;
1767e098bc96SEvan Quan table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1768e098bc96SEvan Quan
1769e098bc96SEvan Quan /* Set Vddc Voltage Controller */
1770e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1771e098bc96SEvan Quan config = VR_SVI2_PLANE_1;
1772e098bc96SEvan Quan table->VRConfig |= config;
1773e098bc96SEvan Quan } else {
1774e098bc96SEvan Quan pr_err("VDDC should be on "
1775e098bc96SEvan Quan "SVI2 control in merged mode !\n");
1776e098bc96SEvan Quan }
1777e098bc96SEvan Quan }
1778e098bc96SEvan Quan
1779e098bc96SEvan Quan /* Set Vddci Voltage Controller */
1780e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1781e098bc96SEvan Quan config = VR_SVI2_PLANE_2; /* only in merged mode */
1782e098bc96SEvan Quan table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1783e098bc96SEvan Quan } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1784e098bc96SEvan Quan config = VR_SMIO_PATTERN_1;
1785e098bc96SEvan Quan table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1786e098bc96SEvan Quan }
1787e098bc96SEvan Quan
1788e098bc96SEvan Quan /* Set Mvdd Voltage Controller */
1789e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1790e098bc96SEvan Quan config = VR_SMIO_PATTERN_2;
1791e098bc96SEvan Quan table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1792e098bc96SEvan Quan }
1793e098bc96SEvan Quan
1794e098bc96SEvan Quan return 0;
1795e098bc96SEvan Quan }
1796e098bc96SEvan Quan
tonga_init_arb_table_index(struct pp_hwmgr * hwmgr)1797e098bc96SEvan Quan static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
1798e098bc96SEvan Quan {
1799e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
1800e098bc96SEvan Quan uint32_t tmp;
1801e098bc96SEvan Quan int result;
1802e098bc96SEvan Quan
1803e098bc96SEvan Quan /*
1804e098bc96SEvan Quan * This is a read-modify-write on the first byte of the ARB table.
1805e098bc96SEvan Quan * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure
1806e098bc96SEvan Quan * is the field 'current'.
1807e098bc96SEvan Quan * This solution is ugly, but we never write the whole table only
1808e098bc96SEvan Quan * individual fields in it.
1809e098bc96SEvan Quan * In reality this field should not be in that structure
1810e098bc96SEvan Quan * but in a soft register.
1811e098bc96SEvan Quan */
1812e098bc96SEvan Quan result = smu7_read_smc_sram_dword(hwmgr,
1813e098bc96SEvan Quan smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1814e098bc96SEvan Quan
1815e098bc96SEvan Quan if (result != 0)
1816e098bc96SEvan Quan return result;
1817e098bc96SEvan Quan
1818e098bc96SEvan Quan tmp &= 0x00FFFFFF;
1819e098bc96SEvan Quan tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1820e098bc96SEvan Quan
1821e098bc96SEvan Quan return smu7_write_smc_sram_dword(hwmgr,
1822e098bc96SEvan Quan smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
1823e098bc96SEvan Quan }
1824e098bc96SEvan Quan
1825e098bc96SEvan Quan
tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr * hwmgr)1826e098bc96SEvan Quan static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1827e098bc96SEvan Quan {
1828e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1829e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1830e098bc96SEvan Quan const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1831e098bc96SEvan Quan SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
1832e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
1833e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
1834e098bc96SEvan Quan struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
1835e098bc96SEvan Quan int i, j, k;
1836e098bc96SEvan Quan const uint16_t *pdef1, *pdef2;
1837e098bc96SEvan Quan
1838e098bc96SEvan Quan dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
1839e098bc96SEvan Quan (uint16_t)(cac_dtp_table->usTDP * 256));
1840e098bc96SEvan Quan dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
1841e098bc96SEvan Quan (uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
1842e098bc96SEvan Quan
1843e098bc96SEvan Quan PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
1844e098bc96SEvan Quan "Target Operating Temp is out of Range !",
1845e098bc96SEvan Quan );
1846e098bc96SEvan Quan
1847e098bc96SEvan Quan dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
1848e098bc96SEvan Quan dpm_table->GpuTjHyst = 8;
1849e098bc96SEvan Quan
1850e098bc96SEvan Quan dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
1851e098bc96SEvan Quan
1852e098bc96SEvan Quan dpm_table->BAPM_TEMP_GRADIENT =
1853e098bc96SEvan Quan PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
1854e098bc96SEvan Quan pdef1 = defaults->bapmti_r;
1855e098bc96SEvan Quan pdef2 = defaults->bapmti_rc;
1856e098bc96SEvan Quan
1857e098bc96SEvan Quan for (i = 0; i < SMU72_DTE_ITERATIONS; i++) {
1858e098bc96SEvan Quan for (j = 0; j < SMU72_DTE_SOURCES; j++) {
1859e098bc96SEvan Quan for (k = 0; k < SMU72_DTE_SINKS; k++) {
1860e098bc96SEvan Quan dpm_table->BAPMTI_R[i][j][k] =
1861e098bc96SEvan Quan PP_HOST_TO_SMC_US(*pdef1);
1862e098bc96SEvan Quan dpm_table->BAPMTI_RC[i][j][k] =
1863e098bc96SEvan Quan PP_HOST_TO_SMC_US(*pdef2);
1864e098bc96SEvan Quan pdef1++;
1865e098bc96SEvan Quan pdef2++;
1866e098bc96SEvan Quan }
1867e098bc96SEvan Quan }
1868e098bc96SEvan Quan }
1869e098bc96SEvan Quan
1870e098bc96SEvan Quan return 0;
1871e098bc96SEvan Quan }
1872e098bc96SEvan Quan
tonga_populate_svi_load_line(struct pp_hwmgr * hwmgr)1873e098bc96SEvan Quan static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1874e098bc96SEvan Quan {
1875e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1876e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1877e098bc96SEvan Quan const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1878e098bc96SEvan Quan
1879e098bc96SEvan Quan smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
1880e098bc96SEvan Quan smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC;
1881e098bc96SEvan Quan smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
1882e098bc96SEvan Quan smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
1883e098bc96SEvan Quan
1884e098bc96SEvan Quan return 0;
1885e098bc96SEvan Quan }
1886e098bc96SEvan Quan
tonga_populate_tdc_limit(struct pp_hwmgr * hwmgr)1887e098bc96SEvan Quan static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1888e098bc96SEvan Quan {
1889e098bc96SEvan Quan uint16_t tdc_limit;
1890e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1891e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1892e098bc96SEvan Quan const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1893e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
1894e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
1895e098bc96SEvan Quan
1896e098bc96SEvan Quan /* TDC number of fraction bits are changed from 8 to 7
1897e098bc96SEvan Quan * for Fiji as requested by SMC team
1898e098bc96SEvan Quan */
1899e098bc96SEvan Quan tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 256);
1900e098bc96SEvan Quan smu_data->power_tune_table.TDC_VDDC_PkgLimit =
1901e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
1902e098bc96SEvan Quan smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
1903e098bc96SEvan Quan defaults->tdc_vddc_throttle_release_limit_perc;
1904e098bc96SEvan Quan smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
1905e098bc96SEvan Quan
1906e098bc96SEvan Quan return 0;
1907e098bc96SEvan Quan }
1908e098bc96SEvan Quan
tonga_populate_dw8(struct pp_hwmgr * hwmgr,uint32_t fuse_table_offset)1909e098bc96SEvan Quan static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1910e098bc96SEvan Quan {
1911e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1912e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1913e098bc96SEvan Quan const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1914e098bc96SEvan Quan uint32_t temp;
1915e098bc96SEvan Quan
1916e098bc96SEvan Quan if (smu7_read_smc_sram_dword(hwmgr,
1917e098bc96SEvan Quan fuse_table_offset +
1918e098bc96SEvan Quan offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl),
1919e098bc96SEvan Quan (uint32_t *)&temp, SMC_RAM_END))
1920e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
1921e098bc96SEvan Quan "Attempt to read PmFuses.DW6 "
1922e098bc96SEvan Quan "(SviLoadLineEn) from SMC Failed !",
1923e098bc96SEvan Quan return -EINVAL);
1924e098bc96SEvan Quan else
1925e098bc96SEvan Quan smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
1926e098bc96SEvan Quan
1927e098bc96SEvan Quan return 0;
1928e098bc96SEvan Quan }
1929e098bc96SEvan Quan
tonga_populate_temperature_scaler(struct pp_hwmgr * hwmgr)1930e098bc96SEvan Quan static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1931e098bc96SEvan Quan {
1932e098bc96SEvan Quan int i;
1933e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1934e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1935e098bc96SEvan Quan
1936e098bc96SEvan Quan /* Currently not used. Set all to zero. */
1937e098bc96SEvan Quan for (i = 0; i < 16; i++)
1938e098bc96SEvan Quan smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
1939e098bc96SEvan Quan
1940e098bc96SEvan Quan return 0;
1941e098bc96SEvan Quan }
1942e098bc96SEvan Quan
tonga_populate_fuzzy_fan(struct pp_hwmgr * hwmgr)1943e098bc96SEvan Quan static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1944e098bc96SEvan Quan {
1945e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
1946e098bc96SEvan Quan
1947e098bc96SEvan Quan if ((hwmgr->thermal_controller.advanceFanControlParameters.
1948e098bc96SEvan Quan usFanOutputSensitivity & (1 << 15)) ||
1949e098bc96SEvan Quan (hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0))
1950e098bc96SEvan Quan hwmgr->thermal_controller.advanceFanControlParameters.
1951e098bc96SEvan Quan usFanOutputSensitivity = hwmgr->thermal_controller.
1952e098bc96SEvan Quan advanceFanControlParameters.usDefaultFanOutputSensitivity;
1953e098bc96SEvan Quan
1954e098bc96SEvan Quan smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
1955e098bc96SEvan Quan PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
1956e098bc96SEvan Quan advanceFanControlParameters.usFanOutputSensitivity);
1957e098bc96SEvan Quan return 0;
1958e098bc96SEvan Quan }
1959e098bc96SEvan Quan
tonga_populate_gnb_lpml(struct pp_hwmgr * hwmgr)1960e098bc96SEvan Quan static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1961e098bc96SEvan Quan {
1962e098bc96SEvan Quan int i;
1963e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1964e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1965e098bc96SEvan Quan
1966e098bc96SEvan Quan /* Currently not used. Set all to zero. */
1967e098bc96SEvan Quan for (i = 0; i < 16; i++)
1968e098bc96SEvan Quan smu_data->power_tune_table.GnbLPML[i] = 0;
1969e098bc96SEvan Quan
1970e098bc96SEvan Quan return 0;
1971e098bc96SEvan Quan }
1972e098bc96SEvan Quan
tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr * hwmgr)1973e098bc96SEvan Quan static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1974e098bc96SEvan Quan {
1975e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1976e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1977e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
1978e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
1979e098bc96SEvan Quan uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
1980e098bc96SEvan Quan uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
1981e098bc96SEvan Quan struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
1982e098bc96SEvan Quan
1983e098bc96SEvan Quan hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
1984e098bc96SEvan Quan lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
1985e098bc96SEvan Quan
1986e098bc96SEvan Quan smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
1987e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
1988e098bc96SEvan Quan smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
1989e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
1990e098bc96SEvan Quan
1991e098bc96SEvan Quan return 0;
1992e098bc96SEvan Quan }
1993e098bc96SEvan Quan
tonga_populate_pm_fuses(struct pp_hwmgr * hwmgr)1994e098bc96SEvan Quan static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1995e098bc96SEvan Quan {
1996e098bc96SEvan Quan struct tonga_smumgr *smu_data =
1997e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
1998e098bc96SEvan Quan uint32_t pm_fuse_table_offset;
1999e098bc96SEvan Quan
2000e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2001e098bc96SEvan Quan PHM_PlatformCaps_PowerContainment)) {
2002e098bc96SEvan Quan if (smu7_read_smc_sram_dword(hwmgr,
2003e098bc96SEvan Quan SMU72_FIRMWARE_HEADER_LOCATION +
2004e098bc96SEvan Quan offsetof(SMU72_Firmware_Header, PmFuseTable),
2005e098bc96SEvan Quan &pm_fuse_table_offset, SMC_RAM_END))
2006e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
2007e098bc96SEvan Quan "Attempt to get pm_fuse_table_offset Failed !",
2008e098bc96SEvan Quan return -EINVAL);
2009e098bc96SEvan Quan
2010e098bc96SEvan Quan /* DW6 */
2011e098bc96SEvan Quan if (tonga_populate_svi_load_line(hwmgr))
2012e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
2013e098bc96SEvan Quan "Attempt to populate SviLoadLine Failed !",
2014e098bc96SEvan Quan return -EINVAL);
2015e098bc96SEvan Quan /* DW7 */
2016e098bc96SEvan Quan if (tonga_populate_tdc_limit(hwmgr))
2017e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
2018e098bc96SEvan Quan "Attempt to populate TDCLimit Failed !",
2019e098bc96SEvan Quan return -EINVAL);
2020e098bc96SEvan Quan /* DW8 */
2021e098bc96SEvan Quan if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset))
2022e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
2023e098bc96SEvan Quan "Attempt to populate TdcWaterfallCtl Failed !",
2024e098bc96SEvan Quan return -EINVAL);
2025e098bc96SEvan Quan
2026e098bc96SEvan Quan /* DW9-DW12 */
2027e098bc96SEvan Quan if (tonga_populate_temperature_scaler(hwmgr) != 0)
2028e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
2029e098bc96SEvan Quan "Attempt to populate LPMLTemperatureScaler Failed !",
2030e098bc96SEvan Quan return -EINVAL);
2031e098bc96SEvan Quan
2032e098bc96SEvan Quan /* DW13-DW14 */
2033e098bc96SEvan Quan if (tonga_populate_fuzzy_fan(hwmgr))
2034e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
2035e098bc96SEvan Quan "Attempt to populate Fuzzy Fan "
2036e098bc96SEvan Quan "Control parameters Failed !",
2037e098bc96SEvan Quan return -EINVAL);
2038e098bc96SEvan Quan
2039e098bc96SEvan Quan /* DW15-DW18 */
2040e098bc96SEvan Quan if (tonga_populate_gnb_lpml(hwmgr))
2041e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
2042e098bc96SEvan Quan "Attempt to populate GnbLPML Failed !",
2043e098bc96SEvan Quan return -EINVAL);
2044e098bc96SEvan Quan
2045e098bc96SEvan Quan /* DW20 */
2046e098bc96SEvan Quan if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
2047e098bc96SEvan Quan PP_ASSERT_WITH_CODE(
2048e098bc96SEvan Quan false,
2049e098bc96SEvan Quan "Attempt to populate BapmVddCBaseLeakage "
2050e098bc96SEvan Quan "Hi and Lo Sidd Failed !",
2051e098bc96SEvan Quan return -EINVAL);
2052e098bc96SEvan Quan
2053e098bc96SEvan Quan if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
2054e098bc96SEvan Quan (uint8_t *)&smu_data->power_tune_table,
2055e098bc96SEvan Quan sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END))
2056e098bc96SEvan Quan PP_ASSERT_WITH_CODE(false,
2057e098bc96SEvan Quan "Attempt to download PmFuseTable Failed !",
2058e098bc96SEvan Quan return -EINVAL);
2059e098bc96SEvan Quan }
2060e098bc96SEvan Quan return 0;
2061e098bc96SEvan Quan }
2062e098bc96SEvan Quan
tonga_populate_mc_reg_address(struct pp_hwmgr * hwmgr,SMU72_Discrete_MCRegisters * mc_reg_table)2063e098bc96SEvan Quan static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
2064e098bc96SEvan Quan SMU72_Discrete_MCRegisters *mc_reg_table)
2065e098bc96SEvan Quan {
2066e098bc96SEvan Quan const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend;
2067e098bc96SEvan Quan
2068e098bc96SEvan Quan uint32_t i, j;
2069e098bc96SEvan Quan
2070e098bc96SEvan Quan for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
2071e098bc96SEvan Quan if (smu_data->mc_reg_table.validflag & 1<<j) {
2072e098bc96SEvan Quan PP_ASSERT_WITH_CODE(
2073e098bc96SEvan Quan i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
2074e098bc96SEvan Quan "Index of mc_reg_table->address[] array "
2075e098bc96SEvan Quan "out of boundary",
2076e098bc96SEvan Quan return -EINVAL);
2077e098bc96SEvan Quan mc_reg_table->address[i].s0 =
2078e098bc96SEvan Quan PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
2079e098bc96SEvan Quan mc_reg_table->address[i].s1 =
2080e098bc96SEvan Quan PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
2081e098bc96SEvan Quan i++;
2082e098bc96SEvan Quan }
2083e098bc96SEvan Quan }
2084e098bc96SEvan Quan
2085e098bc96SEvan Quan mc_reg_table->last = (uint8_t)i;
2086e098bc96SEvan Quan
2087e098bc96SEvan Quan return 0;
2088e098bc96SEvan Quan }
2089e098bc96SEvan Quan
2090e098bc96SEvan Quan /*convert register values from driver to SMC format */
tonga_convert_mc_registers(const struct tonga_mc_reg_entry * entry,SMU72_Discrete_MCRegisterSet * data,uint32_t num_entries,uint32_t valid_flag)2091e098bc96SEvan Quan static void tonga_convert_mc_registers(
2092e098bc96SEvan Quan const struct tonga_mc_reg_entry *entry,
2093e098bc96SEvan Quan SMU72_Discrete_MCRegisterSet *data,
2094e098bc96SEvan Quan uint32_t num_entries, uint32_t valid_flag)
2095e098bc96SEvan Quan {
2096e098bc96SEvan Quan uint32_t i, j;
2097e098bc96SEvan Quan
2098e098bc96SEvan Quan for (i = 0, j = 0; j < num_entries; j++) {
2099e098bc96SEvan Quan if (valid_flag & 1<<j) {
2100e098bc96SEvan Quan data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
2101e098bc96SEvan Quan i++;
2102e098bc96SEvan Quan }
2103e098bc96SEvan Quan }
2104e098bc96SEvan Quan }
2105e098bc96SEvan Quan
tonga_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr * hwmgr,const uint32_t memory_clock,SMU72_Discrete_MCRegisterSet * mc_reg_table_data)2106e098bc96SEvan Quan static int tonga_convert_mc_reg_table_entry_to_smc(
2107e098bc96SEvan Quan struct pp_hwmgr *hwmgr,
2108e098bc96SEvan Quan const uint32_t memory_clock,
2109e098bc96SEvan Quan SMU72_Discrete_MCRegisterSet *mc_reg_table_data
2110e098bc96SEvan Quan )
2111e098bc96SEvan Quan {
2112e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2113e098bc96SEvan Quan uint32_t i = 0;
2114e098bc96SEvan Quan
2115e098bc96SEvan Quan for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
2116e098bc96SEvan Quan if (memory_clock <=
2117e098bc96SEvan Quan smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
2118e098bc96SEvan Quan break;
2119e098bc96SEvan Quan }
2120e098bc96SEvan Quan }
2121e098bc96SEvan Quan
2122e098bc96SEvan Quan if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
2123e098bc96SEvan Quan --i;
2124e098bc96SEvan Quan
2125e098bc96SEvan Quan tonga_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
2126e098bc96SEvan Quan mc_reg_table_data, smu_data->mc_reg_table.last,
2127e098bc96SEvan Quan smu_data->mc_reg_table.validflag);
2128e098bc96SEvan Quan
2129e098bc96SEvan Quan return 0;
2130e098bc96SEvan Quan }
2131e098bc96SEvan Quan
tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr * hwmgr,SMU72_Discrete_MCRegisters * mc_regs)2132e098bc96SEvan Quan static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
2133e098bc96SEvan Quan SMU72_Discrete_MCRegisters *mc_regs)
2134e098bc96SEvan Quan {
2135e098bc96SEvan Quan int result = 0;
2136e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2137e098bc96SEvan Quan int res;
2138e098bc96SEvan Quan uint32_t i;
2139e098bc96SEvan Quan
2140e098bc96SEvan Quan for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
2141e098bc96SEvan Quan res = tonga_convert_mc_reg_table_entry_to_smc(
2142e098bc96SEvan Quan hwmgr,
2143e098bc96SEvan Quan data->dpm_table.mclk_table.dpm_levels[i].value,
2144e098bc96SEvan Quan &mc_regs->data[i]
2145e098bc96SEvan Quan );
2146e098bc96SEvan Quan
2147e098bc96SEvan Quan if (0 != res)
2148e098bc96SEvan Quan result = res;
2149e098bc96SEvan Quan }
2150e098bc96SEvan Quan
2151e098bc96SEvan Quan return result;
2152e098bc96SEvan Quan }
2153e098bc96SEvan Quan
tonga_update_and_upload_mc_reg_table(struct pp_hwmgr * hwmgr)2154e098bc96SEvan Quan static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
2155e098bc96SEvan Quan {
2156e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2157e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2158e098bc96SEvan Quan uint32_t address;
2159e098bc96SEvan Quan int32_t result;
2160e098bc96SEvan Quan
2161e098bc96SEvan Quan if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
2162e098bc96SEvan Quan return 0;
2163e098bc96SEvan Quan
2164e098bc96SEvan Quan
2165e098bc96SEvan Quan memset(&smu_data->mc_regs, 0, sizeof(SMU72_Discrete_MCRegisters));
2166e098bc96SEvan Quan
2167e098bc96SEvan Quan result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
2168e098bc96SEvan Quan
2169e098bc96SEvan Quan if (result != 0)
2170e098bc96SEvan Quan return result;
2171e098bc96SEvan Quan
2172e098bc96SEvan Quan
2173e098bc96SEvan Quan address = smu_data->smu7_data.mc_reg_table_start +
2174e098bc96SEvan Quan (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
2175e098bc96SEvan Quan
2176e098bc96SEvan Quan return smu7_copy_bytes_to_smc(
2177e098bc96SEvan Quan hwmgr, address,
2178e098bc96SEvan Quan (uint8_t *)&smu_data->mc_regs.data[0],
2179e098bc96SEvan Quan sizeof(SMU72_Discrete_MCRegisterSet) *
2180e098bc96SEvan Quan data->dpm_table.mclk_table.count,
2181e098bc96SEvan Quan SMC_RAM_END);
2182e098bc96SEvan Quan }
2183e098bc96SEvan Quan
tonga_populate_initial_mc_reg_table(struct pp_hwmgr * hwmgr)2184e098bc96SEvan Quan static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
2185e098bc96SEvan Quan {
2186e098bc96SEvan Quan int result;
2187e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2188e098bc96SEvan Quan
2189e098bc96SEvan Quan memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
2190e098bc96SEvan Quan result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
2191e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2192e098bc96SEvan Quan "Failed to initialize MCRegTable for the MC register addresses !",
2193e098bc96SEvan Quan return result;);
2194e098bc96SEvan Quan
2195e098bc96SEvan Quan result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
2196e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2197e098bc96SEvan Quan "Failed to initialize MCRegTable for driver state !",
2198e098bc96SEvan Quan return result;);
2199e098bc96SEvan Quan
2200e098bc96SEvan Quan return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
2201e098bc96SEvan Quan (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);
2202e098bc96SEvan Quan }
2203e098bc96SEvan Quan
tonga_initialize_power_tune_defaults(struct pp_hwmgr * hwmgr)2204e098bc96SEvan Quan static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
2205e098bc96SEvan Quan {
2206e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2207e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
2208e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
2209e098bc96SEvan Quan
2210e098bc96SEvan Quan if (table_info &&
2211e098bc96SEvan Quan table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
2212e098bc96SEvan Quan table_info->cac_dtp_table->usPowerTuneDataSetID)
2213e098bc96SEvan Quan smu_data->power_tune_defaults =
2214e098bc96SEvan Quan &tonga_power_tune_data_set_array
2215e098bc96SEvan Quan [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
2216e098bc96SEvan Quan else
2217e098bc96SEvan Quan smu_data->power_tune_defaults = &tonga_power_tune_data_set_array[0];
2218e098bc96SEvan Quan }
2219e098bc96SEvan Quan
tonga_init_smc_table(struct pp_hwmgr * hwmgr)2220e098bc96SEvan Quan static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2221e098bc96SEvan Quan {
2222e098bc96SEvan Quan int result;
2223e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2224e098bc96SEvan Quan struct tonga_smumgr *smu_data =
2225e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
2226e098bc96SEvan Quan SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
2227e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
2228e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
2229e098bc96SEvan Quan
2230e098bc96SEvan Quan uint8_t i;
2231e098bc96SEvan Quan pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2232e098bc96SEvan Quan
2233e098bc96SEvan Quan
2234e098bc96SEvan Quan memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
2235e098bc96SEvan Quan
2236e098bc96SEvan Quan tonga_initialize_power_tune_defaults(hwmgr);
2237e098bc96SEvan Quan
2238e098bc96SEvan Quan if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
2239e098bc96SEvan Quan tonga_populate_smc_voltage_tables(hwmgr, table);
2240e098bc96SEvan Quan
2241e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2242e098bc96SEvan Quan PHM_PlatformCaps_AutomaticDCTransition))
2243e098bc96SEvan Quan table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2244e098bc96SEvan Quan
2245e098bc96SEvan Quan
2246e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2247e098bc96SEvan Quan PHM_PlatformCaps_StepVddc))
2248e098bc96SEvan Quan table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2249e098bc96SEvan Quan
2250e098bc96SEvan Quan if (data->is_memory_gddr5)
2251e098bc96SEvan Quan table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2252e098bc96SEvan Quan
2253e098bc96SEvan Quan i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2254e098bc96SEvan Quan
2255e098bc96SEvan Quan if (i == 1 || i == 0)
2256e098bc96SEvan Quan table->SystemFlags |= 0x40;
2257e098bc96SEvan Quan
2258e098bc96SEvan Quan if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
2259e098bc96SEvan Quan result = tonga_populate_ulv_state(hwmgr, table);
2260e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2261e098bc96SEvan Quan "Failed to initialize ULV state !",
2262e098bc96SEvan Quan return result;);
2263e098bc96SEvan Quan
2264e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2265e098bc96SEvan Quan ixCG_ULV_PARAMETER, 0x40035);
2266e098bc96SEvan Quan }
2267e098bc96SEvan Quan
2268e098bc96SEvan Quan result = tonga_populate_smc_link_level(hwmgr, table);
2269e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2270e098bc96SEvan Quan "Failed to initialize Link Level !", return result);
2271e098bc96SEvan Quan
2272e098bc96SEvan Quan result = tonga_populate_all_graphic_levels(hwmgr);
2273e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2274e098bc96SEvan Quan "Failed to initialize Graphics Level !", return result);
2275e098bc96SEvan Quan
2276e098bc96SEvan Quan result = tonga_populate_all_memory_levels(hwmgr);
2277e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2278e098bc96SEvan Quan "Failed to initialize Memory Level !", return result);
2279e098bc96SEvan Quan
2280e098bc96SEvan Quan result = tonga_populate_smc_acpi_level(hwmgr, table);
2281e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2282e098bc96SEvan Quan "Failed to initialize ACPI Level !", return result);
2283e098bc96SEvan Quan
2284e098bc96SEvan Quan result = tonga_populate_smc_vce_level(hwmgr, table);
2285e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2286e098bc96SEvan Quan "Failed to initialize VCE Level !", return result);
2287e098bc96SEvan Quan
2288e098bc96SEvan Quan result = tonga_populate_smc_acp_level(hwmgr, table);
2289e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2290e098bc96SEvan Quan "Failed to initialize ACP Level !", return result);
2291e098bc96SEvan Quan
2292e098bc96SEvan Quan /* Since only the initial state is completely set up at this
2293e098bc96SEvan Quan * point (the other states are just copies of the boot state) we only
2294e098bc96SEvan Quan * need to populate the ARB settings for the initial state.
2295e098bc96SEvan Quan */
2296e098bc96SEvan Quan result = tonga_program_memory_timing_parameters(hwmgr);
2297e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2298e098bc96SEvan Quan "Failed to Write ARB settings for the initial state.",
2299e098bc96SEvan Quan return result;);
2300e098bc96SEvan Quan
2301e098bc96SEvan Quan result = tonga_populate_smc_uvd_level(hwmgr, table);
2302e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2303e098bc96SEvan Quan "Failed to initialize UVD Level !", return result);
2304e098bc96SEvan Quan
2305e098bc96SEvan Quan result = tonga_populate_smc_boot_level(hwmgr, table);
2306e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2307e098bc96SEvan Quan "Failed to initialize Boot Level !", return result);
2308e098bc96SEvan Quan
2309e098bc96SEvan Quan tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
2310e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2311e098bc96SEvan Quan "Failed to populate BAPM Parameters !", return result);
2312e098bc96SEvan Quan
2313e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2314e098bc96SEvan Quan PHM_PlatformCaps_ClockStretcher)) {
2315e098bc96SEvan Quan result = tonga_populate_clock_stretcher_data_table(hwmgr);
2316e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2317e098bc96SEvan Quan "Failed to populate Clock Stretcher Data Table !",
2318e098bc96SEvan Quan return result;);
2319e098bc96SEvan Quan }
2320e098bc96SEvan Quan table->GraphicsVoltageChangeEnable = 1;
2321e098bc96SEvan Quan table->GraphicsThermThrottleEnable = 1;
2322e098bc96SEvan Quan table->GraphicsInterval = 1;
2323e098bc96SEvan Quan table->VoltageInterval = 1;
2324e098bc96SEvan Quan table->ThermalInterval = 1;
2325e098bc96SEvan Quan table->TemperatureLimitHigh =
2326e098bc96SEvan Quan table_info->cac_dtp_table->usTargetOperatingTemp *
2327e098bc96SEvan Quan SMU7_Q88_FORMAT_CONVERSION_UNIT;
2328e098bc96SEvan Quan table->TemperatureLimitLow =
2329e098bc96SEvan Quan (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2330e098bc96SEvan Quan SMU7_Q88_FORMAT_CONVERSION_UNIT;
2331e098bc96SEvan Quan table->MemoryVoltageChangeEnable = 1;
2332e098bc96SEvan Quan table->MemoryInterval = 1;
2333e098bc96SEvan Quan table->VoltageResponseTime = 0;
2334e098bc96SEvan Quan table->PhaseResponseTime = 0;
2335e098bc96SEvan Quan table->MemoryThermThrottleEnable = 1;
2336e098bc96SEvan Quan
2337e098bc96SEvan Quan /*
2338e098bc96SEvan Quan * Cail reads current link status and reports it as cap (we cannot
2339e098bc96SEvan Quan * change this due to some previous issues we had)
2340e098bc96SEvan Quan * SMC drops the link status to lowest level after enabling
2341e098bc96SEvan Quan * DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
2342e098bc96SEvan Quan * but this time Cail reads current link status which was set to low by
2343e098bc96SEvan Quan * SMC and reports it as cap to powerplay
2344e098bc96SEvan Quan * To avoid it, we set PCIeBootLinkLevel to highest dpm level
2345e098bc96SEvan Quan */
2346e098bc96SEvan Quan PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
2347e098bc96SEvan Quan "There must be 1 or more PCIE levels defined in PPTable.",
2348e098bc96SEvan Quan return -EINVAL);
2349e098bc96SEvan Quan
2350e098bc96SEvan Quan table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
2351e098bc96SEvan Quan
2352e098bc96SEvan Quan table->PCIeGenInterval = 1;
2353e098bc96SEvan Quan
2354e098bc96SEvan Quan result = tonga_populate_vr_config(hwmgr, table);
2355e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2356e098bc96SEvan Quan "Failed to populate VRConfig setting !", return result);
2357e098bc96SEvan Quan data->vr_config = table->VRConfig;
2358e098bc96SEvan Quan table->ThermGpio = 17;
2359e098bc96SEvan Quan table->SclkStepSize = 0x4000;
2360e098bc96SEvan Quan
2361e098bc96SEvan Quan if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
2362e098bc96SEvan Quan &gpio_pin_assignment)) {
2363e098bc96SEvan Quan table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2364e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2365e098bc96SEvan Quan PHM_PlatformCaps_RegulatorHot);
2366e098bc96SEvan Quan } else {
2367e098bc96SEvan Quan table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2368e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2369e098bc96SEvan Quan PHM_PlatformCaps_RegulatorHot);
2370e098bc96SEvan Quan }
2371e098bc96SEvan Quan
2372e098bc96SEvan Quan if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2373e098bc96SEvan Quan &gpio_pin_assignment)) {
2374e098bc96SEvan Quan table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2375e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2376e098bc96SEvan Quan PHM_PlatformCaps_AutomaticDCTransition);
2377e098bc96SEvan Quan } else {
2378e098bc96SEvan Quan table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2379e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2380e098bc96SEvan Quan PHM_PlatformCaps_AutomaticDCTransition);
2381e098bc96SEvan Quan }
2382e098bc96SEvan Quan
2383e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2384e098bc96SEvan Quan PHM_PlatformCaps_Falcon_QuickTransition);
2385e098bc96SEvan Quan
2386e098bc96SEvan Quan if (0) {
2387e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2388e098bc96SEvan Quan PHM_PlatformCaps_AutomaticDCTransition);
2389e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2390e098bc96SEvan Quan PHM_PlatformCaps_Falcon_QuickTransition);
2391e098bc96SEvan Quan }
2392e098bc96SEvan Quan
2393e098bc96SEvan Quan if (atomctrl_get_pp_assign_pin(hwmgr,
2394e098bc96SEvan Quan THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment)) {
2395e098bc96SEvan Quan phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2396e098bc96SEvan Quan PHM_PlatformCaps_ThermalOutGPIO);
2397e098bc96SEvan Quan
2398e098bc96SEvan Quan table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2399e098bc96SEvan Quan
2400e098bc96SEvan Quan table->ThermOutPolarity =
2401e098bc96SEvan Quan (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2402e098bc96SEvan Quan (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1 : 0;
2403e098bc96SEvan Quan
2404e098bc96SEvan Quan table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2405e098bc96SEvan Quan
2406e098bc96SEvan Quan /* if required, combine VRHot/PCC with thermal out GPIO*/
2407e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2408e098bc96SEvan Quan PHM_PlatformCaps_RegulatorHot) &&
2409e098bc96SEvan Quan phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2410e098bc96SEvan Quan PHM_PlatformCaps_CombinePCCWithThermalSignal)){
2411e098bc96SEvan Quan table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2412e098bc96SEvan Quan }
2413e098bc96SEvan Quan } else {
2414e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2415e098bc96SEvan Quan PHM_PlatformCaps_ThermalOutGPIO);
2416e098bc96SEvan Quan
2417e098bc96SEvan Quan table->ThermOutGpio = 17;
2418e098bc96SEvan Quan table->ThermOutPolarity = 1;
2419e098bc96SEvan Quan table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2420e098bc96SEvan Quan }
2421e098bc96SEvan Quan
2422e098bc96SEvan Quan for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++)
2423e098bc96SEvan Quan table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2424e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2425e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2426e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2427e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2428e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2429e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2430e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2431e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2432e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2433e098bc96SEvan Quan
2434e098bc96SEvan Quan /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2435e098bc96SEvan Quan result = smu7_copy_bytes_to_smc(
2436e098bc96SEvan Quan hwmgr,
2437e098bc96SEvan Quan smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
2438e098bc96SEvan Quan (uint8_t *)&(table->SystemFlags),
2439e098bc96SEvan Quan sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController),
2440e098bc96SEvan Quan SMC_RAM_END);
2441e098bc96SEvan Quan
2442e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2443e098bc96SEvan Quan "Failed to upload dpm data to SMC memory !", return result;);
2444e098bc96SEvan Quan
2445e098bc96SEvan Quan result = tonga_init_arb_table_index(hwmgr);
2446e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!result,
2447e098bc96SEvan Quan "Failed to upload arb data to SMC memory !", return result);
2448e098bc96SEvan Quan
2449e098bc96SEvan Quan tonga_populate_pm_fuses(hwmgr);
2450e098bc96SEvan Quan PP_ASSERT_WITH_CODE((!result),
2451e098bc96SEvan Quan "Failed to populate initialize pm fuses !", return result);
2452e098bc96SEvan Quan
2453e098bc96SEvan Quan result = tonga_populate_initial_mc_reg_table(hwmgr);
2454e098bc96SEvan Quan PP_ASSERT_WITH_CODE((!result),
2455e098bc96SEvan Quan "Failed to populate initialize MC Reg table !", return result);
2456e098bc96SEvan Quan
2457e098bc96SEvan Quan return 0;
2458e098bc96SEvan Quan }
2459e098bc96SEvan Quan
tonga_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)2460e098bc96SEvan Quan static int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2461e098bc96SEvan Quan {
2462e098bc96SEvan Quan struct tonga_smumgr *smu_data =
2463e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
2464e098bc96SEvan Quan SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2465e098bc96SEvan Quan uint32_t duty100;
2466e098bc96SEvan Quan uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2467e098bc96SEvan Quan uint16_t fdo_min, slope1, slope2;
2468e098bc96SEvan Quan uint32_t reference_clock;
2469e098bc96SEvan Quan int res;
2470e098bc96SEvan Quan uint64_t tmp64;
2471e098bc96SEvan Quan
2472e098bc96SEvan Quan if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2473e098bc96SEvan Quan PHM_PlatformCaps_MicrocodeFanControl))
2474e098bc96SEvan Quan return 0;
2475e098bc96SEvan Quan
2476e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2477e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2478e098bc96SEvan Quan PHM_PlatformCaps_MicrocodeFanControl);
2479e098bc96SEvan Quan return 0;
2480e098bc96SEvan Quan }
2481e098bc96SEvan Quan
2482e098bc96SEvan Quan if (0 == smu_data->smu7_data.fan_table_start) {
2483e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2484e098bc96SEvan Quan PHM_PlatformCaps_MicrocodeFanControl);
2485e098bc96SEvan Quan return 0;
2486e098bc96SEvan Quan }
2487e098bc96SEvan Quan
2488e098bc96SEvan Quan duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
2489e098bc96SEvan Quan CGS_IND_REG__SMC,
2490e098bc96SEvan Quan CG_FDO_CTRL1, FMAX_DUTY100);
2491e098bc96SEvan Quan
2492e098bc96SEvan Quan if (0 == duty100) {
2493e098bc96SEvan Quan phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2494e098bc96SEvan Quan PHM_PlatformCaps_MicrocodeFanControl);
2495e098bc96SEvan Quan return 0;
2496e098bc96SEvan Quan }
2497e098bc96SEvan Quan
2498e098bc96SEvan Quan tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
2499e098bc96SEvan Quan do_div(tmp64, 10000);
2500e098bc96SEvan Quan fdo_min = (uint16_t)tmp64;
2501e098bc96SEvan Quan
2502e098bc96SEvan Quan t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2503e098bc96SEvan Quan hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2504e098bc96SEvan Quan t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2505e098bc96SEvan Quan hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2506e098bc96SEvan Quan
2507e098bc96SEvan Quan pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2508e098bc96SEvan Quan hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2509e098bc96SEvan Quan pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2510e098bc96SEvan Quan hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2511e098bc96SEvan Quan
2512e098bc96SEvan Quan slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2513e098bc96SEvan Quan slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2514e098bc96SEvan Quan
2515e098bc96SEvan Quan fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
2516e098bc96SEvan Quan fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
2517e098bc96SEvan Quan fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
2518e098bc96SEvan Quan
2519e098bc96SEvan Quan fan_table.Slope1 = cpu_to_be16(slope1);
2520e098bc96SEvan Quan fan_table.Slope2 = cpu_to_be16(slope2);
2521e098bc96SEvan Quan
2522e098bc96SEvan Quan fan_table.FdoMin = cpu_to_be16(fdo_min);
2523e098bc96SEvan Quan
2524e098bc96SEvan Quan fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
2525e098bc96SEvan Quan
2526e098bc96SEvan Quan fan_table.HystUp = cpu_to_be16(1);
2527e098bc96SEvan Quan
2528e098bc96SEvan Quan fan_table.HystSlope = cpu_to_be16(1);
2529e098bc96SEvan Quan
2530e098bc96SEvan Quan fan_table.TempRespLim = cpu_to_be16(5);
2531e098bc96SEvan Quan
2532e098bc96SEvan Quan reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2533e098bc96SEvan Quan
2534e098bc96SEvan Quan fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
2535e098bc96SEvan Quan
2536e098bc96SEvan Quan fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2537e098bc96SEvan Quan
2538e098bc96SEvan Quan fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2539e098bc96SEvan Quan
2540e098bc96SEvan Quan fan_table.FanControl_GL_Flag = 1;
2541e098bc96SEvan Quan
2542e098bc96SEvan Quan res = smu7_copy_bytes_to_smc(hwmgr,
2543e098bc96SEvan Quan smu_data->smu7_data.fan_table_start,
2544e098bc96SEvan Quan (uint8_t *)&fan_table,
2545e098bc96SEvan Quan (uint32_t)sizeof(fan_table),
2546e098bc96SEvan Quan SMC_RAM_END);
2547e098bc96SEvan Quan
254854915feeSAlex Deucher return res;
2549e098bc96SEvan Quan }
2550e098bc96SEvan Quan
2551e098bc96SEvan Quan
tonga_program_mem_timing_parameters(struct pp_hwmgr * hwmgr)2552e098bc96SEvan Quan static int tonga_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2553e098bc96SEvan Quan {
2554e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2555e098bc96SEvan Quan
2556e098bc96SEvan Quan if (data->need_update_smu7_dpm_table &
25574e185502SDeepak R Varma (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK))
2558e098bc96SEvan Quan return tonga_program_memory_timing_parameters(hwmgr);
2559e098bc96SEvan Quan
2560e098bc96SEvan Quan return 0;
2561e098bc96SEvan Quan }
2562e098bc96SEvan Quan
tonga_update_sclk_threshold(struct pp_hwmgr * hwmgr)2563e098bc96SEvan Quan static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2564e098bc96SEvan Quan {
2565e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2566e098bc96SEvan Quan struct tonga_smumgr *smu_data =
2567e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
2568e098bc96SEvan Quan
2569e098bc96SEvan Quan int result = 0;
2570e098bc96SEvan Quan uint32_t low_sclk_interrupt_threshold = 0;
2571e098bc96SEvan Quan
2572e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2573e098bc96SEvan Quan PHM_PlatformCaps_SclkThrottleLowNotification)
2574e098bc96SEvan Quan && (data->low_sclk_interrupt_threshold != 0)) {
2575e098bc96SEvan Quan low_sclk_interrupt_threshold =
2576e098bc96SEvan Quan data->low_sclk_interrupt_threshold;
2577e098bc96SEvan Quan
2578e098bc96SEvan Quan CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2579e098bc96SEvan Quan
2580e098bc96SEvan Quan result = smu7_copy_bytes_to_smc(
2581e098bc96SEvan Quan hwmgr,
2582e098bc96SEvan Quan smu_data->smu7_data.dpm_table_start +
2583e098bc96SEvan Quan offsetof(SMU72_Discrete_DpmTable,
2584e098bc96SEvan Quan LowSclkInterruptThreshold),
2585e098bc96SEvan Quan (uint8_t *)&low_sclk_interrupt_threshold,
2586e098bc96SEvan Quan sizeof(uint32_t),
2587e098bc96SEvan Quan SMC_RAM_END);
2588e098bc96SEvan Quan }
2589e098bc96SEvan Quan
2590e098bc96SEvan Quan result = tonga_update_and_upload_mc_reg_table(hwmgr);
2591e098bc96SEvan Quan
2592e098bc96SEvan Quan PP_ASSERT_WITH_CODE((!result),
2593e098bc96SEvan Quan "Failed to upload MC reg table !",
2594e098bc96SEvan Quan return result);
2595e098bc96SEvan Quan
2596e098bc96SEvan Quan result = tonga_program_mem_timing_parameters(hwmgr);
2597e098bc96SEvan Quan PP_ASSERT_WITH_CODE((result == 0),
2598e098bc96SEvan Quan "Failed to program memory timing parameters !",
2599e098bc96SEvan Quan );
2600e098bc96SEvan Quan
2601e098bc96SEvan Quan return result;
2602e098bc96SEvan Quan }
2603e098bc96SEvan Quan
tonga_get_offsetof(uint32_t type,uint32_t member)2604e098bc96SEvan Quan static uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
2605e098bc96SEvan Quan {
2606e098bc96SEvan Quan switch (type) {
2607e098bc96SEvan Quan case SMU_SoftRegisters:
2608e098bc96SEvan Quan switch (member) {
2609e098bc96SEvan Quan case HandshakeDisables:
2610e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, HandshakeDisables);
2611e098bc96SEvan Quan case VoltageChangeTimeout:
2612e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, VoltageChangeTimeout);
2613e098bc96SEvan Quan case AverageGraphicsActivity:
2614e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
2615e098bc96SEvan Quan case AverageMemoryActivity:
2616e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, AverageMemoryActivity);
2617e098bc96SEvan Quan case PreVBlankGap:
2618e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, PreVBlankGap);
2619e098bc96SEvan Quan case VBlankTimeout:
2620e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, VBlankTimeout);
2621e098bc96SEvan Quan case UcodeLoadStatus:
2622e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, UcodeLoadStatus);
2623e098bc96SEvan Quan case DRAM_LOG_ADDR_H:
2624e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_H);
2625e098bc96SEvan Quan case DRAM_LOG_ADDR_L:
2626e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_L);
2627e098bc96SEvan Quan case DRAM_LOG_PHY_ADDR_H:
2628e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2629e098bc96SEvan Quan case DRAM_LOG_PHY_ADDR_L:
2630e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2631e098bc96SEvan Quan case DRAM_LOG_BUFF_SIZE:
2632e098bc96SEvan Quan return offsetof(SMU72_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2633e098bc96SEvan Quan }
2634e098bc96SEvan Quan break;
2635e098bc96SEvan Quan case SMU_Discrete_DpmTable:
2636e098bc96SEvan Quan switch (member) {
2637e098bc96SEvan Quan case UvdBootLevel:
2638e098bc96SEvan Quan return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
2639e098bc96SEvan Quan case VceBootLevel:
2640e098bc96SEvan Quan return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
2641e098bc96SEvan Quan case LowSclkInterruptThreshold:
2642e098bc96SEvan Quan return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold);
2643e098bc96SEvan Quan }
2644e098bc96SEvan Quan break;
2645e098bc96SEvan Quan }
2646e098bc96SEvan Quan pr_warn("can't get the offset of type %x member %x\n", type, member);
2647e098bc96SEvan Quan return 0;
2648e098bc96SEvan Quan }
2649e098bc96SEvan Quan
tonga_get_mac_definition(uint32_t value)2650e098bc96SEvan Quan static uint32_t tonga_get_mac_definition(uint32_t value)
2651e098bc96SEvan Quan {
2652e098bc96SEvan Quan switch (value) {
2653e098bc96SEvan Quan case SMU_MAX_LEVELS_GRAPHICS:
2654e098bc96SEvan Quan return SMU72_MAX_LEVELS_GRAPHICS;
2655e098bc96SEvan Quan case SMU_MAX_LEVELS_MEMORY:
2656e098bc96SEvan Quan return SMU72_MAX_LEVELS_MEMORY;
2657e098bc96SEvan Quan case SMU_MAX_LEVELS_LINK:
2658e098bc96SEvan Quan return SMU72_MAX_LEVELS_LINK;
2659e098bc96SEvan Quan case SMU_MAX_ENTRIES_SMIO:
2660e098bc96SEvan Quan return SMU72_MAX_ENTRIES_SMIO;
2661e098bc96SEvan Quan case SMU_MAX_LEVELS_VDDC:
2662e098bc96SEvan Quan return SMU72_MAX_LEVELS_VDDC;
2663e098bc96SEvan Quan case SMU_MAX_LEVELS_VDDGFX:
2664e098bc96SEvan Quan return SMU72_MAX_LEVELS_VDDGFX;
2665e098bc96SEvan Quan case SMU_MAX_LEVELS_VDDCI:
2666e098bc96SEvan Quan return SMU72_MAX_LEVELS_VDDCI;
2667e098bc96SEvan Quan case SMU_MAX_LEVELS_MVDD:
2668e098bc96SEvan Quan return SMU72_MAX_LEVELS_MVDD;
2669e098bc96SEvan Quan }
2670e098bc96SEvan Quan pr_warn("can't get the mac value %x\n", value);
2671e098bc96SEvan Quan
2672e098bc96SEvan Quan return 0;
2673e098bc96SEvan Quan }
2674e098bc96SEvan Quan
tonga_update_uvd_smc_table(struct pp_hwmgr * hwmgr)2675e098bc96SEvan Quan static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2676e098bc96SEvan Quan {
2677e098bc96SEvan Quan struct tonga_smumgr *smu_data =
2678e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
2679e098bc96SEvan Quan uint32_t mm_boot_level_offset, mm_boot_level_value;
2680e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
2681e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
2682e098bc96SEvan Quan
2683e098bc96SEvan Quan smu_data->smc_state_table.UvdBootLevel = 0;
2684e098bc96SEvan Quan if (table_info->mm_dep_table->count > 0)
2685e098bc96SEvan Quan smu_data->smc_state_table.UvdBootLevel =
2686e098bc96SEvan Quan (uint8_t) (table_info->mm_dep_table->count - 1);
2687e098bc96SEvan Quan mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2688e098bc96SEvan Quan offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
2689e098bc96SEvan Quan mm_boot_level_offset /= 4;
2690e098bc96SEvan Quan mm_boot_level_offset *= 4;
2691e098bc96SEvan Quan mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2692e098bc96SEvan Quan CGS_IND_REG__SMC, mm_boot_level_offset);
2693e098bc96SEvan Quan mm_boot_level_value &= 0x00FFFFFF;
2694e098bc96SEvan Quan mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2695e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device,
2696e098bc96SEvan Quan CGS_IND_REG__SMC,
2697e098bc96SEvan Quan mm_boot_level_offset, mm_boot_level_value);
2698e098bc96SEvan Quan
2699e098bc96SEvan Quan if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2700e098bc96SEvan Quan PHM_PlatformCaps_UVDDPM) ||
2701e098bc96SEvan Quan phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2702e098bc96SEvan Quan PHM_PlatformCaps_StablePState))
2703e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
2704e098bc96SEvan Quan PPSMC_MSG_UVDDPM_SetEnabledMask,
2705e098bc96SEvan Quan (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2706e098bc96SEvan Quan NULL);
2707e098bc96SEvan Quan return 0;
2708e098bc96SEvan Quan }
2709e098bc96SEvan Quan
tonga_update_vce_smc_table(struct pp_hwmgr * hwmgr)2710e098bc96SEvan Quan static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2711e098bc96SEvan Quan {
2712e098bc96SEvan Quan struct tonga_smumgr *smu_data =
2713e098bc96SEvan Quan (struct tonga_smumgr *)(hwmgr->smu_backend);
2714e098bc96SEvan Quan uint32_t mm_boot_level_offset, mm_boot_level_value;
2715e098bc96SEvan Quan struct phm_ppt_v1_information *table_info =
2716e098bc96SEvan Quan (struct phm_ppt_v1_information *)(hwmgr->pptable);
2717e098bc96SEvan Quan
2718e098bc96SEvan Quan
2719e098bc96SEvan Quan smu_data->smc_state_table.VceBootLevel =
2720e098bc96SEvan Quan (uint8_t) (table_info->mm_dep_table->count - 1);
2721e098bc96SEvan Quan
2722e098bc96SEvan Quan mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2723e098bc96SEvan Quan offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
2724e098bc96SEvan Quan mm_boot_level_offset /= 4;
2725e098bc96SEvan Quan mm_boot_level_offset *= 4;
2726e098bc96SEvan Quan mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2727e098bc96SEvan Quan CGS_IND_REG__SMC, mm_boot_level_offset);
2728e098bc96SEvan Quan mm_boot_level_value &= 0xFF00FFFF;
2729e098bc96SEvan Quan mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2730e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device,
2731e098bc96SEvan Quan CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2732e098bc96SEvan Quan
2733e098bc96SEvan Quan if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2734e098bc96SEvan Quan PHM_PlatformCaps_StablePState))
2735e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
2736e098bc96SEvan Quan PPSMC_MSG_VCEDPM_SetEnabledMask,
2737e098bc96SEvan Quan (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
2738e098bc96SEvan Quan NULL);
2739e098bc96SEvan Quan return 0;
2740e098bc96SEvan Quan }
2741e098bc96SEvan Quan
tonga_update_smc_table(struct pp_hwmgr * hwmgr,uint32_t type)2742e098bc96SEvan Quan static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2743e098bc96SEvan Quan {
2744e098bc96SEvan Quan switch (type) {
2745e098bc96SEvan Quan case SMU_UVD_TABLE:
2746e098bc96SEvan Quan tonga_update_uvd_smc_table(hwmgr);
2747e098bc96SEvan Quan break;
2748e098bc96SEvan Quan case SMU_VCE_TABLE:
2749e098bc96SEvan Quan tonga_update_vce_smc_table(hwmgr);
2750e098bc96SEvan Quan break;
2751e098bc96SEvan Quan default:
2752e098bc96SEvan Quan break;
2753e098bc96SEvan Quan }
2754e098bc96SEvan Quan return 0;
2755e098bc96SEvan Quan }
2756e098bc96SEvan Quan
tonga_process_firmware_header(struct pp_hwmgr * hwmgr)2757e098bc96SEvan Quan static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2758e098bc96SEvan Quan {
2759e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2760e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2761e098bc96SEvan Quan
2762e098bc96SEvan Quan uint32_t tmp;
2763e098bc96SEvan Quan int result;
2764e098bc96SEvan Quan bool error = false;
2765e098bc96SEvan Quan
2766e098bc96SEvan Quan result = smu7_read_smc_sram_dword(hwmgr,
2767e098bc96SEvan Quan SMU72_FIRMWARE_HEADER_LOCATION +
2768e098bc96SEvan Quan offsetof(SMU72_Firmware_Header, DpmTable),
2769e098bc96SEvan Quan &tmp, SMC_RAM_END);
2770e098bc96SEvan Quan
2771e098bc96SEvan Quan if (!result)
2772e098bc96SEvan Quan smu_data->smu7_data.dpm_table_start = tmp;
2773e098bc96SEvan Quan
2774e098bc96SEvan Quan error |= (result != 0);
2775e098bc96SEvan Quan
2776e098bc96SEvan Quan result = smu7_read_smc_sram_dword(hwmgr,
2777e098bc96SEvan Quan SMU72_FIRMWARE_HEADER_LOCATION +
2778e098bc96SEvan Quan offsetof(SMU72_Firmware_Header, SoftRegisters),
2779e098bc96SEvan Quan &tmp, SMC_RAM_END);
2780e098bc96SEvan Quan
2781e098bc96SEvan Quan if (!result) {
2782e098bc96SEvan Quan data->soft_regs_start = tmp;
2783e098bc96SEvan Quan smu_data->smu7_data.soft_regs_start = tmp;
2784e098bc96SEvan Quan }
2785e098bc96SEvan Quan
2786e098bc96SEvan Quan error |= (result != 0);
2787e098bc96SEvan Quan
2788e098bc96SEvan Quan
2789e098bc96SEvan Quan result = smu7_read_smc_sram_dword(hwmgr,
2790e098bc96SEvan Quan SMU72_FIRMWARE_HEADER_LOCATION +
2791e098bc96SEvan Quan offsetof(SMU72_Firmware_Header, mcRegisterTable),
2792e098bc96SEvan Quan &tmp, SMC_RAM_END);
2793e098bc96SEvan Quan
2794e098bc96SEvan Quan if (!result)
2795e098bc96SEvan Quan smu_data->smu7_data.mc_reg_table_start = tmp;
2796e098bc96SEvan Quan
2797e098bc96SEvan Quan result = smu7_read_smc_sram_dword(hwmgr,
2798e098bc96SEvan Quan SMU72_FIRMWARE_HEADER_LOCATION +
2799e098bc96SEvan Quan offsetof(SMU72_Firmware_Header, FanTable),
2800e098bc96SEvan Quan &tmp, SMC_RAM_END);
2801e098bc96SEvan Quan
2802e098bc96SEvan Quan if (!result)
2803e098bc96SEvan Quan smu_data->smu7_data.fan_table_start = tmp;
2804e098bc96SEvan Quan
2805e098bc96SEvan Quan error |= (result != 0);
2806e098bc96SEvan Quan
2807e098bc96SEvan Quan result = smu7_read_smc_sram_dword(hwmgr,
2808e098bc96SEvan Quan SMU72_FIRMWARE_HEADER_LOCATION +
2809e098bc96SEvan Quan offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
2810e098bc96SEvan Quan &tmp, SMC_RAM_END);
2811e098bc96SEvan Quan
2812e098bc96SEvan Quan if (!result)
2813e098bc96SEvan Quan smu_data->smu7_data.arb_table_start = tmp;
2814e098bc96SEvan Quan
2815e098bc96SEvan Quan error |= (result != 0);
2816e098bc96SEvan Quan
2817e098bc96SEvan Quan result = smu7_read_smc_sram_dword(hwmgr,
2818e098bc96SEvan Quan SMU72_FIRMWARE_HEADER_LOCATION +
2819e098bc96SEvan Quan offsetof(SMU72_Firmware_Header, Version),
2820e098bc96SEvan Quan &tmp, SMC_RAM_END);
2821e098bc96SEvan Quan
2822e098bc96SEvan Quan if (!result)
2823e098bc96SEvan Quan hwmgr->microcode_version_info.SMC = tmp;
2824e098bc96SEvan Quan
2825e098bc96SEvan Quan error |= (result != 0);
2826e098bc96SEvan Quan
2827e098bc96SEvan Quan return error ? 1 : 0;
2828e098bc96SEvan Quan }
2829e098bc96SEvan Quan
2830e098bc96SEvan Quan /*---------------------------MC----------------------------*/
2831e098bc96SEvan Quan
tonga_get_memory_modile_index(struct pp_hwmgr * hwmgr)2832e098bc96SEvan Quan static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2833e098bc96SEvan Quan {
2834e098bc96SEvan Quan return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2835e098bc96SEvan Quan }
2836e098bc96SEvan Quan
tonga_check_s0_mc_reg_index(uint16_t in_reg,uint16_t * out_reg)2837e098bc96SEvan Quan static bool tonga_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
2838e098bc96SEvan Quan {
2839e098bc96SEvan Quan bool result = true;
2840e098bc96SEvan Quan
2841e098bc96SEvan Quan switch (in_reg) {
2842e098bc96SEvan Quan case mmMC_SEQ_RAS_TIMING:
2843e098bc96SEvan Quan *out_reg = mmMC_SEQ_RAS_TIMING_LP;
2844e098bc96SEvan Quan break;
2845e098bc96SEvan Quan
2846e098bc96SEvan Quan case mmMC_SEQ_DLL_STBY:
2847e098bc96SEvan Quan *out_reg = mmMC_SEQ_DLL_STBY_LP;
2848e098bc96SEvan Quan break;
2849e098bc96SEvan Quan
2850e098bc96SEvan Quan case mmMC_SEQ_G5PDX_CMD0:
2851e098bc96SEvan Quan *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
2852e098bc96SEvan Quan break;
2853e098bc96SEvan Quan
2854e098bc96SEvan Quan case mmMC_SEQ_G5PDX_CMD1:
2855e098bc96SEvan Quan *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
2856e098bc96SEvan Quan break;
2857e098bc96SEvan Quan
2858e098bc96SEvan Quan case mmMC_SEQ_G5PDX_CTRL:
2859e098bc96SEvan Quan *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
2860e098bc96SEvan Quan break;
2861e098bc96SEvan Quan
2862e098bc96SEvan Quan case mmMC_SEQ_CAS_TIMING:
2863e098bc96SEvan Quan *out_reg = mmMC_SEQ_CAS_TIMING_LP;
2864e098bc96SEvan Quan break;
2865e098bc96SEvan Quan
2866e098bc96SEvan Quan case mmMC_SEQ_MISC_TIMING:
2867e098bc96SEvan Quan *out_reg = mmMC_SEQ_MISC_TIMING_LP;
2868e098bc96SEvan Quan break;
2869e098bc96SEvan Quan
2870e098bc96SEvan Quan case mmMC_SEQ_MISC_TIMING2:
2871e098bc96SEvan Quan *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
2872e098bc96SEvan Quan break;
2873e098bc96SEvan Quan
2874e098bc96SEvan Quan case mmMC_SEQ_PMG_DVS_CMD:
2875e098bc96SEvan Quan *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
2876e098bc96SEvan Quan break;
2877e098bc96SEvan Quan
2878e098bc96SEvan Quan case mmMC_SEQ_PMG_DVS_CTL:
2879e098bc96SEvan Quan *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
2880e098bc96SEvan Quan break;
2881e098bc96SEvan Quan
2882e098bc96SEvan Quan case mmMC_SEQ_RD_CTL_D0:
2883e098bc96SEvan Quan *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
2884e098bc96SEvan Quan break;
2885e098bc96SEvan Quan
2886e098bc96SEvan Quan case mmMC_SEQ_RD_CTL_D1:
2887e098bc96SEvan Quan *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
2888e098bc96SEvan Quan break;
2889e098bc96SEvan Quan
2890e098bc96SEvan Quan case mmMC_SEQ_WR_CTL_D0:
2891e098bc96SEvan Quan *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
2892e098bc96SEvan Quan break;
2893e098bc96SEvan Quan
2894e098bc96SEvan Quan case mmMC_SEQ_WR_CTL_D1:
2895e098bc96SEvan Quan *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
2896e098bc96SEvan Quan break;
2897e098bc96SEvan Quan
2898e098bc96SEvan Quan case mmMC_PMG_CMD_EMRS:
2899e098bc96SEvan Quan *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
2900e098bc96SEvan Quan break;
2901e098bc96SEvan Quan
2902e098bc96SEvan Quan case mmMC_PMG_CMD_MRS:
2903e098bc96SEvan Quan *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
2904e098bc96SEvan Quan break;
2905e098bc96SEvan Quan
2906e098bc96SEvan Quan case mmMC_PMG_CMD_MRS1:
2907e098bc96SEvan Quan *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
2908e098bc96SEvan Quan break;
2909e098bc96SEvan Quan
2910e098bc96SEvan Quan case mmMC_SEQ_PMG_TIMING:
2911e098bc96SEvan Quan *out_reg = mmMC_SEQ_PMG_TIMING_LP;
2912e098bc96SEvan Quan break;
2913e098bc96SEvan Quan
2914e098bc96SEvan Quan case mmMC_PMG_CMD_MRS2:
2915e098bc96SEvan Quan *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
2916e098bc96SEvan Quan break;
2917e098bc96SEvan Quan
2918e098bc96SEvan Quan case mmMC_SEQ_WR_CTL_2:
2919e098bc96SEvan Quan *out_reg = mmMC_SEQ_WR_CTL_2_LP;
2920e098bc96SEvan Quan break;
2921e098bc96SEvan Quan
2922e098bc96SEvan Quan default:
2923e098bc96SEvan Quan result = false;
2924e098bc96SEvan Quan break;
2925e098bc96SEvan Quan }
2926e098bc96SEvan Quan
2927e098bc96SEvan Quan return result;
2928e098bc96SEvan Quan }
2929e098bc96SEvan Quan
tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table * table)2930e098bc96SEvan Quan static int tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table *table)
2931e098bc96SEvan Quan {
2932e098bc96SEvan Quan uint32_t i;
2933e098bc96SEvan Quan uint16_t address;
2934e098bc96SEvan Quan
2935e098bc96SEvan Quan for (i = 0; i < table->last; i++) {
2936e098bc96SEvan Quan table->mc_reg_address[i].s0 =
2937e098bc96SEvan Quan tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,
2938e098bc96SEvan Quan &address) ?
2939e098bc96SEvan Quan address :
2940e098bc96SEvan Quan table->mc_reg_address[i].s1;
2941e098bc96SEvan Quan }
2942e098bc96SEvan Quan return 0;
2943e098bc96SEvan Quan }
2944e098bc96SEvan Quan
tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table * table,struct tonga_mc_reg_table * ni_table)2945e098bc96SEvan Quan static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2946e098bc96SEvan Quan struct tonga_mc_reg_table *ni_table)
2947e098bc96SEvan Quan {
2948e098bc96SEvan Quan uint8_t i, j;
2949e098bc96SEvan Quan
2950e098bc96SEvan Quan PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2951e098bc96SEvan Quan "Invalid VramInfo table.", return -EINVAL);
2952e098bc96SEvan Quan PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
2953e098bc96SEvan Quan "Invalid VramInfo table.", return -EINVAL);
2954e098bc96SEvan Quan
2955e098bc96SEvan Quan for (i = 0; i < table->last; i++)
2956e098bc96SEvan Quan ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2957e098bc96SEvan Quan
2958e098bc96SEvan Quan ni_table->last = table->last;
2959e098bc96SEvan Quan
2960e098bc96SEvan Quan for (i = 0; i < table->num_entries; i++) {
2961e098bc96SEvan Quan ni_table->mc_reg_table_entry[i].mclk_max =
2962e098bc96SEvan Quan table->mc_reg_table_entry[i].mclk_max;
2963e098bc96SEvan Quan for (j = 0; j < table->last; j++) {
2964e098bc96SEvan Quan ni_table->mc_reg_table_entry[i].mc_data[j] =
2965e098bc96SEvan Quan table->mc_reg_table_entry[i].mc_data[j];
2966e098bc96SEvan Quan }
2967e098bc96SEvan Quan }
2968e098bc96SEvan Quan
2969e098bc96SEvan Quan ni_table->num_entries = table->num_entries;
2970e098bc96SEvan Quan
2971e098bc96SEvan Quan return 0;
2972e098bc96SEvan Quan }
2973e098bc96SEvan Quan
tonga_set_mc_special_registers(struct pp_hwmgr * hwmgr,struct tonga_mc_reg_table * table)2974e098bc96SEvan Quan static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr,
2975e098bc96SEvan Quan struct tonga_mc_reg_table *table)
2976e098bc96SEvan Quan {
2977e098bc96SEvan Quan uint8_t i, j, k;
2978e098bc96SEvan Quan uint32_t temp_reg;
2979e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2980e098bc96SEvan Quan
2981e098bc96SEvan Quan for (i = 0, j = table->last; i < table->last; i++) {
2982e098bc96SEvan Quan PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2983e098bc96SEvan Quan "Invalid VramInfo table.", return -EINVAL);
2984e098bc96SEvan Quan
2985e098bc96SEvan Quan switch (table->mc_reg_address[i].s1) {
2986e098bc96SEvan Quan
2987e098bc96SEvan Quan case mmMC_SEQ_MISC1:
2988e098bc96SEvan Quan temp_reg = cgs_read_register(hwmgr->device,
2989e098bc96SEvan Quan mmMC_PMG_CMD_EMRS);
2990e098bc96SEvan Quan table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2991e098bc96SEvan Quan table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
2992e098bc96SEvan Quan for (k = 0; k < table->num_entries; k++) {
2993e098bc96SEvan Quan table->mc_reg_table_entry[k].mc_data[j] =
2994e098bc96SEvan Quan ((temp_reg & 0xffff0000)) |
2995e098bc96SEvan Quan ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2996e098bc96SEvan Quan }
2997e098bc96SEvan Quan j++;
2998e098bc96SEvan Quan
2999e098bc96SEvan Quan PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3000e098bc96SEvan Quan "Invalid VramInfo table.", return -EINVAL);
3001e098bc96SEvan Quan temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3002e098bc96SEvan Quan table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3003e098bc96SEvan Quan table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3004e098bc96SEvan Quan for (k = 0; k < table->num_entries; k++) {
3005e098bc96SEvan Quan table->mc_reg_table_entry[k].mc_data[j] =
3006e098bc96SEvan Quan (temp_reg & 0xffff0000) |
3007e098bc96SEvan Quan (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3008e098bc96SEvan Quan
3009e098bc96SEvan Quan if (!data->is_memory_gddr5)
3010e098bc96SEvan Quan table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3011e098bc96SEvan Quan }
3012e098bc96SEvan Quan j++;
3013e098bc96SEvan Quan
3014e098bc96SEvan Quan if (!data->is_memory_gddr5) {
3015e098bc96SEvan Quan PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3016e098bc96SEvan Quan "Invalid VramInfo table.", return -EINVAL);
3017e098bc96SEvan Quan table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3018e098bc96SEvan Quan table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3019e098bc96SEvan Quan for (k = 0; k < table->num_entries; k++)
3020e098bc96SEvan Quan table->mc_reg_table_entry[k].mc_data[j] =
3021e098bc96SEvan Quan (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3022e098bc96SEvan Quan j++;
3023e098bc96SEvan Quan }
3024e098bc96SEvan Quan
3025e098bc96SEvan Quan break;
3026e098bc96SEvan Quan
3027e098bc96SEvan Quan case mmMC_SEQ_RESERVE_M:
3028e098bc96SEvan Quan temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3029e098bc96SEvan Quan table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3030e098bc96SEvan Quan table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3031e098bc96SEvan Quan for (k = 0; k < table->num_entries; k++) {
3032e098bc96SEvan Quan table->mc_reg_table_entry[k].mc_data[j] =
3033e098bc96SEvan Quan (temp_reg & 0xffff0000) |
3034e098bc96SEvan Quan (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3035e098bc96SEvan Quan }
3036e098bc96SEvan Quan j++;
3037e098bc96SEvan Quan break;
3038e098bc96SEvan Quan
3039e098bc96SEvan Quan default:
3040e098bc96SEvan Quan break;
3041e098bc96SEvan Quan }
3042e098bc96SEvan Quan
3043e098bc96SEvan Quan }
3044e098bc96SEvan Quan
3045e098bc96SEvan Quan table->last = j;
3046e098bc96SEvan Quan
3047e098bc96SEvan Quan return 0;
3048e098bc96SEvan Quan }
3049e098bc96SEvan Quan
tonga_set_valid_flag(struct tonga_mc_reg_table * table)3050e098bc96SEvan Quan static int tonga_set_valid_flag(struct tonga_mc_reg_table *table)
3051e098bc96SEvan Quan {
3052e098bc96SEvan Quan uint8_t i, j;
3053e098bc96SEvan Quan
3054e098bc96SEvan Quan for (i = 0; i < table->last; i++) {
3055e098bc96SEvan Quan for (j = 1; j < table->num_entries; j++) {
3056e098bc96SEvan Quan if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3057e098bc96SEvan Quan table->mc_reg_table_entry[j].mc_data[i]) {
3058e098bc96SEvan Quan table->validflag |= (1<<i);
3059e098bc96SEvan Quan break;
3060e098bc96SEvan Quan }
3061e098bc96SEvan Quan }
3062e098bc96SEvan Quan }
3063e098bc96SEvan Quan
3064e098bc96SEvan Quan return 0;
3065e098bc96SEvan Quan }
3066e098bc96SEvan Quan
tonga_initialize_mc_reg_table(struct pp_hwmgr * hwmgr)3067e098bc96SEvan Quan static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
3068e098bc96SEvan Quan {
3069e098bc96SEvan Quan int result;
3070e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
3071e098bc96SEvan Quan pp_atomctrl_mc_reg_table *table;
3072e098bc96SEvan Quan struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table;
3073e098bc96SEvan Quan uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
3074e098bc96SEvan Quan
3075e098bc96SEvan Quan table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
3076e098bc96SEvan Quan
3077e098bc96SEvan Quan if (table == NULL)
3078e098bc96SEvan Quan return -ENOMEM;
3079e098bc96SEvan Quan
3080e098bc96SEvan Quan /* Program additional LP registers that are no longer programmed by VBIOS */
3081e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
3082e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
3083e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
3084e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
3085e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP,
3086e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
3087e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP,
3088e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
3089e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP,
3090e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
3091e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP,
3092e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
3093e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP,
3094e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
3095e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP,
3096e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
3097e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP,
3098e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
3099e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
3100e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
3101e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP,
3102e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
3103e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP,
3104e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
3105e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP,
3106e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
3107e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP,
3108e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
3109e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
3110e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
3111e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
3112e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
3113e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
3114e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
3115e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
3116e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
3117e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP,
3118e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
3119e098bc96SEvan Quan cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
3120e098bc96SEvan Quan cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
3121e098bc96SEvan Quan
3122e098bc96SEvan Quan result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
3123e098bc96SEvan Quan
3124e098bc96SEvan Quan if (!result)
3125e098bc96SEvan Quan result = tonga_copy_vbios_smc_reg_table(table, ni_table);
3126e098bc96SEvan Quan
3127e098bc96SEvan Quan if (!result) {
3128e098bc96SEvan Quan tonga_set_s0_mc_reg_index(ni_table);
3129e098bc96SEvan Quan result = tonga_set_mc_special_registers(hwmgr, ni_table);
3130e098bc96SEvan Quan }
3131e098bc96SEvan Quan
3132e098bc96SEvan Quan if (!result)
3133e098bc96SEvan Quan tonga_set_valid_flag(ni_table);
3134e098bc96SEvan Quan
3135e098bc96SEvan Quan kfree(table);
3136e098bc96SEvan Quan
3137e098bc96SEvan Quan return result;
3138e098bc96SEvan Quan }
3139e098bc96SEvan Quan
tonga_is_dpm_running(struct pp_hwmgr * hwmgr)3140e098bc96SEvan Quan static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
3141e098bc96SEvan Quan {
3142e098bc96SEvan Quan return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
3143e098bc96SEvan Quan CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
3144e098bc96SEvan Quan ? true : false;
3145e098bc96SEvan Quan }
3146e098bc96SEvan Quan
tonga_update_dpm_settings(struct pp_hwmgr * hwmgr,void * profile_setting)3147e098bc96SEvan Quan static int tonga_update_dpm_settings(struct pp_hwmgr *hwmgr,
3148e098bc96SEvan Quan void *profile_setting)
3149e098bc96SEvan Quan {
3150e098bc96SEvan Quan struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3151e098bc96SEvan Quan struct tonga_smumgr *smu_data = (struct tonga_smumgr *)
3152e098bc96SEvan Quan (hwmgr->smu_backend);
3153e098bc96SEvan Quan struct profile_mode_setting *setting;
3154e098bc96SEvan Quan struct SMU72_Discrete_GraphicsLevel *levels =
3155e098bc96SEvan Quan smu_data->smc_state_table.GraphicsLevel;
3156e098bc96SEvan Quan uint32_t array = smu_data->smu7_data.dpm_table_start +
3157e098bc96SEvan Quan offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
3158e098bc96SEvan Quan
3159e098bc96SEvan Quan uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
3160e098bc96SEvan Quan offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
3161e098bc96SEvan Quan struct SMU72_Discrete_MemoryLevel *mclk_levels =
3162e098bc96SEvan Quan smu_data->smc_state_table.MemoryLevel;
3163e098bc96SEvan Quan uint32_t i;
3164e098bc96SEvan Quan uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
3165e098bc96SEvan Quan
3166e098bc96SEvan Quan if (profile_setting == NULL)
3167e098bc96SEvan Quan return -EINVAL;
3168e098bc96SEvan Quan
3169e098bc96SEvan Quan setting = (struct profile_mode_setting *)profile_setting;
3170e098bc96SEvan Quan
3171e098bc96SEvan Quan if (setting->bupdate_sclk) {
3172e098bc96SEvan Quan if (!data->sclk_dpm_key_disabled)
3173e098bc96SEvan Quan smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
3174e098bc96SEvan Quan for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
3175e098bc96SEvan Quan if (levels[i].ActivityLevel !=
3176e098bc96SEvan Quan cpu_to_be16(setting->sclk_activity)) {
3177e098bc96SEvan Quan levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
3178e098bc96SEvan Quan
3179e098bc96SEvan Quan clk_activity_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
3180e098bc96SEvan Quan + offsetof(SMU72_Discrete_GraphicsLevel, ActivityLevel);
3181e098bc96SEvan Quan offset = clk_activity_offset & ~0x3;
3182e098bc96SEvan Quan tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3183e098bc96SEvan Quan tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
3184e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
3185e098bc96SEvan Quan
3186e098bc96SEvan Quan }
3187e098bc96SEvan Quan if (levels[i].UpHyst != setting->sclk_up_hyst ||
3188e098bc96SEvan Quan levels[i].DownHyst != setting->sclk_down_hyst) {
3189e098bc96SEvan Quan levels[i].UpHyst = setting->sclk_up_hyst;
3190e098bc96SEvan Quan levels[i].DownHyst = setting->sclk_down_hyst;
3191e098bc96SEvan Quan up_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
3192e098bc96SEvan Quan + offsetof(SMU72_Discrete_GraphicsLevel, UpHyst);
3193e098bc96SEvan Quan down_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
3194e098bc96SEvan Quan + offsetof(SMU72_Discrete_GraphicsLevel, DownHyst);
3195e098bc96SEvan Quan offset = up_hyst_offset & ~0x3;
3196e098bc96SEvan Quan tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3197e098bc96SEvan Quan tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
3198e098bc96SEvan Quan tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
3199e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
3200e098bc96SEvan Quan }
3201e098bc96SEvan Quan }
3202e098bc96SEvan Quan if (!data->sclk_dpm_key_disabled)
3203e098bc96SEvan Quan smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
3204e098bc96SEvan Quan }
3205e098bc96SEvan Quan
3206e098bc96SEvan Quan if (setting->bupdate_mclk) {
3207e098bc96SEvan Quan if (!data->mclk_dpm_key_disabled)
3208e098bc96SEvan Quan smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
3209e098bc96SEvan Quan for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
3210e098bc96SEvan Quan if (mclk_levels[i].ActivityLevel !=
3211e098bc96SEvan Quan cpu_to_be16(setting->mclk_activity)) {
3212e098bc96SEvan Quan mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
3213e098bc96SEvan Quan
3214e098bc96SEvan Quan clk_activity_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
3215e098bc96SEvan Quan + offsetof(SMU72_Discrete_MemoryLevel, ActivityLevel);
3216e098bc96SEvan Quan offset = clk_activity_offset & ~0x3;
3217e098bc96SEvan Quan tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3218e098bc96SEvan Quan tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
3219e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
3220e098bc96SEvan Quan
3221e098bc96SEvan Quan }
3222e098bc96SEvan Quan if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
3223e098bc96SEvan Quan mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
3224e098bc96SEvan Quan mclk_levels[i].UpHyst = setting->mclk_up_hyst;
3225e098bc96SEvan Quan mclk_levels[i].DownHyst = setting->mclk_down_hyst;
3226e098bc96SEvan Quan up_hyst_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
3227e098bc96SEvan Quan + offsetof(SMU72_Discrete_MemoryLevel, UpHyst);
3228e098bc96SEvan Quan down_hyst_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
3229e098bc96SEvan Quan + offsetof(SMU72_Discrete_MemoryLevel, DownHyst);
3230e098bc96SEvan Quan offset = up_hyst_offset & ~0x3;
3231e098bc96SEvan Quan tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3232e098bc96SEvan Quan tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
3233e098bc96SEvan Quan tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
3234e098bc96SEvan Quan cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
3235e098bc96SEvan Quan }
3236e098bc96SEvan Quan }
3237e098bc96SEvan Quan if (!data->mclk_dpm_key_disabled)
3238e098bc96SEvan Quan smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);
3239e098bc96SEvan Quan }
3240e098bc96SEvan Quan return 0;
3241e098bc96SEvan Quan }
3242e098bc96SEvan Quan
3243e098bc96SEvan Quan const struct pp_smumgr_func tonga_smu_funcs = {
3244e098bc96SEvan Quan .name = "tonga_smu",
3245e098bc96SEvan Quan .smu_init = &tonga_smu_init,
3246e098bc96SEvan Quan .smu_fini = &smu7_smu_fini,
3247e098bc96SEvan Quan .start_smu = &tonga_start_smu,
3248e098bc96SEvan Quan .check_fw_load_finish = &smu7_check_fw_load_finish,
3249e098bc96SEvan Quan .request_smu_load_fw = &smu7_request_smu_load_fw,
3250e098bc96SEvan Quan .request_smu_load_specific_fw = NULL,
3251e098bc96SEvan Quan .send_msg_to_smc = &smu7_send_msg_to_smc,
3252e098bc96SEvan Quan .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
3253e098bc96SEvan Quan .get_argument = smu7_get_argument,
3254e098bc96SEvan Quan .download_pptable_settings = NULL,
3255e098bc96SEvan Quan .upload_pptable_settings = NULL,
3256e098bc96SEvan Quan .update_smc_table = tonga_update_smc_table,
3257e098bc96SEvan Quan .get_offsetof = tonga_get_offsetof,
3258e098bc96SEvan Quan .process_firmware_header = tonga_process_firmware_header,
3259e098bc96SEvan Quan .init_smc_table = tonga_init_smc_table,
3260e098bc96SEvan Quan .update_sclk_threshold = tonga_update_sclk_threshold,
3261e098bc96SEvan Quan .thermal_setup_fan_table = tonga_thermal_setup_fan_table,
3262e098bc96SEvan Quan .populate_all_graphic_levels = tonga_populate_all_graphic_levels,
3263e098bc96SEvan Quan .populate_all_memory_levels = tonga_populate_all_memory_levels,
3264e098bc96SEvan Quan .get_mac_definition = tonga_get_mac_definition,
3265e098bc96SEvan Quan .initialize_mc_reg_table = tonga_initialize_mc_reg_table,
3266e098bc96SEvan Quan .is_dpm_running = tonga_is_dpm_running,
3267e098bc96SEvan Quan .update_dpm_settings = tonga_update_dpm_settings,
3268e098bc96SEvan Quan };
3269