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Searched refs:dpm (Results 1 – 25 of 38) sorted by relevance

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/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dlegacy_dpm.c127 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
129 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
131 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
143 for (i = 0; i < adev->pm.dpm.num_ps; i++) in amdgpu_pm_print_power_states()
144 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); in amdgpu_pm_print_power_states()
172 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in amdgpu_get_platform_caps()
173 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in amdgpu_get_platform_caps()
174 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in amdgpu_get_platform_caps()
242 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in amdgpu_parse_extended_power_table()
243 adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in amdgpu_parse_extended_power_table()
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H A Dsi_dpm.c1854 struct si_power_info *pi = adev->pm.dpm.priv; in si_get_pi()
1927 u32 p_limit1 = adev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1928 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1956 struct rv7xx_power_info *pi = adev->pm.dpm.priv; in rv770_get_pi()
1963 struct ni_power_info *pi = adev->pm.dpm.priv; in ni_get_pi()
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2226 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
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H A Dkv_dpm.c77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
369 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
793 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
895 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
968 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
1029 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1095 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1154 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1221 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
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H A DMakefile23 AMD_LEGACYDPM_PATH = ../pm/legacy-dpm
/linux/drivers/gpu/drm/radeon/
H A Dr600_dpm.c145 if (rps == rdev->pm.dpm.current_ps) in r600_dpm_print_ps_status()
147 if (rps == rdev->pm.dpm.requested_ps) in r600_dpm_print_ps_status()
149 if (rps == rdev->pm.dpm.boot_ps) in r600_dpm_print_ps_status()
756 rdev->pm.dpm.thermal.min_temp = low_temp; in r600_set_thermal_temperature_range()
757 rdev->pm.dpm.thermal.max_temp = high_temp; in r600_set_thermal_temperature_range()
856 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in r600_get_platform_caps()
857 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in r600_get_platform_caps()
858 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in r600_get_platform_caps()
893 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in r600_parse_extended_power_table()
894 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in r600_parse_extended_power_table()
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H A Dradeon_pm.c80 rdev->pm.dpm.ac_power = true; in radeon_pm_acpi_event_handler()
82 rdev->pm.dpm.ac_power = false; in radeon_pm_acpi_event_handler()
84 if (rdev->asic->dpm.enable_bapm) in radeon_pm_acpi_event_handler()
85 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); in radeon_pm_acpi_event_handler()
472 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; in radeon_get_dpm_state()
489 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; in radeon_set_dpm_state()
491 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in radeon_set_dpm_state()
493 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; in radeon_set_dpm_state()
516 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; in radeon_get_dpm_forced_performance_level()
553 if (rdev->asic->dpm.force_performance_level) { in radeon_set_dpm_forced_performance_level()
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H A Dbtc_dpm.c1201 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
1208 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
1251 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1255 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
1256 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
1258 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
1262 rdev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
1289 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
1291 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
1295 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
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H A Dci_dpm.c169 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
254 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
256 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
258 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
259 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
262 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
263 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
264 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
265 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
266 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
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H A Dsi_dpm.c1701 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1775 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1776 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
2066 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2069 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2072 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2073 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2075 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2076 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2077 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
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H A Dkv_dpm.c152 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi()
398 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
420 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
561 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
663 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
736 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
797 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
863 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
922 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1120 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in kv_dpm_enable()
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H A Drv6xx_dpm.c45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi()
921 rdev->pm.dpm.voltage_response_time, in rv6xx_program_voltage_timing_parameters()
925 rdev->pm.dpm.backbias_response_time, in rv6xx_program_voltage_timing_parameters()
1185 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv6xx_program_display_gap()
1188 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv6xx_program_display_gap()
1298 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); in rv6xx_step_sw_voltage()
1548 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_enable()
1553 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_enable()
1615 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_disable()
1633 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_disable()
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H A Dni_dpm.c728 struct ni_power_info *pi = rdev->pm.dpm.priv; in ni_get_pi()
795 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ni_apply_state_adjust_rules()
801 if (rdev->pm.dpm.ac_power) in ni_apply_state_adjust_rules()
802 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ni_apply_state_adjust_rules()
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ni_apply_state_adjust_rules()
806 if (rdev->pm.dpm.ac_power == false) { in ni_apply_state_adjust_rules()
873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
876 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ni_apply_state_adjust_rules()
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ni_apply_state_adjust_rules()
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in ni_apply_state_adjust_rules()
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H A Drs780_dpm.c44 struct igp_power_info *pi = rdev->pm.dpm.priv; in rs780_get_pi()
380 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); in rs780_force_voltage()
407 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); in rs780_force_fbdiv()
600 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rs780_dpm_enable()
652 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in rs780_dpm_set_power_state()
653 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; in rs780_dpm_set_power_state()
742 rdev->pm.dpm.boot_ps = rps; in rs780_parse_pplib_non_clock_info()
744 rdev->pm.dpm.uvd_ps = rps; in rs780_parse_pplib_non_clock_info()
807 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates, in rs780_parse_power_table()
810 if (!rdev->pm.dpm.ps) in rs780_parse_power_table()
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H A Dtrinity_dpm.c309 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi()
1013 rdev->pm.dpm.thermal.min_temp = low_temp; in trinity_set_thermal_temperature_range()
1014 rdev->pm.dpm.thermal.max_temp = high_temp; in trinity_set_thermal_temperature_range()
1076 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_enable()
1124 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_disable()
1179 rdev->pm.dpm.forced_level = level; in trinity_dpm_force_performance_level()
1187 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in trinity_dpm_pre_set_power_state()
1208 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power); in trinity_dpm_set_power_state()
1462 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in trinity_get_vce_clock_voltage()
1499 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; in trinity_apply_state_adjust_rules()
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H A Drv770_dpm.c58 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi()
65 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi()
1192 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) { in rv770_init_smc_table()
1195 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT) in rv770_init_smc_table()
1198 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT) in rv770_init_smc_table()
1202 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in rv770_init_smc_table()
1348 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv770_program_display_gap()
1351 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv770_program_display_gap()
1500 rdev->pm.dpm.forced_level = level; in rv770_dpm_force_performance_level()
1709 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in rv770_program_response_times()
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H A Dsumo_dpm.c81 struct sumo_power_info *pi = rdev->pm.dpm.priv; in sumo_get_pi()
1172 rdev->pm.dpm.thermal.min_temp = low_temp; in sumo_set_thermal_temperature_range()
1173 rdev->pm.dpm.thermal.max_temp = high_temp; in sumo_set_thermal_temperature_range()
1230 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in sumo_dpm_enable()
1275 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in sumo_dpm_disable()
1281 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in sumo_dpm_pre_set_power_state()
1420 rdev->pm.dpm.boot_ps = rps; in sumo_parse_pplib_non_clock_info()
1424 rdev->pm.dpm.uvd_ps = rps; in sumo_parse_pplib_non_clock_info()
1482 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in sumo_parse_power_table()
1485 if (!rdev->pm.dpm.ps) in sumo_parse_power_table()
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H A Dcypress_dpm.c1638 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in cypress_init_smc_table()
1641 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in cypress_init_smc_table()
1644 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in cypress_init_smc_table()
1751 if (rdev->pm.dpm.new_active_crtc_count > 0) in cypress_program_display_gap()
1756 if (rdev->pm.dpm.new_active_crtc_count > 1) in cypress_program_display_gap()
1766 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in cypress_program_display_gap()
1767 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in cypress_program_display_gap()
1770 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in cypress_program_display_gap()
1783 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in cypress_program_display_gap()
1810 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in cypress_dpm_enable()
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H A Dradeon.h1646 struct radeon_dpm dpm; member
1984 } dpm; member
2765 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2766 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2767 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2768 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2769 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2770 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2771 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2772 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
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H A Dradeon_uvd.c866 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, in radeon_uvd_idle_work_handler()
867 &rdev->pm.dpm.hd); in radeon_uvd_idle_work_handler()
888 if ((rdev->pm.dpm.sd != sd) || in radeon_uvd_note_usage()
889 (rdev->pm.dpm.hd != hd)) { in radeon_uvd_note_usage()
890 rdev->pm.dpm.sd = sd; in radeon_uvd_note_usage()
891 rdev->pm.dpm.hd = hd; in radeon_uvd_note_usage()
H A Dradeon_asic.c1084 .dpm = {
1177 .dpm = {
1283 .dpm = {
1403 .dpm = {
1497 .dpm = {
1591 .dpm = {
1739 .dpm = {
1860 .dpm = {
1998 .dpm = {
2168 .dpm = {
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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhardwaremanager.c260 adev->pm.dpm.thermal.min_temp = range.min; in phm_start_thermal_controller()
261 adev->pm.dpm.thermal.max_temp = range.max; in phm_start_thermal_controller()
262 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max; in phm_start_thermal_controller()
263 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min; in phm_start_thermal_controller()
264 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max; in phm_start_thermal_controller()
265 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max; in phm_start_thermal_controller()
266 adev->pm.dpm.thermal.min_mem_temp = range.mem_min; in phm_start_thermal_controller()
267 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max; in phm_start_thermal_controller()
268 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max; in phm_start_thermal_controller()
269 adev->pm.dpm.thermal.sw_ctf_threshold = range.sw_ctf_threshold; in phm_start_thermal_controller()
/linux/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm_internal.c36 adev->pm.dpm.new_active_crtcs = 0; in amdgpu_dpm_get_active_displays()
37 adev->pm.dpm.new_active_crtc_count = 0; in amdgpu_dpm_get_active_displays()
43 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); in amdgpu_dpm_get_active_displays()
44 adev->pm.dpm.new_active_crtc_count++; in amdgpu_dpm_get_active_displays()
H A DMakefile37 -I$(FULL_AMD_PATH)/pm/legacy-dpm
41 PM_LIBS = swsmu powerplay legacy-dpm
H A Damdgpu_dpm.c567 adev->pm.dpm.uvd_active = true; in amdgpu_dpm_enable_uvd()
568 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; in amdgpu_dpm_enable_uvd()
570 adev->pm.dpm.uvd_active = false; in amdgpu_dpm_enable_uvd()
601 adev->pm.dpm.vce_active = true; in amdgpu_dpm_enable_vce()
603 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; in amdgpu_dpm_enable_vce()
605 adev->pm.dpm.vce_active = false; in amdgpu_dpm_enable_vce()
943 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
950 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
960 adev->pm.dpm.user_state = state; in amdgpu_dpm_set_power_state()
984 level = adev->pm.dpm.forced_level; in amdgpu_dpm_get_performance_level()
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/linux/drivers/net/can/
H A Djanz-ican3.c229 void __iomem *dpm; member
316 peer = ioread8(mod->dpm + MSYNC_PEER); in ican3_old_recv_msg()
317 locl = ioread8(mod->dpm + MSYNC_LOCL); in ican3_old_recv_msg()
334 memcpy_fromio(msg, mod->dpm, sizeof(*msg)); in ican3_old_recv_msg()
343 iowrite8(locl, mod->dpm + MSYNC_LOCL); in ican3_old_recv_msg()
361 peer = ioread8(mod->dpm + MSYNC_PEER); in ican3_old_send_msg()
362 locl = ioread8(mod->dpm + MSYNC_LOCL); in ican3_old_send_msg()
376 memcpy_toio(mod->dpm, msg, sizeof(*msg)); in ican3_old_send_msg()
383 iowrite8(locl, mod->dpm + MSYNC_LOCL); in ican3_old_send_msg()
406 dst = mod->dpm; in ican3_init_new_host_interface()
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