Lines Matching refs:dpm
77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
369 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
793 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
895 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
968 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
1029 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1095 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1154 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1221 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1233 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1364 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1366 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1378 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1380 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1405 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_disable()
1503 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1539 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
1555 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_update_vce_dpm()
1589 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_update_samu_dpm()
1641 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_update_acp_dpm()
1770 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1891 adev->pm.dpm.forced_level = level; in kv_dpm_force_performance_level()
1900 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in kv_dpm_pre_set_power_state()
2047 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_patch_voltage_values()
2049 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_patch_voltage_values()
2051 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_patch_voltage_values()
2053 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_patch_voltage_values()
2166 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2207 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2210 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2213 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2214 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2240 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in kv_apply_state_adjust_rules()
2241 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in kv_apply_state_adjust_rules()
2302 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2344 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2361 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2411 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
2535 adev->pm.dpm.thermal.min_temp = low_temp; in kv_set_thermal_temperature_range()
2536 adev->pm.dpm.thermal.max_temp = high_temp; in kv_set_thermal_temperature_range()
2609 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in kv_parse_sys_info_table()
2664 adev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2668 adev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2727 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in kv_parse_power_table()
2730 if (!adev->pm.dpm.ps) in kv_parse_power_table()
2742 adev->pm.dpm.ps[i].ps_priv = ps; in kv_parse_power_table()
2755 &adev->pm.dpm.ps[i], k, in kv_parse_power_table()
2759 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in kv_parse_power_table()
2764 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
2767 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in kv_parse_power_table()
2769 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in kv_parse_power_table()
2774 adev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2775 adev->pm.dpm.vce_states[i].mclk = 0; in kv_parse_power_table()
2789 adev->pm.dpm.priv = pi; in kv_dpm_init()
2907 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in kv_dpm_fini()
2908 kfree(adev->pm.dpm.ps[i].ps_priv); in kv_dpm_fini()
2910 kfree(adev->pm.dpm.ps); in kv_dpm_fini()
2911 kfree(adev->pm.dpm.priv); in kv_dpm_fini()
2989 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
2994 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
2999 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3000 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3001 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; in kv_dpm_sw_init()
3011 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in kv_dpm_sw_init()
3015 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_sw_init()
3032 flush_work(&adev->pm.dpm.thermal.work); in kv_dpm_sw_fini()
3074 cancel_work_sync(&adev->pm.dpm.thermal.work); in kv_dpm_suspend()
3082 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_suspend()
3177 adev->pm.dpm.thermal.high_to_low = false; in kv_dpm_process_interrupt()
3182 adev->pm.dpm.thermal.high_to_low = true; in kv_dpm_process_interrupt()
3190 schedule_work(&adev->pm.dpm.thermal.work); in kv_dpm_process_interrupt()
3359 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in kv_dpm_set_irq_funcs()
3360 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; in kv_dpm_set_irq_funcs()